PlatformIO package of the Teensy core framework compatible with GCC 10 & C++20
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wiring.cpp 6.7KB

3 years ago
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  1. #define FASTLED_INTERNAL
  2. #include "FastLED.h"
  3. FASTLED_USING_NAMESPACE
  4. #if 0
  5. #if defined(FASTLED_AVR) && !defined(TEENSYDUINO) && !defined(LIB8_ATTINY)
  6. extern "C" {
  7. // the prescaler is set so that timer0 ticks every 64 clock cycles, and the
  8. // the overflow handler is called every 256 ticks.
  9. #define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
  10. typedef union { unsigned long _long; uint8_t raw[4]; } tBytesForLong;
  11. // tBytesForLong FastLED_timer0_overflow_count;
  12. volatile unsigned long FastLED_timer0_overflow_count=0;
  13. volatile unsigned long FastLED_timer0_millis = 0;
  14. LIB8STATIC void __attribute__((always_inline)) fastinc32 (volatile uint32_t & _long) {
  15. uint8_t b = ++((tBytesForLong&)_long).raw[0];
  16. if(!b) {
  17. b = ++((tBytesForLong&)_long).raw[1];
  18. if(!b) {
  19. b = ++((tBytesForLong&)_long).raw[2];
  20. if(!b) {
  21. ++((tBytesForLong&)_long).raw[3];
  22. }
  23. }
  24. }
  25. }
  26. #if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
  27. ISR(TIM0_OVF_vect)
  28. #else
  29. ISR(TIMER0_OVF_vect)
  30. #endif
  31. {
  32. fastinc32(FastLED_timer0_overflow_count);
  33. // FastLED_timer0_overflow_count++;
  34. }
  35. // there are 1024 microseconds per overflow counter tick.
  36. unsigned long millis()
  37. {
  38. unsigned long m;
  39. uint8_t oldSREG = SREG;
  40. // disable interrupts while we read FastLED_timer0_millis or we might get an
  41. // inconsistent value (e.g. in the middle of a write to FastLED_timer0_millis)
  42. cli();
  43. m = FastLED_timer0_overflow_count; //._long;
  44. SREG = oldSREG;
  45. return (m*(MICROSECONDS_PER_TIMER0_OVERFLOW/8))/(1000/8);
  46. }
  47. unsigned long micros() {
  48. unsigned long m;
  49. uint8_t oldSREG = SREG, t;
  50. cli();
  51. m = FastLED_timer0_overflow_count; // ._long;
  52. #if defined(TCNT0)
  53. t = TCNT0;
  54. #elif defined(TCNT0L)
  55. t = TCNT0L;
  56. #else
  57. #error TIMER 0 not defined
  58. #endif
  59. #ifdef TIFR0
  60. if ((TIFR0 & _BV(TOV0)) && (t < 255))
  61. m++;
  62. #else
  63. if ((TIFR & _BV(TOV0)) && (t < 255))
  64. m++;
  65. #endif
  66. SREG = oldSREG;
  67. return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
  68. }
  69. void delay(unsigned long ms)
  70. {
  71. uint16_t start = (uint16_t)micros();
  72. while (ms > 0) {
  73. if (((uint16_t)micros() - start) >= 1000) {
  74. ms--;
  75. start += 1000;
  76. }
  77. }
  78. }
  79. #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
  80. void init()
  81. {
  82. // this needs to be called before setup() or some functions won't
  83. // work there
  84. sei();
  85. // on the ATmega168, timer 0 is also used for fast hardware pwm
  86. // (using phase-correct PWM would mean that timer 0 overflowed half as often
  87. // resulting in different millis() behavior on the ATmega8 and ATmega168)
  88. #if defined(TCCR0A) && defined(WGM01)
  89. sbi(TCCR0A, WGM01);
  90. sbi(TCCR0A, WGM00);
  91. #endif
  92. // set timer 0 prescale factor to 64
  93. #if defined(__AVR_ATmega128__)
  94. // CPU specific: different values for the ATmega128
  95. sbi(TCCR0, CS02);
  96. #elif defined(TCCR0) && defined(CS01) && defined(CS00)
  97. // this combination is for the standard atmega8
  98. sbi(TCCR0, CS01);
  99. sbi(TCCR0, CS00);
  100. #elif defined(TCCR0B) && defined(CS01) && defined(CS00)
  101. // this combination is for the standard 168/328/1280/2560
  102. sbi(TCCR0B, CS01);
  103. sbi(TCCR0B, CS00);
  104. #elif defined(TCCR0A) && defined(CS01) && defined(CS00)
  105. // this combination is for the __AVR_ATmega645__ series
  106. sbi(TCCR0A, CS01);
  107. sbi(TCCR0A, CS00);
  108. #else
  109. #error Timer 0 prescale factor 64 not set correctly
  110. #endif
  111. // enable timer 0 overflow interrupt
  112. #if defined(TIMSK) && defined(TOIE0)
  113. sbi(TIMSK, TOIE0);
  114. #elif defined(TIMSK0) && defined(TOIE0)
  115. sbi(TIMSK0, TOIE0);
  116. #else
  117. #error Timer 0 overflow interrupt not set correctly
  118. #endif
  119. // timers 1 and 2 are used for phase-correct hardware pwm
  120. // this is better for motors as it ensures an even waveform
  121. // note, however, that fast pwm mode can achieve a frequency of up
  122. // 8 MHz (with a 16 MHz clock) at 50% duty cycle
  123. #if defined(TCCR1B) && defined(CS11) && defined(CS10)
  124. TCCR1B = 0;
  125. // set timer 1 prescale factor to 64
  126. sbi(TCCR1B, CS11);
  127. #if F_CPU >= 8000000L
  128. sbi(TCCR1B, CS10);
  129. #endif
  130. #elif defined(TCCR1) && defined(CS11) && defined(CS10)
  131. sbi(TCCR1, CS11);
  132. #if F_CPU >= 8000000L
  133. sbi(TCCR1, CS10);
  134. #endif
  135. #endif
  136. // put timer 1 in 8-bit phase correct pwm mode
  137. #if defined(TCCR1A) && defined(WGM10)
  138. sbi(TCCR1A, WGM10);
  139. #elif defined(TCCR1)
  140. #warning this needs to be finished
  141. #endif
  142. // set timer 2 prescale factor to 64
  143. #if defined(TCCR2) && defined(CS22)
  144. sbi(TCCR2, CS22);
  145. #elif defined(TCCR2B) && defined(CS22)
  146. sbi(TCCR2B, CS22);
  147. #else
  148. #warning Timer 2 not finished (may not be present on this CPU)
  149. #endif
  150. // configure timer 2 for phase correct pwm (8-bit)
  151. #if defined(TCCR2) && defined(WGM20)
  152. sbi(TCCR2, WGM20);
  153. #elif defined(TCCR2A) && defined(WGM20)
  154. sbi(TCCR2A, WGM20);
  155. #else
  156. #warning Timer 2 not finished (may not be present on this CPU)
  157. #endif
  158. #if defined(TCCR3B) && defined(CS31) && defined(WGM30)
  159. sbi(TCCR3B, CS31); // set timer 3 prescale factor to 64
  160. sbi(TCCR3B, CS30);
  161. sbi(TCCR3A, WGM30); // put timer 3 in 8-bit phase correct pwm mode
  162. #endif
  163. #if defined(TCCR4A) && defined(TCCR4B) && defined(TCCR4D) /* beginning of timer4 block for 32U4 and similar */
  164. sbi(TCCR4B, CS42); // set timer4 prescale factor to 64
  165. sbi(TCCR4B, CS41);
  166. sbi(TCCR4B, CS40);
  167. sbi(TCCR4D, WGM40); // put timer 4 in phase- and frequency-correct PWM mode
  168. sbi(TCCR4A, PWM4A); // enable PWM mode for comparator OCR4A
  169. sbi(TCCR4C, PWM4D); // enable PWM mode for comparator OCR4D
  170. #else /* beginning of timer4 block for ATMEGA1280 and ATMEGA2560 */
  171. #if defined(TCCR4B) && defined(CS41) && defined(WGM40)
  172. sbi(TCCR4B, CS41); // set timer 4 prescale factor to 64
  173. sbi(TCCR4B, CS40);
  174. sbi(TCCR4A, WGM40); // put timer 4 in 8-bit phase correct pwm mode
  175. #endif
  176. #endif /* end timer4 block for ATMEGA1280/2560 and similar */
  177. #if defined(TCCR5B) && defined(CS51) && defined(WGM50)
  178. sbi(TCCR5B, CS51); // set timer 5 prescale factor to 64
  179. sbi(TCCR5B, CS50);
  180. sbi(TCCR5A, WGM50); // put timer 5 in 8-bit phase correct pwm mode
  181. #endif
  182. #if defined(ADCSRA)
  183. // set a2d prescale factor to 128
  184. // 16 MHz / 128 = 125 KHz, inside the desired 50-200 KHz range.
  185. // XXX: this will not work properly for other clock speeds, and
  186. // this code should use F_CPU to determine the prescale factor.
  187. sbi(ADCSRA, ADPS2);
  188. sbi(ADCSRA, ADPS1);
  189. sbi(ADCSRA, ADPS0);
  190. // enable a2d conversions
  191. sbi(ADCSRA, ADEN);
  192. #endif
  193. // the bootloader connects pins 0 and 1 to the USART; disconnect them
  194. // here so they can be used as normal digital i/o; they will be
  195. // reconnected in Serial.begin()
  196. #if defined(UCSRB)
  197. UCSRB = 0;
  198. #elif defined(UCSR0B)
  199. UCSR0B = 0;
  200. #endif
  201. }
  202. };
  203. #endif
  204. #endif