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PlatformIO package of the Teensy core framework compatible with GCC 10 & C++20
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framework-arduinoteensy-cxx20/cores/teensy4/cmsis_gcc.h

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  1. /**************************************************************************//**

  2.  * @file     cmsis_gcc.h

  3.  * @brief    CMSIS compiler GCC header file

  4.  * @version  V5.3.0

  5.  * @date     26. March 2020

  6.  ******************************************************************************/

  7. /*

  8.  * Copyright (c) 2009-2020 Arm Limited. All rights reserved.

  9.  *

  10.  * SPDX-License-Identifier: Apache-2.0

  11.  *

  12.  * Licensed under the Apache License, Version 2.0 (the License); you may

  13.  * not use this file except in compliance with the License.

  14.  * You may obtain a copy of the License at

  15.  *

  16.  * www.apache.org/licenses/LICENSE-2.0

  17.  *

  18.  * Unless required by applicable law or agreed to in writing, software

  19.  * distributed under the License is distributed on an AS IS BASIS, WITHOUT

  20.  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

  21.  * See the License for the specific language governing permissions and

  22.  * limitations under the License.

  23.  */

  24. 

  25. #ifndef __CMSIS_GCC_H

  26. #define __CMSIS_GCC_H

  27. 

  28. /* ignore some GCC warnings */

  29. #pragma GCC diagnostic push

  30. #pragma GCC diagnostic ignored "-Wsign-conversion"

  31. #pragma GCC diagnostic ignored "-Wconversion"

  32. #pragma GCC diagnostic ignored "-Wunused-parameter"

  33. 

  34. /* Fallback for __has_builtin */

  35. #ifndef __has_builtin

  36.   #define __has_builtin(x) (0)

  37. #endif

  38. 

  39. #ifdef TEENSYDUINO

  40. #include <irq.h>

  41. #endif

  42. 

  43. /* CMSIS compiler specific defines */

  44. #ifndef   __ASM

  45.   #define __ASM                                  __asm

  46. #endif

  47. #ifndef   __INLINE

  48.   #define __INLINE                               inline

  49. #endif

  50. #ifndef   __STATIC_INLINE

  51.   #define __STATIC_INLINE                        static inline

  52. #endif

  53. #ifndef   __STATIC_FORCEINLINE

  54.   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline

  55. #endif

  56. #ifndef   __NO_RETURN

  57.   #define __NO_RETURN                            __attribute__((__noreturn__))

  58. #endif

  59. #ifndef   __USED

  60.   #define __USED                                 __attribute__((used))

  61. #endif

  62. #ifndef   __WEAK

  63.   #define __WEAK                                 __attribute__((weak))

  64. #endif

  65. #ifndef   __PACKED

  66.   #define __PACKED                               __attribute__((packed, aligned(1)))

  67. #endif

  68. #ifndef   __PACKED_STRUCT

  69.   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))

  70. #endif

  71. #ifndef   __PACKED_UNION

  72.   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))

  73. #endif

  74. #ifndef   __UNALIGNED_UINT32        /* deprecated */

  75.   #pragma GCC diagnostic push

  76.   #pragma GCC diagnostic ignored "-Wpacked"

  77.   #pragma GCC diagnostic ignored "-Wattributes"

  78.   struct __attribute__((packed)) T_UINT32 { uint32_t v; };

  79.   #pragma GCC diagnostic pop

  80.   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)

  81. #endif

  82. #ifndef   __UNALIGNED_UINT16_WRITE

  83.   #pragma GCC diagnostic push

  84.   #pragma GCC diagnostic ignored "-Wpacked"

  85.   #pragma GCC diagnostic ignored "-Wattributes"

  86.   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };

  87.   #pragma GCC diagnostic pop

  88.   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))

  89. #endif

  90. #ifndef   __UNALIGNED_UINT16_READ

  91.   #pragma GCC diagnostic push

  92.   #pragma GCC diagnostic ignored "-Wpacked"

  93.   #pragma GCC diagnostic ignored "-Wattributes"

  94.   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };

  95.   #pragma GCC diagnostic pop

  96.   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)

  97. #endif

  98. #ifndef   __UNALIGNED_UINT32_WRITE

  99.   #pragma GCC diagnostic push

  100.   #pragma GCC diagnostic ignored "-Wpacked"

  101.   #pragma GCC diagnostic ignored "-Wattributes"

  102.   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };

  103.   #pragma GCC diagnostic pop

  104.   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))

  105. #endif

  106. #ifndef   __UNALIGNED_UINT32_READ

  107.   #pragma GCC diagnostic push

  108.   #pragma GCC diagnostic ignored "-Wpacked"

  109.   #pragma GCC diagnostic ignored "-Wattributes"

  110.   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };

  111.   #pragma GCC diagnostic pop

  112.   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)

  113. #endif

  114. #ifndef   __ALIGNED

  115.   #define __ALIGNED(x)                           __attribute__((aligned(x)))

  116. #endif

  117. #ifndef   __RESTRICT

  118.   #define __RESTRICT                             __restrict

  119. #endif

  120. #ifndef   __COMPILER_BARRIER

  121.   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")

  122. #endif

  123. 

  124. /* #########################  Startup and Lowlevel Init  ######################## */

  125. 

  126. #ifndef __PROGRAM_START

  127. 

  128. /**

  129.   \brief   Initializes data and bss sections

  130.   \details This default implementations initialized all data and additional bss

  131.            sections relying on .copy.table and .zero.table specified properly

  132.            in the used linker script.

  133. 

  134.  */

  135. __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)

  136. {

  137.   extern void _start(void) __NO_RETURN;

  138. 

  139.   typedef struct {

  140.     uint32_t const* src;

  141.     uint32_t* dest;

  142.     uint32_t  wlen;

  143.   } __copy_table_t;

  144. 

  145.   typedef struct {

  146.     uint32_t* dest;

  147.     uint32_t  wlen;

  148.   } __zero_table_t;

  149. 

  150.   extern const __copy_table_t __copy_table_start__;

  151.   extern const __copy_table_t __copy_table_end__;

  152.   extern const __zero_table_t __zero_table_start__;

  153.   extern const __zero_table_t __zero_table_end__;

  154. 

  155.   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {

  156.     for(uint32_t i=0u; i<pTable->wlen; ++i) {

  157.       pTable->dest[i] = pTable->src[i];

  158.     }

  159.   }

  160. 

  161.   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {

  162.     for(uint32_t i=0u; i<pTable->wlen; ++i) {

  163.       pTable->dest[i] = 0u;

  164.     }

  165.   }

  166. 

  167.   _start();

  168. }

  169. 

  170. #define __PROGRAM_START           __cmsis_start

  171. #endif

  172. 

  173. #ifndef __INITIAL_SP

  174. #define __INITIAL_SP              __StackTop

  175. #endif

  176. 

  177. #ifndef __STACK_LIMIT

  178. #define __STACK_LIMIT             __StackLimit

  179. #endif

  180. 

  181. #ifndef __VECTOR_TABLE

  182. #define __VECTOR_TABLE            __Vectors

  183. #endif

  184. 

  185. #ifndef __VECTOR_TABLE_ATTRIBUTE

  186. #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))

  187. #endif

  188. 

  189. /* ###########################  Core Function Access  ########################### */

  190. /** \ingroup  CMSIS_Core_FunctionInterface

  191.     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

  192.   @{

  193.  */

  194. 

  195. #ifndef TEENSYDUINO

  196. 

  197. /**

  198.   \brief   Enable IRQ Interrupts

  199.   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

  200.            Can only be executed in Privileged modes.

  201.  */

  202. __STATIC_FORCEINLINE void __enable_irq(void)

  203. {

  204.   __ASM volatile ("cpsie i" : : : "memory");

  205. }

  206. 

  207. 

  208. /**

  209.   \brief   Disable IRQ Interrupts

  210.   \details Disables IRQ interrupts by setting the I-bit in the CPSR.

  211.            Can only be executed in Privileged modes.

  212.  */

  213. __STATIC_FORCEINLINE void __disable_irq(void)

  214. {

  215.   __ASM volatile ("cpsid i" : : : "memory");

  216. }

  217. 

  218. #endif

  219. 

  220. 

  221. /**

  222.   \brief   Get Control Register

  223.   \details Returns the content of the Control Register.

  224.   \return               Control Register value

  225.  */

  226. __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)

  227. {

  228.   uint32_t result;

  229. 

  230.   __ASM volatile ("MRS %0, control" : "=r" (result) );

  231.   return(result);

  232. }

  233. 

  234. 

  235. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  236. /**

  237.   \brief   Get Control Register (non-secure)

  238.   \details Returns the content of the non-secure Control Register when in secure mode.

  239.   \return               non-secure Control Register value

  240.  */

  241. __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)

  242. {

  243.   uint32_t result;

  244. 

  245.   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

  246.   return(result);

  247. }

  248. #endif

  249. 

  250. 

  251. /**

  252.   \brief   Set Control Register

  253.   \details Writes the given value to the Control Register.

  254.   \param [in]    control  Control Register value to set

  255.  */

  256. __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)

  257. {

  258.   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

  259. }

  260. 

  261. 

  262. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  263. /**

  264.   \brief   Set Control Register (non-secure)

  265.   \details Writes the given value to the non-secure Control Register when in secure state.

  266.   \param [in]    control  Control Register value to set

  267.  */

  268. __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)

  269. {

  270.   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

  271. }

  272. #endif

  273. 

  274. 

  275. /**

  276.   \brief   Get IPSR Register

  277.   \details Returns the content of the IPSR Register.

  278.   \return               IPSR Register value

  279.  */

  280. __STATIC_FORCEINLINE uint32_t __get_IPSR(void)

  281. {

  282.   uint32_t result;

  283. 

  284.   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

  285.   return(result);

  286. }

  287. 

  288. 

  289. /**

  290.   \brief   Get APSR Register

  291.   \details Returns the content of the APSR Register.

  292.   \return               APSR Register value

  293.  */

  294. __STATIC_FORCEINLINE uint32_t __get_APSR(void)

  295. {

  296.   uint32_t result;

  297. 

  298.   __ASM volatile ("MRS %0, apsr" : "=r" (result) );

  299.   return(result);

  300. }

  301. 

  302. 

  303. /**

  304.   \brief   Get xPSR Register

  305.   \details Returns the content of the xPSR Register.

  306.   \return               xPSR Register value

  307.  */

  308. __STATIC_FORCEINLINE uint32_t __get_xPSR(void)

  309. {

  310.   uint32_t result;

  311. 

  312.   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

  313.   return(result);

  314. }

  315. 

  316. 

  317. /**

  318.   \brief   Get Process Stack Pointer

  319.   \details Returns the current value of the Process Stack Pointer (PSP).

  320.   \return               PSP Register value

  321.  */

  322. __STATIC_FORCEINLINE uint32_t __get_PSP(void)

  323. {

  324.   uint32_t result;

  325. 

  326.   __ASM volatile ("MRS %0, psp"  : "=r" (result) );

  327.   return(result);

  328. }

  329. 

  330. 

  331. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  332. /**

  333.   \brief   Get Process Stack Pointer (non-secure)

  334.   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

  335.   \return               PSP Register value

  336.  */

  337. __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)

  338. {

  339.   uint32_t result;

  340. 

  341.   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

  342.   return(result);

  343. }

  344. #endif

  345. 

  346. 

  347. /**

  348.   \brief   Set Process Stack Pointer

  349.   \details Assigns the given value to the Process Stack Pointer (PSP).

  350.   \param [in]    topOfProcStack  Process Stack Pointer value to set

  351.  */

  352. __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)

  353. {

  354.   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );

  355. }

  356. 

  357. 

  358. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  359. /**

  360.   \brief   Set Process Stack Pointer (non-secure)

  361.   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

  362.   \param [in]    topOfProcStack  Process Stack Pointer value to set

  363.  */

  364. __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

  365. {

  366.   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );

  367. }

  368. #endif

  369. 

  370. 

  371. /**

  372.   \brief   Get Main Stack Pointer

  373.   \details Returns the current value of the Main Stack Pointer (MSP).

  374.   \return               MSP Register value

  375.  */

  376. __STATIC_FORCEINLINE uint32_t __get_MSP(void)

  377. {

  378.   uint32_t result;

  379. 

  380.   __ASM volatile ("MRS %0, msp" : "=r" (result) );

  381.   return(result);

  382. }

  383. 

  384. 

  385. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  386. /**

  387.   \brief   Get Main Stack Pointer (non-secure)

  388.   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

  389.   \return               MSP Register value

  390.  */

  391. __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)

  392. {

  393.   uint32_t result;

  394. 

  395.   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

  396.   return(result);

  397. }

  398. #endif

  399. 

  400. 

  401. /**

  402.   \brief   Set Main Stack Pointer

  403.   \details Assigns the given value to the Main Stack Pointer (MSP).

  404.   \param [in]    topOfMainStack  Main Stack Pointer value to set

  405.  */

  406. __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)

  407. {

  408.   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );

  409. }

  410. 

  411. 

  412. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  413. /**

  414.   \brief   Set Main Stack Pointer (non-secure)

  415.   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

  416.   \param [in]    topOfMainStack  Main Stack Pointer value to set

  417.  */

  418. __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

  419. {

  420.   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );

  421. }

  422. #endif

  423. 

  424. 

  425. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  426. /**

  427.   \brief   Get Stack Pointer (non-secure)

  428.   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

  429.   \return               SP Register value

  430.  */

  431. __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)

  432. {

  433.   uint32_t result;

  434. 

  435.   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );

  436.   return(result);

  437. }

  438. 

  439. 

  440. /**

  441.   \brief   Set Stack Pointer (non-secure)

  442.   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

  443.   \param [in]    topOfStack  Stack Pointer value to set

  444.  */

  445. __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)

  446. {

  447.   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );

  448. }

  449. #endif

  450. 

  451. 

  452. /**

  453.   \brief   Get Priority Mask

  454.   \details Returns the current state of the priority mask bit from the Priority Mask Register.

  455.   \return               Priority Mask value

  456.  */

  457. __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)

  458. {

  459.   uint32_t result;

  460. 

  461.   __ASM volatile ("MRS %0, primask" : "=r" (result) );

  462.   return(result);

  463. }

  464. 

  465. 

  466. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  467. /**

  468.   \brief   Get Priority Mask (non-secure)

  469.   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

  470.   \return               Priority Mask value

  471.  */

  472. __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)

  473. {

  474.   uint32_t result;

  475. 

  476.   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );

  477.   return(result);

  478. }

  479. #endif

  480. 

  481. 

  482. /**

  483.   \brief   Set Priority Mask

  484.   \details Assigns the given value to the Priority Mask Register.

  485.   \param [in]    priMask  Priority Mask

  486.  */

  487. __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)

  488. {

  489.   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

  490. }

  491. 

  492. 

  493. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  494. /**

  495.   \brief   Set Priority Mask (non-secure)

  496.   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

  497.   \param [in]    priMask  Priority Mask

  498.  */

  499. __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

  500. {

  501.   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

  502. }

  503. #endif

  504. 

  505. 

  506. #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  507.      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  508.      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

  509. /**

  510.   \brief   Enable FIQ

  511.   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

  512.            Can only be executed in Privileged modes.

  513.  */

  514. __STATIC_FORCEINLINE void __enable_fault_irq(void)

  515. {

  516.   __ASM volatile ("cpsie f" : : : "memory");

  517. }

  518. 

  519. 

  520. /**

  521.   \brief   Disable FIQ

  522.   \details Disables FIQ interrupts by setting the F-bit in the CPSR.

  523.            Can only be executed in Privileged modes.

  524.  */

  525. __STATIC_FORCEINLINE void __disable_fault_irq(void)

  526. {

  527.   __ASM volatile ("cpsid f" : : : "memory");

  528. }

  529. 

  530. 

  531. /**

  532.   \brief   Get Base Priority

  533.   \details Returns the current value of the Base Priority register.

  534.   \return               Base Priority register value

  535.  */

  536. __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)

  537. {

  538.   uint32_t result;

  539. 

  540.   __ASM volatile ("MRS %0, basepri" : "=r" (result) );

  541.   return(result);

  542. }

  543. 

  544. 

  545. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  546. /**

  547.   \brief   Get Base Priority (non-secure)

  548.   \details Returns the current value of the non-secure Base Priority register when in secure state.

  549.   \return               Base Priority register value

  550.  */

  551. __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)

  552. {

  553.   uint32_t result;

  554. 

  555.   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

  556.   return(result);

  557. }

  558. #endif

  559. 

  560. 

  561. /**

  562.   \brief   Set Base Priority

  563.   \details Assigns the given value to the Base Priority register.

  564.   \param [in]    basePri  Base Priority value to set

  565.  */

  566. __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)

  567. {

  568.   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");

  569. }

  570. 

  571. 

  572. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  573. /**

  574.   \brief   Set Base Priority (non-secure)

  575.   \details Assigns the given value to the non-secure Base Priority register when in secure state.

  576.   \param [in]    basePri  Base Priority value to set

  577.  */

  578. __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)

  579. {

  580.   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");

  581. }

  582. #endif

  583. 

  584. 

  585. /**

  586.   \brief   Set Base Priority with condition

  587.   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

  588.            or the new value increases the BASEPRI priority level.

  589.   \param [in]    basePri  Base Priority value to set

  590.  */

  591. __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)

  592. {

  593.   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");

  594. }

  595. 

  596. 

  597. /**

  598.   \brief   Get Fault Mask

  599.   \details Returns the current value of the Fault Mask register.

  600.   \return               Fault Mask register value

  601.  */

  602. __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)

  603. {

  604.   uint32_t result;

  605. 

  606.   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

  607.   return(result);

  608. }

  609. 

  610. 

  611. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  612. /**

  613.   \brief   Get Fault Mask (non-secure)

  614.   \details Returns the current value of the non-secure Fault Mask register when in secure state.

  615.   \return               Fault Mask register value

  616.  */

  617. __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)

  618. {

  619.   uint32_t result;

  620. 

  621.   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

  622.   return(result);

  623. }

  624. #endif

  625. 

  626. 

  627. /**

  628.   \brief   Set Fault Mask

  629.   \details Assigns the given value to the Fault Mask register.

  630.   \param [in]    faultMask  Fault Mask value to set

  631.  */

  632. __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)

  633. {

  634.   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

  635. }

  636. 

  637. 

  638. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

  639. /**

  640.   \brief   Set Fault Mask (non-secure)

  641.   \details Assigns the given value to the non-secure Fault Mask register when in secure state.

  642.   \param [in]    faultMask  Fault Mask value to set

  643.  */

  644. __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

  645. {

  646.   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

  647. }

  648. #endif

  649. 

  650. #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  651.            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  652.            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

  653. 

  654. 

  655. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  656.      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

  657. 

  658. /**

  659.   \brief   Get Process Stack Pointer Limit

  660.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  661.   Stack Pointer Limit register hence zero is returned always in non-secure

  662.   mode.

  663. 

  664.   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

  665.   \return               PSPLIM Register value

  666.  */

  667. __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)

  668. {

  669. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

  670.     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

  671.     // without main extensions, the non-secure PSPLIM is RAZ/WI

  672.   return 0U;

  673. #else

  674.   uint32_t result;

  675.   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

  676.   return result;

  677. #endif

  678. }

  679. 

  680. #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))

  681. /**

  682.   \brief   Get Process Stack Pointer Limit (non-secure)

  683.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  684.   Stack Pointer Limit register hence zero is returned always.

  685. 

  686.   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

  687.   \return               PSPLIM Register value

  688.  */

  689. __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)

  690. {

  691. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

  692.   // without main extensions, the non-secure PSPLIM is RAZ/WI

  693.   return 0U;

  694. #else

  695.   uint32_t result;

  696.   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

  697.   return result;

  698. #endif

  699. }

  700. #endif

  701. 

  702. 

  703. /**

  704.   \brief   Set Process Stack Pointer Limit

  705.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  706.   Stack Pointer Limit register hence the write is silently ignored in non-secure

  707.   mode.

  708. 

  709.   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

  710.   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

  711.  */

  712. __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

  713. {

  714. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

  715.     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

  716.   // without main extensions, the non-secure PSPLIM is RAZ/WI

  717.   (void)ProcStackPtrLimit;

  718. #else

  719.   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

  720. #endif

  721. }

  722. 

  723. 

  724. #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

  725. /**

  726.   \brief   Set Process Stack Pointer (non-secure)

  727.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  728.   Stack Pointer Limit register hence the write is silently ignored.

  729. 

  730.   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

  731.   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

  732.  */

  733. __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

  734. {

  735. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

  736.   // without main extensions, the non-secure PSPLIM is RAZ/WI

  737.   (void)ProcStackPtrLimit;

  738. #else

  739.   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

  740. #endif

  741. }

  742. #endif

  743. 

  744. 

  745. /**

  746.   \brief   Get Main Stack Pointer Limit

  747.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  748.   Stack Pointer Limit register hence zero is returned always in non-secure

  749.   mode.

  750. 

  751.   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

  752.   \return               MSPLIM Register value

  753.  */

  754. __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)

  755. {

  756. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

  757.     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

  758.   // without main extensions, the non-secure MSPLIM is RAZ/WI

  759.   return 0U;

  760. #else

  761.   uint32_t result;

  762.   __ASM volatile ("MRS %0, msplim" : "=r" (result) );

  763.   return result;

  764. #endif

  765. }

  766. 

  767. 

  768. #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

  769. /**

  770.   \brief   Get Main Stack Pointer Limit (non-secure)

  771.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  772.   Stack Pointer Limit register hence zero is returned always.

  773. 

  774.   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

  775.   \return               MSPLIM Register value

  776.  */

  777. __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)

  778. {

  779. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

  780.   // without main extensions, the non-secure MSPLIM is RAZ/WI

  781.   return 0U;

  782. #else

  783.   uint32_t result;

  784.   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

  785.   return result;

  786. #endif

  787. }

  788. #endif

  789. 

  790. 

  791. /**

  792.   \brief   Set Main Stack Pointer Limit

  793.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  794.   Stack Pointer Limit register hence the write is silently ignored in non-secure

  795.   mode.

  796. 

  797.   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

  798.   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

  799.  */

  800. __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

  801. {

  802. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

  803.     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

  804.   // without main extensions, the non-secure MSPLIM is RAZ/WI

  805.   (void)MainStackPtrLimit;

  806. #else

  807.   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

  808. #endif

  809. }

  810. 

  811. 

  812. #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

  813. /**

  814.   \brief   Set Main Stack Pointer Limit (non-secure)

  815.   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

  816.   Stack Pointer Limit register hence the write is silently ignored.

  817. 

  818.   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

  819.   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

  820.  */

  821. __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

  822. {

  823. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

  824.   // without main extensions, the non-secure MSPLIM is RAZ/WI

  825.   (void)MainStackPtrLimit;

  826. #else

  827.   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

  828. #endif

  829. }

  830. #endif

  831. 

  832. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  833.            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

  834. 

  835. 

  836. /**

  837.   \brief   Get FPSCR

  838.   \details Returns the current value of the Floating Point Status/Control register.

  839.   \return               Floating Point Status/Control register value

  840.  */

  841. __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)

  842. {

  843. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

  844.      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

  845. #if __has_builtin(__builtin_arm_get_fpscr)

  846. // Re-enable using built-in when GCC has been fixed

  847. // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

  848.   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

  849.   return __builtin_arm_get_fpscr();

  850. #else

  851.   uint32_t result;

  852. 

  853.   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

  854.   return(result);

  855. #endif

  856. #else

  857.   return(0U);

  858. #endif

  859. }

  860. 

  861. 

  862. /**

  863.   \brief   Set FPSCR

  864.   \details Assigns the given value to the Floating Point Status/Control register.

  865.   \param [in]    fpscr  Floating Point Status/Control value to set

  866.  */

  867. __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)

  868. {

  869. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

  870.      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

  871. #if __has_builtin(__builtin_arm_set_fpscr)

  872. // Re-enable using built-in when GCC has been fixed

  873. // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

  874.   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

  875.   __builtin_arm_set_fpscr(fpscr);

  876. #else

  877.   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");

  878. #endif

  879. #else

  880.   (void)fpscr;

  881. #endif

  882. }

  883. 

  884. 

  885. /*@} end of CMSIS_Core_RegAccFunctions */

  886. 

  887. 

  888. /* ##########################  Core Instruction Access  ######################### */

  889. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

  890.   Access to dedicated instructions

  891.   @{

  892. */

  893. 

  894. /* Define macros for porting to both thumb1 and thumb2.

  895.  * For thumb1, use low register (r0-r7), specified by constraint "l"

  896.  * Otherwise, use general registers, specified by constraint "r" */

  897. #if defined (__thumb__) && !defined (__thumb2__)

  898. #define __CMSIS_GCC_OUT_REG(r) "=l" (r)

  899. #define __CMSIS_GCC_RW_REG(r) "+l" (r)

  900. #define __CMSIS_GCC_USE_REG(r) "l" (r)

  901. #else

  902. #define __CMSIS_GCC_OUT_REG(r) "=r" (r)

  903. #define __CMSIS_GCC_RW_REG(r) "+r" (r)

  904. #define __CMSIS_GCC_USE_REG(r) "r" (r)

  905. #endif

  906. 

  907. /**

  908.   \brief   No Operation

  909.   \details No Operation does nothing. This instruction can be used for code alignment purposes.

  910.  */

  911. #define __NOP()                             __ASM volatile ("nop")

  912. 

  913. /**

  914.   \brief   Wait For Interrupt

  915.   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

  916.  */

  917. #define __WFI()                             __ASM volatile ("wfi":::"memory")

  918. 

  919. 

  920. /**

  921.   \brief   Wait For Event

  922.   \details Wait For Event is a hint instruction that permits the processor to enter

  923.            a low-power state until one of a number of events occurs.

  924.  */

  925. #define __WFE()                             __ASM volatile ("wfe":::"memory")

  926. 

  927. 

  928. /**

  929.   \brief   Send Event

  930.   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

  931.  */

  932. #define __SEV()                             __ASM volatile ("sev")

  933. 

  934. 

  935. /**

  936.   \brief   Instruction Synchronization Barrier

  937.   \details Instruction Synchronization Barrier flushes the pipeline in the processor,

  938.            so that all instructions following the ISB are fetched from cache or memory,

  939.            after the instruction has been completed.

  940.  */

  941. __STATIC_FORCEINLINE void __ISB(void)

  942. {

  943.   __ASM volatile ("isb 0xF":::"memory");

  944. }

  945. 

  946. 

  947. /**

  948.   \brief   Data Synchronization Barrier

  949.   \details Acts as a special kind of Data Memory Barrier.

  950.            It completes when all explicit memory accesses before this instruction complete.

  951.  */

  952. __STATIC_FORCEINLINE void __DSB(void)

  953. {

  954.   __ASM volatile ("dsb 0xF":::"memory");

  955. }

  956. 

  957. 

  958. /**

  959.   \brief   Data Memory Barrier

  960.   \details Ensures the apparent order of the explicit memory operations before

  961.            and after the instruction, without ensuring their completion.

  962.  */

  963. __STATIC_FORCEINLINE void __DMB(void)

  964. {

  965.   __ASM volatile ("dmb 0xF":::"memory");

  966. }

  967. 

  968. 

  969. /**

  970.   \brief   Reverse byte order (32 bit)

  971.   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

  972.   \param [in]    value  Value to reverse

  973.   \return               Reversed value

  974.  */

  975. __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)

  976. {

  977. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

  978.   return __builtin_bswap32(value);

  979. #else

  980.   uint32_t result;

  981. 

  982.   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

  983.   return result;

  984. #endif

  985. }

  986. 

  987. 

  988. /**

  989.   \brief   Reverse byte order (16 bit)

  990.   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

  991.   \param [in]    value  Value to reverse

  992.   \return               Reversed value

  993.  */

  994. __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)

  995. {

  996.   uint32_t result;

  997. 

  998.   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

  999.   return result;

  1000. }

  1001. 

  1002. 

  1003. /**

  1004.   \brief   Reverse byte order (16 bit)

  1005.   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

  1006.   \param [in]    value  Value to reverse

  1007.   \return               Reversed value

  1008.  */

  1009. __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)

  1010. {

  1011. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

  1012.   return (int16_t)__builtin_bswap16(value);

  1013. #else

  1014.   int16_t result;

  1015. 

  1016.   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

  1017.   return result;

  1018. #endif

  1019. }

  1020. 

  1021. 

  1022. /**

  1023.   \brief   Rotate Right in unsigned value (32 bit)

  1024.   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

  1025.   \param [in]    op1  Value to rotate

  1026.   \param [in]    op2  Number of Bits to rotate

  1027.   \return               Rotated value

  1028.  */

  1029. __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

  1030. {

  1031.   op2 %= 32U;

  1032.   if (op2 == 0U)

  1033.   {

  1034.     return op1;

  1035.   }

  1036.   return (op1 >> op2) | (op1 << (32U - op2));

  1037. }

  1038. 

  1039. 

  1040. /**

  1041.   \brief   Breakpoint

  1042.   \details Causes the processor to enter Debug state.

  1043.            Debug tools can use this to investigate system state when the instruction at a particular address is reached.

  1044.   \param [in]    value  is ignored by the processor.

  1045.                  If required, a debugger can use it to store additional information about the breakpoint.

  1046.  */

  1047. #define __BKPT(value)                       __ASM volatile ("bkpt "#value)

  1048. 

  1049. 

  1050. /**

  1051.   \brief   Reverse bit order of value

  1052.   \details Reverses the bit order of the given value.

  1053.   \param [in]    value  Value to reverse

  1054.   \return               Reversed value

  1055.  */

  1056. __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)

  1057. {

  1058.   uint32_t result;

  1059. 

  1060. #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1061.      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1062.      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

  1063.    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );

  1064. #else

  1065.   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */

  1066. 

  1067.   result = value;                      /* r will be reversed bits of v; first get LSB of v */

  1068.   for (value >>= 1U; value != 0U; value >>= 1U)

  1069.   {

  1070.     result <<= 1U;

  1071.     result |= value & 1U;

  1072.     s--;

  1073.   }

  1074.   result <<= s;                        /* shift when v's highest bits are zero */

  1075. #endif

  1076.   return result;

  1077. }

  1078. 

  1079. 

  1080. /**

  1081.   \brief   Count leading zeros

  1082.   \details Counts the number of leading zeros of a data value.

  1083.   \param [in]  value  Value to count the leading zeros

  1084.   \return             number of leading zeros in value

  1085.  */

  1086. __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)

  1087. {

  1088.   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally

  1089.      __builtin_clz(0) is undefined behaviour, so handle this case specially.

  1090.      This guarantees ARM-compatible results if happening to compile on a non-ARM

  1091.      target, and ensures the compiler doesn't decide to activate any

  1092.      optimisations using the logic "value was passed to __builtin_clz, so it

  1093.      is non-zero".

  1094.      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a

  1095.      single CLZ instruction.

  1096.    */

  1097.   if (value == 0U)

  1098.   {

  1099.     return 32U;

  1100.   }

  1101.   return __builtin_clz(value);

  1102. }

  1103. 

  1104. 

  1105. #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1106.      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1107.      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  1108.      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

  1109. /**

  1110.   \brief   LDR Exclusive (8 bit)

  1111.   \details Executes a exclusive LDR instruction for 8 bit value.

  1112.   \param [in]    ptr  Pointer to data

  1113.   \return             value of type uint8_t at (*ptr)

  1114.  */

  1115. __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)

  1116. {

  1117.     uint32_t result;

  1118. 

  1119. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

  1120.    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

  1121. #else

  1122.     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

  1123.        accepted by assembler. So has to use following less efficient pattern.

  1124.     */

  1125.    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

  1126. #endif

  1127.    return ((uint8_t) result);    /* Add explicit type cast here */

  1128. }

  1129. 

  1130. 

  1131. /**

  1132.   \brief   LDR Exclusive (16 bit)

  1133.   \details Executes a exclusive LDR instruction for 16 bit values.

  1134.   \param [in]    ptr  Pointer to data

  1135.   \return        value of type uint16_t at (*ptr)

  1136.  */

  1137. __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)

  1138. {

  1139.     uint32_t result;

  1140. 

  1141. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

  1142.    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

  1143. #else

  1144.     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

  1145.        accepted by assembler. So has to use following less efficient pattern.

  1146.     */

  1147.    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

  1148. #endif

  1149.    return ((uint16_t) result);    /* Add explicit type cast here */

  1150. }

  1151. 

  1152. 

  1153. /**

  1154.   \brief   LDR Exclusive (32 bit)

  1155.   \details Executes a exclusive LDR instruction for 32 bit values.

  1156.   \param [in]    ptr  Pointer to data

  1157.   \return        value of type uint32_t at (*ptr)

  1158.  */

  1159. __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)

  1160. {

  1161.     uint32_t result;

  1162. 

  1163.    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

  1164.    return(result);

  1165. }

  1166. 

  1167. 

  1168. /**

  1169.   \brief   STR Exclusive (8 bit)

  1170.   \details Executes a exclusive STR instruction for 8 bit values.

  1171.   \param [in]  value  Value to store

  1172.   \param [in]    ptr  Pointer to location

  1173.   \return          0  Function succeeded

  1174.   \return          1  Function failed

  1175.  */

  1176. __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

  1177. {

  1178.    uint32_t result;

  1179. 

  1180.    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

  1181.    return(result);

  1182. }

  1183. 

  1184. 

  1185. /**

  1186.   \brief   STR Exclusive (16 bit)

  1187.   \details Executes a exclusive STR instruction for 16 bit values.

  1188.   \param [in]  value  Value to store

  1189.   \param [in]    ptr  Pointer to location

  1190.   \return          0  Function succeeded

  1191.   \return          1  Function failed

  1192.  */

  1193. __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

  1194. {

  1195.    uint32_t result;

  1196. 

  1197.    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

  1198.    return(result);

  1199. }

  1200. 

  1201. 

  1202. /**

  1203.   \brief   STR Exclusive (32 bit)

  1204.   \details Executes a exclusive STR instruction for 32 bit values.

  1205.   \param [in]  value  Value to store

  1206.   \param [in]    ptr  Pointer to location

  1207.   \return          0  Function succeeded

  1208.   \return          1  Function failed

  1209.  */

  1210. __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

  1211. {

  1212.    uint32_t result;

  1213. 

  1214.    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

  1215.    return(result);

  1216. }

  1217. 

  1218. 

  1219. /**

  1220.   \brief   Remove the exclusive lock

  1221.   \details Removes the exclusive lock which is created by LDREX.

  1222.  */

  1223. __STATIC_FORCEINLINE void __CLREX(void)

  1224. {

  1225.   __ASM volatile ("clrex" ::: "memory");

  1226. }

  1227. 

  1228. #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1229.            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1230.            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  1231.            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

  1232. 

  1233. 

  1234. #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1235.      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1236.      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

  1237. /**

  1238.   \brief   Signed Saturate

  1239.   \details Saturates a signed value.

  1240.   \param [in]  ARG1  Value to be saturated

  1241.   \param [in]  ARG2  Bit position to saturate to (1..32)

  1242.   \return             Saturated value

  1243.  */

  1244. #define __SSAT(ARG1, ARG2) \

  1245. __extension__ \

  1246. ({                          \

  1247.   int32_t __RES, __ARG1 = (ARG1); \

  1248.   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

  1249.   __RES; \

  1250.  })

  1251. 

  1252. 

  1253. /**

  1254.   \brief   Unsigned Saturate

  1255.   \details Saturates an unsigned value.

  1256.   \param [in]  ARG1  Value to be saturated

  1257.   \param [in]  ARG2  Bit position to saturate to (0..31)

  1258.   \return             Saturated value

  1259.  */

  1260. #define __USAT(ARG1, ARG2) \

  1261.  __extension__ \

  1262. ({                          \

  1263.   uint32_t __RES, __ARG1 = (ARG1); \

  1264.   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

  1265.   __RES; \

  1266.  })

  1267. 

  1268. 

  1269. /**

  1270.   \brief   Rotate Right with Extend (32 bit)

  1271.   \details Moves each bit of a bitstring right by one bit.

  1272.            The carry input is shifted in at the left end of the bitstring.

  1273.   \param [in]    value  Value to rotate

  1274.   \return               Rotated value

  1275.  */

  1276. __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)

  1277. {

  1278.   uint32_t result;

  1279. 

  1280.   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

  1281.   return(result);

  1282. }

  1283. 

  1284. 

  1285. /**

  1286.   \brief   LDRT Unprivileged (8 bit)

  1287.   \details Executes a Unprivileged LDRT instruction for 8 bit value.

  1288.   \param [in]    ptr  Pointer to data

  1289.   \return             value of type uint8_t at (*ptr)

  1290.  */

  1291. __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)

  1292. {

  1293.     uint32_t result;

  1294. 

  1295. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

  1296.    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );

  1297. #else

  1298.     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

  1299.        accepted by assembler. So has to use following less efficient pattern.

  1300.     */

  1301.    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );

  1302. #endif

  1303.    return ((uint8_t) result);    /* Add explicit type cast here */

  1304. }

  1305. 

  1306. 

  1307. /**

  1308.   \brief   LDRT Unprivileged (16 bit)

  1309.   \details Executes a Unprivileged LDRT instruction for 16 bit values.

  1310.   \param [in]    ptr  Pointer to data

  1311.   \return        value of type uint16_t at (*ptr)

  1312.  */

  1313. __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)

  1314. {

  1315.     uint32_t result;

  1316. 

  1317. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

  1318.    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );

  1319. #else

  1320.     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

  1321.        accepted by assembler. So has to use following less efficient pattern.

  1322.     */

  1323.    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );

  1324. #endif

  1325.    return ((uint16_t) result);    /* Add explicit type cast here */

  1326. }

  1327. 

  1328. 

  1329. /**

  1330.   \brief   LDRT Unprivileged (32 bit)

  1331.   \details Executes a Unprivileged LDRT instruction for 32 bit values.

  1332.   \param [in]    ptr  Pointer to data

  1333.   \return        value of type uint32_t at (*ptr)

  1334.  */

  1335. __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)

  1336. {

  1337.     uint32_t result;

  1338. 

  1339.    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );

  1340.    return(result);

  1341. }

  1342. 

  1343. 

  1344. /**

  1345.   \brief   STRT Unprivileged (8 bit)

  1346.   \details Executes a Unprivileged STRT instruction for 8 bit values.

  1347.   \param [in]  value  Value to store

  1348.   \param [in]    ptr  Pointer to location

  1349.  */

  1350. __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)

  1351. {

  1352.    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

  1353. }

  1354. 

  1355. 

  1356. /**

  1357.   \brief   STRT Unprivileged (16 bit)

  1358.   \details Executes a Unprivileged STRT instruction for 16 bit values.

  1359.   \param [in]  value  Value to store

  1360.   \param [in]    ptr  Pointer to location

  1361.  */

  1362. __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)

  1363. {

  1364.    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

  1365. }

  1366. 

  1367. 

  1368. /**

  1369.   \brief   STRT Unprivileged (32 bit)

  1370.   \details Executes a Unprivileged STRT instruction for 32 bit values.

  1371.   \param [in]  value  Value to store

  1372.   \param [in]    ptr  Pointer to location

  1373.  */

  1374. __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)

  1375. {

  1376.    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );

  1377. }

  1378. 

  1379. #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1380.            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1381.            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

  1382. 

  1383. /**

  1384.   \brief   Signed Saturate

  1385.   \details Saturates a signed value.

  1386.   \param [in]  value  Value to be saturated

  1387.   \param [in]    sat  Bit position to saturate to (1..32)

  1388.   \return             Saturated value

  1389.  */

  1390. __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)

  1391. {

  1392.   if ((sat >= 1U) && (sat <= 32U))

  1393.   {

  1394.     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);

  1395.     const int32_t min = -1 - max ;

  1396.     if (val > max)

  1397.     {

  1398.       return max;

  1399.     }

  1400.     else if (val < min)

  1401.     {

  1402.       return min;

  1403.     }

  1404.   }

  1405.   return val;

  1406. }

  1407. 

  1408. /**

  1409.   \brief   Unsigned Saturate

  1410.   \details Saturates an unsigned value.

  1411.   \param [in]  value  Value to be saturated

  1412.   \param [in]    sat  Bit position to saturate to (0..31)

  1413.   \return             Saturated value

  1414.  */

  1415. __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)

  1416. {

  1417.   if (sat <= 31U)

  1418.   {

  1419.     const uint32_t max = ((1U << sat) - 1U);

  1420.     if (val > (int32_t)max)

  1421.     {

  1422.       return max;

  1423.     }

  1424.     else if (val < 0)

  1425.     {

  1426.       return 0U;

  1427.     }

  1428.   }

  1429.   return (uint32_t)val;

  1430. }

  1431. 

  1432. #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

  1433.            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

  1434.            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

  1435. 

  1436. 

  1437. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  1438.      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

  1439. /**

  1440.   \brief   Load-Acquire (8 bit)

  1441.   \details Executes a LDAB instruction for 8 bit value.

  1442.   \param [in]    ptr  Pointer to data

  1443.   \return             value of type uint8_t at (*ptr)

  1444.  */

  1445. __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)

  1446. {

  1447.     uint32_t result;

  1448. 

  1449.    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1450.    return ((uint8_t) result);

  1451. }

  1452. 

  1453. 

  1454. /**

  1455.   \brief   Load-Acquire (16 bit)

  1456.   \details Executes a LDAH instruction for 16 bit values.

  1457.   \param [in]    ptr  Pointer to data

  1458.   \return        value of type uint16_t at (*ptr)

  1459.  */

  1460. __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)

  1461. {

  1462.     uint32_t result;

  1463. 

  1464.    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1465.    return ((uint16_t) result);

  1466. }

  1467. 

  1468. 

  1469. /**

  1470.   \brief   Load-Acquire (32 bit)

  1471.   \details Executes a LDA instruction for 32 bit values.

  1472.   \param [in]    ptr  Pointer to data

  1473.   \return        value of type uint32_t at (*ptr)

  1474.  */

  1475. __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)

  1476. {

  1477.     uint32_t result;

  1478. 

  1479.    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1480.    return(result);

  1481. }

  1482. 

  1483. 

  1484. /**

  1485.   \brief   Store-Release (8 bit)

  1486.   \details Executes a STLB instruction for 8 bit values.

  1487.   \param [in]  value  Value to store

  1488.   \param [in]    ptr  Pointer to location

  1489.  */

  1490. __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)

  1491. {

  1492.    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1493. }

  1494. 

  1495. 

  1496. /**

  1497.   \brief   Store-Release (16 bit)

  1498.   \details Executes a STLH instruction for 16 bit values.

  1499.   \param [in]  value  Value to store

  1500.   \param [in]    ptr  Pointer to location

  1501.  */

  1502. __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)

  1503. {

  1504.    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1505. }

  1506. 

  1507. 

  1508. /**

  1509.   \brief   Store-Release (32 bit)

  1510.   \details Executes a STL instruction for 32 bit values.

  1511.   \param [in]  value  Value to store

  1512.   \param [in]    ptr  Pointer to location

  1513.  */

  1514. __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)

  1515. {

  1516.    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1517. }

  1518. 

  1519. 

  1520. /**

  1521.   \brief   Load-Acquire Exclusive (8 bit)

  1522.   \details Executes a LDAB exclusive instruction for 8 bit value.

  1523.   \param [in]    ptr  Pointer to data

  1524.   \return             value of type uint8_t at (*ptr)

  1525.  */

  1526. __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)

  1527. {

  1528.     uint32_t result;

  1529. 

  1530.    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1531.    return ((uint8_t) result);

  1532. }

  1533. 

  1534. 

  1535. /**

  1536.   \brief   Load-Acquire Exclusive (16 bit)

  1537.   \details Executes a LDAH exclusive instruction for 16 bit values.

  1538.   \param [in]    ptr  Pointer to data

  1539.   \return        value of type uint16_t at (*ptr)

  1540.  */

  1541. __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)

  1542. {

  1543.     uint32_t result;

  1544. 

  1545.    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1546.    return ((uint16_t) result);

  1547. }

  1548. 

  1549. 

  1550. /**

  1551.   \brief   Load-Acquire Exclusive (32 bit)

  1552.   \details Executes a LDA exclusive instruction for 32 bit values.

  1553.   \param [in]    ptr  Pointer to data

  1554.   \return        value of type uint32_t at (*ptr)

  1555.  */

  1556. __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)

  1557. {

  1558.     uint32_t result;

  1559. 

  1560.    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

  1561.    return(result);

  1562. }

  1563. 

  1564. 

  1565. /**

  1566.   \brief   Store-Release Exclusive (8 bit)

  1567.   \details Executes a STLB exclusive instruction for 8 bit values.

  1568.   \param [in]  value  Value to store

  1569.   \param [in]    ptr  Pointer to location

  1570.   \return          0  Function succeeded

  1571.   \return          1  Function failed

  1572.  */

  1573. __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)

  1574. {

  1575.    uint32_t result;

  1576. 

  1577.    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1578.    return(result);

  1579. }

  1580. 

  1581. 

  1582. /**

  1583.   \brief   Store-Release Exclusive (16 bit)

  1584.   \details Executes a STLH exclusive instruction for 16 bit values.

  1585.   \param [in]  value  Value to store

  1586.   \param [in]    ptr  Pointer to location

  1587.   \return          0  Function succeeded

  1588.   \return          1  Function failed

  1589.  */

  1590. __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)

  1591. {

  1592.    uint32_t result;

  1593. 

  1594.    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1595.    return(result);

  1596. }

  1597. 

  1598. 

  1599. /**

  1600.   \brief   Store-Release Exclusive (32 bit)

  1601.   \details Executes a STL exclusive instruction for 32 bit values.

  1602.   \param [in]  value  Value to store

  1603.   \param [in]    ptr  Pointer to location

  1604.   \return          0  Function succeeded

  1605.   \return          1  Function failed

  1606.  */

  1607. __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)

  1608. {

  1609.    uint32_t result;

  1610. 

  1611.    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

  1612.    return(result);

  1613. }

  1614. 

  1615. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

  1616.            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

  1617. 

  1618. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */

  1619. 

  1620. 

  1621. /* ###################  Compiler specific Intrinsics  ########################### */

  1622. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

  1623.   Access to dedicated SIMD instructions

  1624.   @{

  1625. */

  1626. 

  1627. #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))

  1628. 

  1629. __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

  1630. {

  1631.   uint32_t result;

  1632. 

  1633.   __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1634.   return(result);

  1635. }

  1636. 

  1637. __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

  1638. {

  1639.   uint32_t result;

  1640. 

  1641.   __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1642.   return(result);

  1643. }

  1644. 

  1645. __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

  1646. {

  1647.   uint32_t result;

  1648. 

  1649.   __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1650.   return(result);

  1651. }

  1652. 

  1653. __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

  1654. {

  1655.   uint32_t result;

  1656. 

  1657.   __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1658.   return(result);

  1659. }

  1660. 

  1661. __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

  1662. {

  1663.   uint32_t result;

  1664. 

  1665.   __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1666.   return(result);

  1667. }

  1668. 

  1669. __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

  1670. {

  1671.   uint32_t result;

  1672. 

  1673.   __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1674.   return(result);

  1675. }

  1676. 

  1677. 

  1678. __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

  1679. {

  1680.   uint32_t result;

  1681. 

  1682.   __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1683.   return(result);

  1684. }

  1685. 

  1686. __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

  1687. {

  1688.   uint32_t result;

  1689. 

  1690.   __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1691.   return(result);

  1692. }

  1693. 

  1694. __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

  1695. {

  1696.   uint32_t result;

  1697. 

  1698.   __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1699.   return(result);

  1700. }

  1701. 

  1702. __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

  1703. {

  1704.   uint32_t result;

  1705. 

  1706.   __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1707.   return(result);

  1708. }

  1709. 

  1710. __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

  1711. {

  1712.   uint32_t result;

  1713. 

  1714.   __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1715.   return(result);

  1716. }

  1717. 

  1718. __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

  1719. {

  1720.   uint32_t result;

  1721. 

  1722.   __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1723.   return(result);

  1724. }

  1725. 

  1726. 

  1727. __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

  1728. {

  1729.   uint32_t result;

  1730. 

  1731.   __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1732.   return(result);

  1733. }

  1734. 

  1735. __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

  1736. {

  1737.   uint32_t result;

  1738. 

  1739.   __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1740.   return(result);

  1741. }

  1742. 

  1743. __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

  1744. {

  1745.   uint32_t result;

  1746. 

  1747.   __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1748.   return(result);

  1749. }

  1750. 

  1751. __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

  1752. {

  1753.   uint32_t result;

  1754. 

  1755.   __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1756.   return(result);

  1757. }

  1758. 

  1759. __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

  1760. {

  1761.   uint32_t result;

  1762. 

  1763.   __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1764.   return(result);

  1765. }

  1766. 

  1767. __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

  1768. {

  1769.   uint32_t result;

  1770. 

  1771.   __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1772.   return(result);

  1773. }

  1774. 

  1775. __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

  1776. {

  1777.   uint32_t result;

  1778. 

  1779.   __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1780.   return(result);

  1781. }

  1782. 

  1783. __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

  1784. {

  1785.   uint32_t result;

  1786. 

  1787.   __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1788.   return(result);

  1789. }

  1790. 

  1791. __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

  1792. {

  1793.   uint32_t result;

  1794. 

  1795.   __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1796.   return(result);

  1797. }

  1798. 

  1799. __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

  1800. {

  1801.   uint32_t result;

  1802. 

  1803.   __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1804.   return(result);

  1805. }

  1806. 

  1807. __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

  1808. {

  1809.   uint32_t result;

  1810. 

  1811.   __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1812.   return(result);

  1813. }

  1814. 

  1815. __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

  1816. {

  1817.   uint32_t result;

  1818. 

  1819.   __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1820.   return(result);

  1821. }

  1822. 

  1823. __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

  1824. {

  1825.   uint32_t result;

  1826. 

  1827.   __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1828.   return(result);

  1829. }

  1830. 

  1831. __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

  1832. {

  1833.   uint32_t result;

  1834. 

  1835.   __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1836.   return(result);

  1837. }

  1838. 

  1839. __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

  1840. {

  1841.   uint32_t result;

  1842. 

  1843.   __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1844.   return(result);

  1845. }

  1846. 

  1847. __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

  1848. {

  1849.   uint32_t result;

  1850. 

  1851.   __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1852.   return(result);

  1853. }

  1854. 

  1855. __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

  1856. {

  1857.   uint32_t result;

  1858. 

  1859.   __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1860.   return(result);

  1861. }

  1862. 

  1863. __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

  1864. {

  1865.   uint32_t result;

  1866. 

  1867.   __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1868.   return(result);

  1869. }

  1870. 

  1871. __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

  1872. {

  1873.   uint32_t result;

  1874. 

  1875.   __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1876.   return(result);

  1877. }

  1878. 

  1879. __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

  1880. {

  1881.   uint32_t result;

  1882. 

  1883.   __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1884.   return(result);

  1885. }

  1886. 

  1887. __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

  1888. {

  1889.   uint32_t result;

  1890. 

  1891.   __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1892.   return(result);

  1893. }

  1894. 

  1895. __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

  1896. {

  1897.   uint32_t result;

  1898. 

  1899.   __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1900.   return(result);

  1901. }

  1902. 

  1903. __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

  1904. {

  1905.   uint32_t result;

  1906. 

  1907.   __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1908.   return(result);

  1909. }

  1910. 

  1911. __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

  1912. {

  1913.   uint32_t result;

  1914. 

  1915.   __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1916.   return(result);

  1917. }

  1918. 

  1919. __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

  1920. {

  1921.   uint32_t result;

  1922. 

  1923.   __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1924.   return(result);

  1925. }

  1926. 

  1927. __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

  1928. {

  1929.   uint32_t result;

  1930. 

  1931.   __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  1932.   return(result);

  1933. }

  1934. 

  1935. #define __SSAT16(ARG1, ARG2) \

  1936. ({                          \

  1937.   int32_t __RES, __ARG1 = (ARG1); \

  1938.   __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

  1939.   __RES; \

  1940.  })

  1941. 

  1942. #define __USAT16(ARG1, ARG2) \

  1943. ({                          \

  1944.   uint32_t __RES, __ARG1 = (ARG1); \

  1945.   __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

  1946.   __RES; \

  1947.  })

  1948. 

  1949. __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)

  1950. {

  1951.   uint32_t result;

  1952. 

  1953.   __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

  1954.   return(result);

  1955. }

  1956. 

  1957. __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

  1958. {

  1959.   uint32_t result;

  1960. 

  1961.   __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1962.   return(result);

  1963. }

  1964. 

  1965. __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)

  1966. {

  1967.   uint32_t result;

  1968. 

  1969.   __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

  1970.   return(result);

  1971. }

  1972. 

  1973. __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)

  1974. {

  1975.   uint32_t result;

  1976.   if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {

  1977.     __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );

  1978.   } else {

  1979.     result = __SXTB16(__ROR(op1, rotate)) ;

  1980.   }

  1981.   return result;

  1982. }

  1983. 

  1984. __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

  1985. {

  1986.   uint32_t result;

  1987. 

  1988.   __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1989.   return(result);

  1990. }

  1991. 

  1992. __STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

  1993. {

  1994.   uint32_t result;

  1995. 

  1996.   __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  1997.   return(result);

  1998. }

  1999. 

  2000. __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

  2001. {

  2002.   uint32_t result;

  2003. 

  2004.   __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2005.   return(result);

  2006. }

  2007. 

  2008. __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

  2009. {

  2010.   uint32_t result;

  2011. 

  2012.   __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  2013.   return(result);

  2014. }

  2015. 

  2016. __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

  2017. {

  2018.   uint32_t result;

  2019. 

  2020.   __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  2021.   return(result);

  2022. }

  2023. 

  2024. __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

  2025. {

  2026.   union llreg_u{

  2027.     uint32_t w32[2];

  2028.     uint64_t w64;

  2029.   } llr;

  2030.   llr.w64 = acc;

  2031. 

  2032. #ifndef __ARMEB__   /* Little endian */

  2033.   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

  2034. #else               /* Big endian */

  2035.   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

  2036. #endif

  2037. 

  2038.   return(llr.w64);

  2039. }

  2040. 

  2041. __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

  2042. {

  2043.   union llreg_u{

  2044.     uint32_t w32[2];

  2045.     uint64_t w64;

  2046.   } llr;

  2047.   llr.w64 = acc;

  2048. 

  2049. #ifndef __ARMEB__   /* Little endian */

  2050.   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

  2051. #else               /* Big endian */

  2052.   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

  2053. #endif

  2054. 

  2055.   return(llr.w64);

  2056. }

  2057. 

  2058. __STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

  2059. {

  2060.   uint32_t result;

  2061. 

  2062.   __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2063.   return(result);

  2064. }

  2065. 

  2066. __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

  2067. {

  2068.   uint32_t result;

  2069. 

  2070.   __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2071.   return(result);

  2072. }

  2073. 

  2074. __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

  2075. {

  2076.   uint32_t result;

  2077. 

  2078.   __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  2079.   return(result);

  2080. }

  2081. 

  2082. __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

  2083. {

  2084.   uint32_t result;

  2085. 

  2086.   __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  2087.   return(result);

  2088. }

  2089. 

  2090. __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

  2091. {

  2092.   union llreg_u{

  2093.     uint32_t w32[2];

  2094.     uint64_t w64;

  2095.   } llr;

  2096.   llr.w64 = acc;

  2097. 

  2098. #ifndef __ARMEB__   /* Little endian */

  2099.   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

  2100. #else               /* Big endian */

  2101.   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

  2102. #endif

  2103. 

  2104.   return(llr.w64);

  2105. }

  2106. 

  2107. __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

  2108. {

  2109.   union llreg_u{

  2110.     uint32_t w32[2];

  2111.     uint64_t w64;

  2112.   } llr;

  2113.   llr.w64 = acc;

  2114. 

  2115. #ifndef __ARMEB__   /* Little endian */

  2116.   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

  2117. #else               /* Big endian */

  2118.   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

  2119. #endif

  2120. 

  2121.   return(llr.w64);

  2122. }

  2123. 

  2124. __STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

  2125. {

  2126.   uint32_t result;

  2127. 

  2128.   __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2129.   return(result);

  2130. }

  2131. 

  2132. __STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)

  2133. {

  2134.   int32_t result;

  2135. 

  2136.   __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2137.   return(result);

  2138. }

  2139. 

  2140. __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)

  2141. {

  2142.   int32_t result;

  2143. 

  2144.   __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  2145.   return(result);

  2146. }

  2147. 

  2148. 

  2149. #define __PKHBT(ARG1,ARG2,ARG3) \

  2150. ({                          \

  2151.   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

  2152.   __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

  2153.   __RES; \

  2154.  })

  2155. 

  2156. #define __PKHTB(ARG1,ARG2,ARG3) \

  2157. ({                          \

  2158.   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

  2159.   if (ARG3 == 0) \

  2160.     __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

  2161.   else \

  2162.     __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

  2163.   __RES; \

  2164.  })

  2165. 

  2166. 

  2167. __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

  2168. {

  2169.  int32_t result;

  2170. 

  2171.  __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

  2172.  return(result);

  2173. }

  2174. 

  2175. #endif /* (__ARM_FEATURE_DSP == 1) */

  2176. /*@} end of group CMSIS_SIMD_intrinsics */

  2177. 

  2178. 

  2179. #pragma GCC diagnostic pop

  2180. 

  2181. #endif /* __CMSIS_GCC_H */