PlatformIO package of the Teensy core framework compatible with GCC 10 & C++20
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  1. /*! @file radio_config.h
  2. * @brief This file contains the automatically generated
  3. * configurations.
  4. *
  5. * @n WDS GUI Version: 3.2.6.0
  6. * @n Device: Si4460 Rev.: B1
  7. *
  8. * @b COPYRIGHT
  9. * @n Silicon Laboratories Confidential
  10. * @n Copyright 2013 Silicon Laboratories, Inc.
  11. * @n http://www.silabs.com
  12. */
  13. #ifndef RADIO_CONFIG_H_
  14. #define RADIO_CONFIG_H_
  15. // USER DEFINED PARAMETERS
  16. // Define your own parameters here
  17. // INPUT DATA
  18. /*
  19. // Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
  20. // MOD_type: 3 Rsymb(sps): 50000 Fdev(Hz): 100000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
  21. // RF Freq.(MHz): 434 API_TC: 31 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
  22. //
  23. // # WB filter 2 (BW = 274.83 kHz); NB-filter 2 (BW = 274.83 kHz)
  24. //
  25. // Modulation index: 4
  26. */
  27. // CONFIGURATION PARAMETERS
  28. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ {30000000L}
  29. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER {0x00}
  30. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH {0x07}
  31. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP {0x03}
  32. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET {0xF000}
  33. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5}
  34. // CONFIGURATION COMMANDS
  35. /*
  36. // Command: RF_POWER_UP
  37. // Description: Command to power-up the device and select the operational mode and functionality.
  38. */
  39. #define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
  40. /*
  41. // Command: RF_GPIO_PIN_CFG
  42. // Description: Configures the GPIO pins.
  43. */
  44. #define RF_GPIO_PIN_CFG 0x13, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  45. /*
  46. // Set properties: RF_GLOBAL_XO_TUNE_1
  47. // Number of properties: 1
  48. // Group ID: 0x00
  49. // Start ID: 0x00
  50. // Default values: 0x40,
  51. // Descriptions:
  52. // GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
  53. */
  54. #define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
  55. /*
  56. // Set properties: RF_GLOBAL_CONFIG_1
  57. // Number of properties: 1
  58. // Group ID: 0x00
  59. // Start ID: 0x03
  60. // Default values: 0x20,
  61. // Descriptions:
  62. // GLOBAL_CONFIG - Global configuration settings.
  63. */
  64. #define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
  65. /*
  66. // Set properties: RF_INT_CTL_ENABLE_2
  67. // Number of properties: 2
  68. // Group ID: 0x01
  69. // Start ID: 0x00
  70. // Default values: 0x04, 0x00,
  71. // Descriptions:
  72. // INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
  73. // INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
  74. */
  75. #define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x38
  76. /*
  77. // Set properties: RF_FRR_CTL_A_MODE_4
  78. // Number of properties: 4
  79. // Group ID: 0x02
  80. // Start ID: 0x00
  81. // Default values: 0x01, 0x02, 0x09, 0x00,
  82. // Descriptions:
  83. // FRR_CTL_A_MODE - Fast Response Register A Configuration.
  84. // FRR_CTL_B_MODE - Fast Response Register B Configuration.
  85. // FRR_CTL_C_MODE - Fast Response Register C Configuration.
  86. // FRR_CTL_D_MODE - Fast Response Register D Configuration.
  87. */
  88. #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
  89. /*
  90. // Set properties: RF_PREAMBLE_TX_LENGTH_9
  91. // Number of properties: 9
  92. // Group ID: 0x10
  93. // Start ID: 0x00
  94. // Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00,
  95. // Descriptions:
  96. // PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
  97. // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
  98. // PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
  99. // PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
  100. // PREAMBLE_CONFIG - General configuration bits for the Preamble field.
  101. // PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  102. // PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  103. // PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  104. // PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  105. */
  106. #define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00
  107. /*
  108. // Set properties: RF_SYNC_CONFIG_5
  109. // Number of properties: 5
  110. // Group ID: 0x11
  111. // Start ID: 0x00
  112. // Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4,
  113. // Descriptions:
  114. // SYNC_CONFIG - Sync Word configuration bits.
  115. // SYNC_BITS_31_24 - Sync word.
  116. // SYNC_BITS_23_16 - Sync word.
  117. // SYNC_BITS_15_8 - Sync word.
  118. // SYNC_BITS_7_0 - Sync word.
  119. */
  120. #define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00
  121. /*
  122. // Set properties: RF_PKT_CRC_CONFIG_1
  123. // Number of properties: 1
  124. // Group ID: 0x12
  125. // Start ID: 0x00
  126. // Default values: 0x00,
  127. // Descriptions:
  128. // PKT_CRC_CONFIG - Select a CRC polynomial and seed.
  129. */
  130. #define RF_PKT_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x00, 0x80
  131. /*
  132. // Set properties: RF_PKT_WHT_SEED_15_8_4
  133. // Number of properties: 4
  134. // Group ID: 0x12
  135. // Start ID: 0x03
  136. // Default values: 0xFF, 0xFF, 0x00, 0x00,
  137. // Descriptions:
  138. // PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
  139. // PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
  140. // PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
  141. // PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
  142. */
  143. #define RF_PKT_WHT_SEED_15_8_4 0x11, 0x12, 0x04, 0x03, 0xFF, 0xFF, 0x00, 0x02
  144. /*
  145. // Set properties: RF_PKT_LEN_12
  146. // Number of properties: 12
  147. // Group ID: 0x12
  148. // Start ID: 0x08
  149. // Default values: 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  150. // Descriptions:
  151. // PKT_LEN - Configuration bits for reception of a variable length packet.
  152. // PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
  153. // PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
  154. // PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
  155. // PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
  156. // PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
  157. // PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
  158. // PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
  159. // PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
  160. // PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
  161. // PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
  162. // PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
  163. */
  164. #define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00
  165. /*
  166. // Set properties: RF_PKT_FIELD_2_CRC_CONFIG_12
  167. // Number of properties: 12
  168. // Group ID: 0x12
  169. // Start ID: 0x14
  170. // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  171. // Descriptions:
  172. // PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
  173. // PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
  174. // PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
  175. // PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
  176. // PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
  177. // PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
  178. // PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
  179. // PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
  180. // PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
  181. // PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
  182. // PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
  183. // PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
  184. */
  185. #define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  186. /*
  187. // Set properties: RF_PKT_FIELD_5_CRC_CONFIG_1
  188. // Number of properties: 1
  189. // Group ID: 0x12
  190. // Start ID: 0x20
  191. // Default values: 0x00,
  192. // Descriptions:
  193. // PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
  194. */
  195. #define RF_PKT_FIELD_5_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x20, 0x00
  196. /*
  197. // Set properties: RF_MODEM_MOD_TYPE_12
  198. // Number of properties: 12
  199. // Group ID: 0x20
  200. // Start ID: 0x00
  201. // Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
  202. // Descriptions:
  203. // MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
  204. // MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
  205. // MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
  206. // MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
  207. // MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
  208. // MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
  209. // MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  210. // MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  211. // MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  212. // MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  213. // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
  214. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
  215. */
  216. #define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x1B
  217. /*
  218. // Set properties: RF_MODEM_FREQ_DEV_0_1
  219. // Number of properties: 1
  220. // Group ID: 0x20
  221. // Start ID: 0x0C
  222. // Default values: 0xD3,
  223. // Descriptions:
  224. // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
  225. */
  226. #define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x4F
  227. /*
  228. // Set properties: RF_MODEM_TX_RAMP_DELAY_8
  229. // Number of properties: 8
  230. // Group ID: 0x20
  231. // Start ID: 0x18
  232. // Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
  233. // Descriptions:
  234. // MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
  235. // MODEM_MDM_CTRL - MDM control.
  236. // MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
  237. // MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
  238. // MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
  239. // MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
  240. // MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
  241. // MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
  242. */
  243. #define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x00, 0x10
  244. /*
  245. // Set properties: RF_MODEM_BCR_OSR_1_9
  246. // Number of properties: 9
  247. // Group ID: 0x20
  248. // Start ID: 0x22
  249. // Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
  250. // Descriptions:
  251. // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
  252. // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
  253. // MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
  254. // MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
  255. // MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
  256. // MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
  257. // MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
  258. // MODEM_BCR_GEAR - RX BCR loop gear control.
  259. // MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
  260. */
  261. #define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0xC8, 0x02, 0x8F, 0x5C, 0x01, 0x48, 0x02, 0xC2
  262. /*
  263. // Set properties: RF_MODEM_AFC_GEAR_7
  264. // Number of properties: 7
  265. // Group ID: 0x20
  266. // Start ID: 0x2C
  267. // Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
  268. // Descriptions:
  269. // MODEM_AFC_GEAR - RX AFC loop gear control.
  270. // MODEM_AFC_WAIT - RX AFC loop wait time control.
  271. // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
  272. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
  273. // MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
  274. // MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
  275. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
  276. */
  277. #define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x92, 0x0A, 0x46, 0x80
  278. /*
  279. // Set properties: RF_MODEM_AGC_CONTROL_1
  280. // Number of properties: 1
  281. // Group ID: 0x20
  282. // Start ID: 0x35
  283. // Default values: 0xE0,
  284. // Descriptions:
  285. // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
  286. */
  287. #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
  288. /*
  289. // Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
  290. // Number of properties: 9
  291. // Group ID: 0x20
  292. // Start ID: 0x38
  293. // Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
  294. // Descriptions:
  295. // MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
  296. // MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
  297. // MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
  298. // MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
  299. // MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
  300. // MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
  301. // MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
  302. // MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
  303. // MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
  304. */
  305. #define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x2C, 0x2C, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x29
  306. /*
  307. // Set properties: RF_MODEM_OOK_CNT1_11
  308. // Number of properties: 11
  309. // Group ID: 0x20
  310. // Start ID: 0x42
  311. // Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01,
  312. // Descriptions:
  313. // MODEM_OOK_CNT1 - OOK control.
  314. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
  315. // MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
  316. // MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
  317. // MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
  318. // MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
  319. // MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
  320. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
  321. // MODEM_RSSI_THRESH - Configures the RSSI threshold.
  322. // MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
  323. // MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
  324. */
  325. #define RF_MODEM_OOK_CNT1_11 0x11, 0x20, 0x0B, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x01, 0x7F, 0x01, 0x80, 0xFF, 0x0C, 0x02
  326. /*
  327. // Set properties: RF_MODEM_RSSI_COMP_1
  328. // Number of properties: 1
  329. // Group ID: 0x20
  330. // Start ID: 0x4E
  331. // Default values: 0x40,
  332. // Descriptions:
  333. // MODEM_RSSI_COMP - RSSI compensation value.
  334. */
  335. #define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
  336. /*
  337. // Set properties: RF_MODEM_CLKGEN_BAND_1
  338. // Number of properties: 1
  339. // Group ID: 0x20
  340. // Start ID: 0x51
  341. // Default values: 0x08,
  342. // Descriptions:
  343. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
  344. */
  345. #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
  346. /*
  347. // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
  348. // Number of properties: 12
  349. // Group ID: 0x21
  350. // Start ID: 0x00
  351. // Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
  352. // Descriptions:
  353. // MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
  354. // MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
  355. // MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
  356. // MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
  357. // MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
  358. // MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
  359. // MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
  360. // MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
  361. // MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
  362. // MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
  363. // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
  364. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
  365. */
  366. #define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
  367. /*
  368. // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
  369. // Number of properties: 12
  370. // Group ID: 0x21
  371. // Start ID: 0x0C
  372. // Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
  373. // Descriptions:
  374. // MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
  375. // MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
  376. // MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
  377. // MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
  378. // MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
  379. // MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
  380. // MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
  381. // MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
  382. // MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
  383. // MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
  384. // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
  385. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
  386. */
  387. #define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
  388. /*
  389. // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
  390. // Number of properties: 12
  391. // Group ID: 0x21
  392. // Start ID: 0x18
  393. // Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
  394. // Descriptions:
  395. // MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
  396. // MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
  397. // MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
  398. // MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
  399. // MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
  400. // MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
  401. // MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
  402. // MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
  403. // MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
  404. // MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
  405. // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
  406. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
  407. */
  408. #define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
  409. /*
  410. // Set properties: RF_PA_MODE_4
  411. // Number of properties: 4
  412. // Group ID: 0x22
  413. // Start ID: 0x00
  414. // Default values: 0x08, 0x7F, 0x00, 0x5D,
  415. // Descriptions:
  416. // PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
  417. // PA_PWR_LVL - Configuration of PA output power level.
  418. // PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
  419. // PA_TC - Configuration of PA ramping parameters.
  420. */
  421. #define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x18, 0x01, 0xC0, 0x3F
  422. /*
  423. // Set properties: RF_SYNTH_PFDCP_CPFF_7
  424. // Number of properties: 7
  425. // Group ID: 0x23
  426. // Start ID: 0x00
  427. // Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
  428. // Descriptions:
  429. // SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
  430. // SYNTH_PFDCP_CPINT - Integration charge pump current selection.
  431. // SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
  432. // SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
  433. // SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
  434. // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
  435. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
  436. */
  437. #define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
  438. /*
  439. // Set properties: RF_MATCH_VALUE_1_12
  440. // Number of properties: 12
  441. // Group ID: 0x30
  442. // Start ID: 0x00
  443. // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  444. // Descriptions:
  445. // MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
  446. // MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
  447. // MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
  448. // MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
  449. // MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
  450. // MATCH_CTRL_2 - Configuration of Match Byte 2.
  451. // MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
  452. // MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
  453. // MATCH_CTRL_3 - Configuration of Match Byte 3.
  454. // MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
  455. // MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
  456. // MATCH_CTRL_4 - Configuration of Match Byte 4.
  457. */
  458. #define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  459. /*
  460. // Set properties: RF_FREQ_CONTROL_INTE_8
  461. // Number of properties: 8
  462. // Group ID: 0x40
  463. // Start ID: 0x00
  464. // Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
  465. // Descriptions:
  466. // FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
  467. // FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
  468. // FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
  469. // FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
  470. // FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
  471. // FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
  472. // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
  473. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
  474. */
  475. #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE
  476. // AUTOMATICALLY GENERATED CODE!
  477. // DO NOT EDIT/MODIFY BELOW THIS LINE!
  478. // --------------------------------------------
  479. #ifndef FIRMWARE_LOAD_COMPILE
  480. #define RADIO_CONFIGURATION_DATA_ARRAY { \
  481. 0x07, RF_POWER_UP, \
  482. 0x08, RF_GPIO_PIN_CFG, \
  483. 0x05, RF_GLOBAL_XO_TUNE_1, \
  484. 0x05, RF_GLOBAL_CONFIG_1, \
  485. 0x06, RF_INT_CTL_ENABLE_2, \
  486. 0x08, RF_FRR_CTL_A_MODE_4, \
  487. 0x0D, RF_PREAMBLE_TX_LENGTH_9, \
  488. 0x09, RF_SYNC_CONFIG_5, \
  489. 0x05, RF_PKT_CRC_CONFIG_1, \
  490. 0x08, RF_PKT_WHT_SEED_15_8_4, \
  491. 0x10, RF_PKT_LEN_12, \
  492. 0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \
  493. 0x05, RF_PKT_FIELD_5_CRC_CONFIG_1, \
  494. 0x10, RF_MODEM_MOD_TYPE_12, \
  495. 0x05, RF_MODEM_FREQ_DEV_0_1, \
  496. 0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
  497. 0x0D, RF_MODEM_BCR_OSR_1_9, \
  498. 0x0B, RF_MODEM_AFC_GEAR_7, \
  499. 0x05, RF_MODEM_AGC_CONTROL_1, \
  500. 0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
  501. 0x0F, RF_MODEM_OOK_CNT1_11, \
  502. 0x05, RF_MODEM_RSSI_COMP_1, \
  503. 0x05, RF_MODEM_CLKGEN_BAND_1, \
  504. 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
  505. 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
  506. 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
  507. 0x08, RF_PA_MODE_4, \
  508. 0x0B, RF_SYNTH_PFDCP_CPFF_7, \
  509. 0x10, RF_MATCH_VALUE_1_12, \
  510. 0x0C, RF_FREQ_CONTROL_INTE_8, \
  511. 0x00 \
  512. }
  513. #else
  514. #define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
  515. #endif
  516. // DEFAULT VALUES FOR CONFIGURATION PARAMETERS
  517. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
  518. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
  519. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
  520. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
  521. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
  522. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT 0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31 // BUTTON1
  523. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
  524. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
  525. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
  526. #ifndef RADIO_CONFIGURATION_DATA_ARRAY
  527. #error "This property must be defined!"
  528. #endif
  529. #ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
  530. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ { RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT }
  531. #endif
  532. #ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
  533. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER { RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT }
  534. #endif
  535. #ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
  536. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH { RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT }
  537. #endif
  538. #ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
  539. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP { RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT }
  540. #endif
  541. #ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
  542. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET { RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT }
  543. #endif
  544. #ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD
  545. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD { RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT }
  546. #endif
  547. #define RADIO_CONFIGURATION_DATA { \
  548. Radio_Configuration_Data_Array, \
  549. RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
  550. RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
  551. RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
  552. RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET, \
  553. RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD \
  554. }
  555. #endif /* RADIO_CONFIG_H_ */