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PlatformIO package of the Teensy core framework compatible with GCC 10 & C++20
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framework-arduinoteensy-cxx20/libraries/RadioHead/radio_config_Si4460.h

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原始文件 Blame 歷史記錄 

  1. /*! @file radio_config.h

  2.  * @brief This file contains the automatically generated

  3.  * configurations.

  4.  *

  5.  * @n WDS GUI Version: 3.2.6.0

  6.  * @n Device: Si4460 Rev.: B1                                 

  7.  *

  8.  * @b COPYRIGHT

  9.  * @n Silicon Laboratories Confidential

  10.  * @n Copyright 2013 Silicon Laboratories, Inc.

  11.  * @n http://www.silabs.com

  12.  */

  13. 

  14. #ifndef RADIO_CONFIG_H_

  15. #define RADIO_CONFIG_H_

  16. 

  17. // USER DEFINED PARAMETERS

  18. // Define your own parameters here

  19. 

  20. // INPUT DATA

  21. /*

  22. // Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    

  23. // MOD_type: 3    Rsymb(sps): 50000    Fdev(Hz): 100000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    

  24. // RF Freq.(MHz): 434    API_TC: 31    fhst: 250000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    

  25. // 

  26. // # WB filter 2 (BW = 274.83 kHz);  NB-filter 2 (BW = 274.83 kHz) 


  27. // 

  28. // Modulation index: 4

  29. */

  30. 

  31. 

  32. // CONFIGURATION PARAMETERS

  33. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     {30000000L}

  34. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    {0x00}

  35. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               {0x07}

  36. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        {0x03}

  37. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       {0xF000}

  38. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD					   {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5}

  39. 

  40. 

  41. // CONFIGURATION COMMANDS

  42. 

  43. /*

  44. // Command:                  RF_POWER_UP

  45. // Description:              Command to power-up the device and select the operational mode and functionality.

  46. */

  47. #define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80

  48. 

  49. /*

  50. // Command:                  RF_GPIO_PIN_CFG

  51. // Description:              Configures the GPIO pins.

  52. */

  53. #define RF_GPIO_PIN_CFG 0x13, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  54. 

  55. /*

  56. // Set properties:           RF_GLOBAL_XO_TUNE_1

  57. // Number of properties:     1

  58. // Group ID:                 0x00

  59. // Start ID:                 0x00

  60. // Default values:           0x40, 

  61. // Descriptions:

  62. //   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.

  63. */

  64. #define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52

  65. 

  66. /*

  67. // Set properties:           RF_GLOBAL_CONFIG_1

  68. // Number of properties:     1

  69. // Group ID:                 0x00

  70. // Start ID:                 0x03

  71. // Default values:           0x20, 

  72. // Descriptions:

  73. //   GLOBAL_CONFIG - Global configuration settings.

  74. */

  75. #define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60

  76. 

  77. /*

  78. // Set properties:           RF_INT_CTL_ENABLE_2

  79. // Number of properties:     2

  80. // Group ID:                 0x01

  81. // Start ID:                 0x00

  82. // Default values:           0x04, 0x00, 

  83. // Descriptions:

  84. //   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.

  85. //   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.

  86. */

  87. #define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x38

  88. 

  89. /*

  90. // Set properties:           RF_FRR_CTL_A_MODE_4

  91. // Number of properties:     4

  92. // Group ID:                 0x02

  93. // Start ID:                 0x00

  94. // Default values:           0x01, 0x02, 0x09, 0x00, 

  95. // Descriptions:

  96. //   FRR_CTL_A_MODE - Fast Response Register A Configuration.

  97. //   FRR_CTL_B_MODE - Fast Response Register B Configuration.

  98. //   FRR_CTL_C_MODE - Fast Response Register C Configuration.

  99. //   FRR_CTL_D_MODE - Fast Response Register D Configuration.

  100. */

  101. #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00

  102. 

  103. /*

  104. // Set properties:           RF_PREAMBLE_TX_LENGTH_9

  105. // Number of properties:     9

  106. // Group ID:                 0x10

  107. // Start ID:                 0x00

  108. // Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 

  109. // Descriptions:

  110. //   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.

  111. //   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.

  112. //   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.

  113. //   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.

  114. //   PREAMBLE_CONFIG - General configuration bits for the Preamble field.

  115. //   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.

  116. //   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.

  117. //   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.

  118. //   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.

  119. */

  120. #define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00

  121. 

  122. /*

  123. // Set properties:           RF_SYNC_CONFIG_5

  124. // Number of properties:     5

  125. // Group ID:                 0x11

  126. // Start ID:                 0x00

  127. // Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 

  128. // Descriptions:

  129. //   SYNC_CONFIG - Sync Word configuration bits.

  130. //   SYNC_BITS_31_24 - Sync word.

  131. //   SYNC_BITS_23_16 - Sync word.

  132. //   SYNC_BITS_15_8 - Sync word.

  133. //   SYNC_BITS_7_0 - Sync word.

  134. */

  135. #define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00

  136. 

  137. /*

  138. // Set properties:           RF_PKT_CRC_CONFIG_1

  139. // Number of properties:     1

  140. // Group ID:                 0x12

  141. // Start ID:                 0x00

  142. // Default values:           0x00, 

  143. // Descriptions:

  144. //   PKT_CRC_CONFIG - Select a CRC polynomial and seed.

  145. */

  146. #define RF_PKT_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x00, 0x80

  147. 

  148. /*

  149. // Set properties:           RF_PKT_WHT_SEED_15_8_4

  150. // Number of properties:     4

  151. // Group ID:                 0x12

  152. // Start ID:                 0x03

  153. // Default values:           0xFF, 0xFF, 0x00, 0x00, 

  154. // Descriptions:

  155. //   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)

  156. //   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)

  157. //   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.

  158. //   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.

  159. */

  160. #define RF_PKT_WHT_SEED_15_8_4 0x11, 0x12, 0x04, 0x03, 0xFF, 0xFF, 0x00, 0x02

  161. 

  162. /*

  163. // Set properties:           RF_PKT_LEN_12

  164. // Number of properties:     12

  165. // Group ID:                 0x12

  166. // Start ID:                 0x08

  167. // Default values:           0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 

  168. // Descriptions:

  169. //   PKT_LEN - Configuration bits for reception of a variable length packet.

  170. //   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).

  171. //   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).

  172. //   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.

  173. //   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.

  174. //   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.

  175. //   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.

  176. //   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.

  177. //   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.

  178. //   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.

  179. //   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.

  180. //   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.

  181. */

  182. #define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00

  183. 

  184. /*

  185. // Set properties:           RF_PKT_FIELD_2_CRC_CONFIG_12

  186. // Number of properties:     12

  187. // Group ID:                 0x12

  188. // Start ID:                 0x14

  189. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 

  190. // Descriptions:

  191. //   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.

  192. //   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.

  193. //   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.

  194. //   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.

  195. //   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.

  196. //   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.

  197. //   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.

  198. //   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.

  199. //   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.

  200. //   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.

  201. //   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.

  202. //   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.

  203. */

  204. #define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  205. 

  206. /*

  207. // Set properties:           RF_PKT_FIELD_5_CRC_CONFIG_1

  208. // Number of properties:     1

  209. // Group ID:                 0x12

  210. // Start ID:                 0x20

  211. // Default values:           0x00, 

  212. // Descriptions:

  213. //   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.

  214. */

  215. #define RF_PKT_FIELD_5_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x20, 0x00

  216. 

  217. /*

  218. // Set properties:           RF_MODEM_MOD_TYPE_12

  219. // Number of properties:     12

  220. // Group ID:                 0x20

  221. // Start ID:                 0x00

  222. // Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 

  223. // Descriptions:

  224. //   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.

  225. //   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.

  226. //   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.

  227. //   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate

  228. //   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate

  229. //   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate

  230. //   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.

  231. //   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.

  232. //   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.

  233. //   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.

  234. //   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.

  235. //   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.

  236. */

  237. #define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x1B

  238. 

  239. /*

  240. // Set properties:           RF_MODEM_FREQ_DEV_0_1

  241. // Number of properties:     1

  242. // Group ID:                 0x20

  243. // Start ID:                 0x0C

  244. // Default values:           0xD3, 

  245. // Descriptions:

  246. //   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.

  247. */

  248. #define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x4F

  249. 

  250. /*

  251. // Set properties:           RF_MODEM_TX_RAMP_DELAY_8

  252. // Number of properties:     8

  253. // Group ID:                 0x20

  254. // Start ID:                 0x18

  255. // Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 

  256. // Descriptions:

  257. //   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.

  258. //   MODEM_MDM_CTRL - MDM control.

  259. //   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.

  260. //   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).

  261. //   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).

  262. //   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).

  263. //   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.

  264. //   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.

  265. */

  266. #define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x00, 0x10

  267. 

  268. /*

  269. // Set properties:           RF_MODEM_BCR_OSR_1_9

  270. // Number of properties:     9

  271. // Group ID:                 0x20

  272. // Start ID:                 0x22

  273. // Default values:           0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 

  274. // Descriptions:

  275. //   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).

  276. //   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).

  277. //   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).

  278. //   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).

  279. //   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).

  280. //   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.

  281. //   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.

  282. //   MODEM_BCR_GEAR - RX BCR loop gear control.

  283. //   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.

  284. */

  285. #define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0xC8, 0x02, 0x8F, 0x5C, 0x01, 0x48, 0x02, 0xC2

  286. 

  287. /*

  288. // Set properties:           RF_MODEM_AFC_GEAR_7

  289. // Number of properties:     7

  290. // Group ID:                 0x20

  291. // Start ID:                 0x2C

  292. // Default values:           0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0, 

  293. // Descriptions:

  294. //   MODEM_AFC_GEAR - RX AFC loop gear control.

  295. //   MODEM_AFC_WAIT - RX AFC loop wait time control.

  296. //   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.

  297. //   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.

  298. //   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.

  299. //   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.

  300. //   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.

  301. */

  302. #define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x92, 0x0A, 0x46, 0x80

  303. 

  304. /*

  305. // Set properties:           RF_MODEM_AGC_CONTROL_1

  306. // Number of properties:     1

  307. // Group ID:                 0x20

  308. // Start ID:                 0x35

  309. // Default values:           0xE0, 

  310. // Descriptions:

  311. //   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.

  312. */

  313. #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2

  314. 

  315. /*

  316. // Set properties:           RF_MODEM_AGC_WINDOW_SIZE_9

  317. // Number of properties:     9

  318. // Group ID:                 0x20

  319. // Start ID:                 0x38

  320. // Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 

  321. // Descriptions:

  322. //   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.

  323. //   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.

  324. //   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.

  325. //   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.

  326. //   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.

  327. //   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.

  328. //   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.

  329. //   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.

  330. //   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.

  331. */

  332. #define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x2C, 0x2C, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x29

  333. 

  334. /*

  335. // Set properties:           RF_MODEM_OOK_CNT1_11

  336. // Number of properties:     11

  337. // Group ID:                 0x20

  338. // Start ID:                 0x42

  339. // Default values:           0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 

  340. // Descriptions:

  341. //   MODEM_OOK_CNT1 - OOK control.

  342. //   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.

  343. //   MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.

  344. //   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.

  345. //   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.

  346. //   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.

  347. //   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.

  348. //   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.

  349. //   MODEM_RSSI_THRESH - Configures the RSSI threshold.

  350. //   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.

  351. //   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).

  352. */

  353. #define RF_MODEM_OOK_CNT1_11 0x11, 0x20, 0x0B, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x01, 0x7F, 0x01, 0x80, 0xFF, 0x0C, 0x02

  354. 

  355. /*

  356. // Set properties:           RF_MODEM_RSSI_COMP_1

  357. // Number of properties:     1

  358. // Group ID:                 0x20

  359. // Start ID:                 0x4E

  360. // Default values:           0x40, 

  361. // Descriptions:

  362. //   MODEM_RSSI_COMP - RSSI compensation value.

  363. */

  364. #define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40

  365. 

  366. /*

  367. // Set properties:           RF_MODEM_CLKGEN_BAND_1

  368. // Number of properties:     1

  369. // Group ID:                 0x20

  370. // Start ID:                 0x51

  371. // Default values:           0x08, 

  372. // Descriptions:

  373. //   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.

  374. */

  375. #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A

  376. 

  377. /*

  378. // Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12

  379. // Number of properties:     12

  380. // Group ID:                 0x21

  381. // Start ID:                 0x00

  382. // Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 

  383. // Descriptions:

  384. //   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.

  385. //   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.

  386. //   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.

  387. //   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.

  388. //   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.

  389. //   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.

  390. //   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.

  391. //   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.

  392. //   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.

  393. //   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.

  394. //   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.

  395. //   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.

  396. */

  397. #define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C

  398. 

  399. /*

  400. // Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12

  401. // Number of properties:     12

  402. // Group ID:                 0x21

  403. // Start ID:                 0x0C

  404. // Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 

  405. // Descriptions:

  406. //   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.

  407. //   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.

  408. //   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.

  409. //   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.

  410. //   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.

  411. //   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.

  412. //   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.

  413. //   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.

  414. //   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.

  415. //   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.

  416. //   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.

  417. //   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.

  418. */

  419. #define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5

  420. 

  421. /*

  422. // Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12

  423. // Number of properties:     12

  424. // Group ID:                 0x21

  425. // Start ID:                 0x18

  426. // Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 

  427. // Descriptions:

  428. //   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.

  429. //   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.

  430. //   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.

  431. //   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.

  432. //   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.

  433. //   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.

  434. //   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.

  435. //   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.

  436. //   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.

  437. //   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.

  438. //   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.

  439. //   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.

  440. */

  441. #define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00

  442. 

  443. /*

  444. // Set properties:           RF_PA_MODE_4

  445. // Number of properties:     4

  446. // Group ID:                 0x22

  447. // Start ID:                 0x00

  448. // Default values:           0x08, 0x7F, 0x00, 0x5D, 

  449. // Descriptions:

  450. //   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).

  451. //   PA_PWR_LVL - Configuration of PA output power level.

  452. //   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.

  453. //   PA_TC - Configuration of PA ramping parameters.

  454. */

  455. #define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x18, 0x01, 0xC0, 0x3F

  456. 

  457. /*

  458. // Set properties:           RF_SYNTH_PFDCP_CPFF_7

  459. // Number of properties:     7

  460. // Group ID:                 0x23

  461. // Start ID:                 0x00

  462. // Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 

  463. // Descriptions:

  464. //   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.

  465. //   SYNTH_PFDCP_CPINT - Integration charge pump current selection.

  466. //   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.

  467. //   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.

  468. //   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.

  469. //   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.

  470. //   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.

  471. */

  472. #define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03

  473. 

  474. /*

  475. // Set properties:           RF_MATCH_VALUE_1_12

  476. // Number of properties:     12

  477. // Group ID:                 0x30

  478. // Start ID:                 0x00

  479. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 

  480. // Descriptions:

  481. //   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.

  482. //   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.

  483. //   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.

  484. //   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.

  485. //   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.

  486. //   MATCH_CTRL_2 - Configuration of Match Byte 2.

  487. //   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.

  488. //   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.

  489. //   MATCH_CTRL_3 - Configuration of Match Byte 3.

  490. //   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.

  491. //   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.

  492. //   MATCH_CTRL_4 - Configuration of Match Byte 4.

  493. */

  494. #define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  495. 

  496. /*

  497. // Set properties:           RF_FREQ_CONTROL_INTE_8

  498. // Number of properties:     8

  499. // Group ID:                 0x40

  500. // Start ID:                 0x00

  501. // Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 

  502. // Descriptions:

  503. //   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.

  504. //   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.

  505. //   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.

  506. //   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.

  507. //   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.

  508. //   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.

  509. //   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.

  510. //   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.

  511. */

  512. #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE

  513. 

  514. 

  515. // AUTOMATICALLY GENERATED CODE! 

  516. // DO NOT EDIT/MODIFY BELOW THIS LINE!

  517. // --------------------------------------------

  518. 

  519. #ifndef FIRMWARE_LOAD_COMPILE

  520. #define RADIO_CONFIGURATION_DATA_ARRAY { \

  521.         0x07, RF_POWER_UP, \

  522.         0x08, RF_GPIO_PIN_CFG, \

  523.         0x05, RF_GLOBAL_XO_TUNE_1, \

  524.         0x05, RF_GLOBAL_CONFIG_1, \

  525.         0x06, RF_INT_CTL_ENABLE_2, \

  526.         0x08, RF_FRR_CTL_A_MODE_4, \

  527.         0x0D, RF_PREAMBLE_TX_LENGTH_9, \

  528.         0x09, RF_SYNC_CONFIG_5, \

  529.         0x05, RF_PKT_CRC_CONFIG_1, \

  530.         0x08, RF_PKT_WHT_SEED_15_8_4, \

  531.         0x10, RF_PKT_LEN_12, \

  532.         0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \

  533.         0x05, RF_PKT_FIELD_5_CRC_CONFIG_1, \

  534.         0x10, RF_MODEM_MOD_TYPE_12, \

  535.         0x05, RF_MODEM_FREQ_DEV_0_1, \

  536.         0x0C, RF_MODEM_TX_RAMP_DELAY_8, \

  537.         0x0D, RF_MODEM_BCR_OSR_1_9, \

  538.         0x0B, RF_MODEM_AFC_GEAR_7, \

  539.         0x05, RF_MODEM_AGC_CONTROL_1, \

  540.         0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \

  541.         0x0F, RF_MODEM_OOK_CNT1_11, \

  542.         0x05, RF_MODEM_RSSI_COMP_1, \

  543.         0x05, RF_MODEM_CLKGEN_BAND_1, \

  544.         0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \

  545.         0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \

  546.         0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \

  547.         0x08, RF_PA_MODE_4, \

  548.         0x0B, RF_SYNTH_PFDCP_CPFF_7, \

  549.         0x10, RF_MATCH_VALUE_1_12, \

  550.         0x0C, RF_FREQ_CONTROL_INTE_8, \

  551.         0x00 \

  552.  }

  553. #else

  554. #define RADIO_CONFIGURATION_DATA_ARRAY { 0 }

  555. #endif

  556. 

  557. // DEFAULT VALUES FOR CONFIGURATION PARAMETERS

  558. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L

  559. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00

  560. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10

  561. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01

  562. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000

  563. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT					   0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31 // BUTTON1 

  564. 

  565. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00

  566. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00

  567. #define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }

  568. 

  569. #ifndef RADIO_CONFIGURATION_DATA_ARRAY

  570. #error "This property must be defined!"

  571. #endif

  572. 

  573. #ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ

  574. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ         { RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT }

  575. #endif

  576. 

  577. #ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER

  578. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER        { RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT }

  579. #endif

  580. 

  581. #ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH

  582. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH   { RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT }

  583. #endif

  584. 

  585. #ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP

  586. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP  { RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT }

  587. #endif

  588. 

  589. #ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET

  590. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET { RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT }

  591. #endif

  592. 

  593. #ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD

  594. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD        { RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT }

  595. #endif

  596. 

  597. #define RADIO_CONFIGURATION_DATA { \

  598.                             Radio_Configuration_Data_Array,                            \

  599.                             RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \

  600.                             RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \

  601.                             RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \

  602.                             RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET,       \

  603.                             RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD                   \

  604.                             }

  605. 

  606. #endif /* RADIO_CONFIG_H_ */