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PlatformIO package of the Teensy core framework compatible with GCC 10 & C++20
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framework-arduinoteensy-cxx20/libraries/SD/utility/NXP_SDHC.cpp

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  1. // adapted for Arduino SD library by Paul Stoffregen

  2. // following code is modified by Walter Zimmer from

  3. // from version provided by

  4. // Petr Gargulak (NXP Employee)

  5. //https://community.nxp.com/servlet/JiveServlet/download/339474-1-263510/SDHC_K60_Baremetal.ZIP

  6. //see also

  7. //https://community.nxp.com/thread/99202

  8. 

  9. #if defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(__IMXRT1062__)

  10. 

  11. #include "core_pins.h"  // include calls to kinetis.h or imxrt.h

  12. #include "usb_serial.h" // for Serial

  13. 

  14. #include "NXP_SDHC.h"

  15. 

  16. /******************************************************************************

  17.   Constants

  18. ******************************************************************************/

  19. 

  20. enum {

  21.   SDHC_RESULT_OK = 0,             /* 0: Successful */

  22.   SDHC_RESULT_ERROR,              /* 1: R/W Error */

  23.   SDHC_RESULT_WRPRT,              /* 2: Write Protected */

  24.   SDHC_RESULT_NOT_READY,          /* 3: Not Ready */

  25.   SDHC_RESULT_PARERR,             /* 4: Invalid Parameter */

  26.   SDHC_RESULT_NO_RESPONSE         /* 5: No Response */ // from old diskio.h

  27. };

  28. 

  29. /*void print_result(int n)

  30.   {

  31.         switch (n) {

  32.         case SDHC_RESULT_OK: serial_print("OK\n"); break;

  33.         case SDHC_RESULT_ERROR: serial_print("R/W Error\n"); break;

  34.         case SDHC_RESULT_WRPRT: serial_print("Write Protect\n"); break;

  35.         case SDHC_RESULT_NOT_READY: serial_print("Not Ready\n"); break;

  36.         case SDHC_RESULT_PARERR: serial_print("Invalid Param\n"); break;

  37.         case SDHC_RESULT_NO_RESPONSE: serial_print("No Response\n"); break;

  38.         default: serial_print("Unknown result\n");

  39.         }

  40.   }*/

  41. 

  42. 

  43. #define IO_SDHC_ATTRIBS (IO_DEV_ATTR_READ | IO_DEV_ATTR_REMOVE | IO_DEV_ATTR_SEEK | IO_DEV_ATTR_WRITE | IO_DEV_ATTR_BLOCK_MODE)

  44. 

  45. #define SDHC_XFERTYP_RSPTYP_NO              (0x00)

  46. #define SDHC_XFERTYP_RSPTYP_136             (0x01)

  47. #define SDHC_XFERTYP_RSPTYP_48              (0x02)

  48. #define SDHC_XFERTYP_RSPTYP_48BUSY          (0x03)

  49. 

  50. #define SDHC_XFERTYP_CMDTYP_ABORT           (0x03)

  51. 

  52. #define SDHC_PROCTL_EMODE_INVARIANT         (0x02)

  53. 

  54. #define SDHC_PROCTL_DTW_1BIT                (0x00)

  55. #define SDHC_PROCTL_DTW_4BIT                (0x01)

  56. #define SDHC_PROCTL_DTW_8BIT                (0x10)

  57. 

  58. #define SDHC_INITIALIZATION_MAX_CNT 100000

  59. 

  60. /* SDHC commands */

  61. #define SDHC_CMD0                           (0)

  62. #define SDHC_CMD1                           (1)

  63. #define SDHC_CMD2                           (2)

  64. #define SDHC_CMD3                           (3)

  65. #define SDHC_CMD4                           (4)

  66. #define SDHC_CMD5                           (5)

  67. #define SDHC_CMD6                           (6)

  68. #define SDHC_CMD7                           (7)

  69. #define SDHC_CMD8                           (8)

  70. #define SDHC_CMD9                           (9)

  71. #define SDHC_CMD10                          (10)

  72. #define SDHC_CMD11                          (11)

  73. #define SDHC_CMD12                          (12)

  74. #define SDHC_CMD13                          (13)

  75. #define SDHC_CMD15                          (15)

  76. #define SDHC_CMD16                          (16)

  77. #define SDHC_CMD17                          (17)

  78. #define SDHC_CMD18                          (18)

  79. #define SDHC_CMD20                          (20)

  80. #define SDHC_CMD24                          (24)

  81. #define SDHC_CMD25                          (25)

  82. #define SDHC_CMD26                          (26)

  83. #define SDHC_CMD27                          (27)

  84. #define SDHC_CMD28                          (28)

  85. #define SDHC_CMD29                          (29)

  86. #define SDHC_CMD30                          (30)

  87. #define SDHC_CMD32                          (32)

  88. #define SDHC_CMD33                          (33)

  89. #define SDHC_CMD34                          (34)

  90. #define SDHC_CMD35                          (35)

  91. #define SDHC_CMD36                          (36)

  92. #define SDHC_CMD37                          (37)

  93. #define SDHC_CMD38                          (38)

  94. #define SDHC_CMD39                          (39)

  95. #define SDHC_CMD40                          (40)

  96. #define SDHC_CMD42                          (42)

  97. #define SDHC_CMD52                          (52)

  98. #define SDHC_CMD53                          (53)

  99. #define SDHC_CMD55                          (55)

  100. #define SDHC_CMD56                          (56)

  101. #define SDHC_CMD59                          (59)

  102. #define SDHC_CMD60                          (60)

  103. #define SDHC_CMD61                          (61)

  104. #define SDHC_ACMD6                          (0x40 + 6)

  105. #define SDHC_ACMD13                         (0x40 + 13)

  106. #define SDHC_ACMD22                         (0x40 + 22)

  107. #define SDHC_ACMD23                         (0x40 + 23)

  108. #define SDHC_ACMD41                         (0x40 + 41)

  109. #define SDHC_ACMD42                         (0x40 + 42)

  110. #define SDHC_ACMD51                         (0x40 + 51)

  111. 

  112. #define SDHC_FIFO_BUFFER_SIZE               16

  113. #define SDHC_BLOCK_SIZE                     512

  114. 

  115. #if defined(__IMXRT1062__)

  116. #define MAKE_REG_MASK(m,s) (((uint32_t)(((uint32_t)(m) << s))))

  117. #define MAKE_REG_GET(x,m,s) (((uint32_t)(((uint32_t)(x)>>s) & m)))

  118. #define MAKE_REG_SET(x,m,s) (((uint32_t)(((uint32_t)(x) & m) << s)))

  119. 

  120. #define SDHC_BLKATTR_BLKSIZE_MASK MAKE_REG_MASK(0x1FFF,0) //uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size Mask

  121. #define SDHC_BLKATTR_BLKSIZE(n)   MAKE_REG_SET(n,0x1FFF,0) //uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size

  122. #define SDHC_BLKATTR_BLKCNT_MASK  MAKE_REG_MASK(0x1FFF,16) //((uint32_t)0x1FFF<<16)

  123. #define SDHC_BLKATTR_BLKCNT(n)    MAKE_REG_SET(n,0x1FFF,16) //(uint32_t)(((n) & 0x1FFF)<<16) // Blocks Count For Current Transfer

  124. 

  125. #define SDHC_XFERTYP_CMDINX(n)  MAKE_REG_SET(n,0x3F,24) //(uint32_t)(((n) & 0x3F)<<24)// Command Index

  126. #define SDHC_XFERTYP_CMDTYP(n)  MAKE_REG_SET(n,0x3,22) //(uint32_t)(((n) & 0x3)<<22)  // Command Type

  127. #define SDHC_XFERTYP_DPSEL    MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data Present Select

  128. #define SDHC_XFERTYP_CICEN    MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Command Index Check Enable

  129. #define SDHC_XFERTYP_CCCEN    MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command CRC Check Enable

  130. #define SDHC_XFERTYP_RSPTYP(n)  MAKE_REG_SET(n,0x3,16) //(uint32_t)(((n) & 0x3)<<16)  // Response Type Select

  131. #define SDHC_XFERTYP_MSBSEL   MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Multi/Single Block Select

  132. #define SDHC_XFERTYP_DTDSEL   MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Data Transfer Direction Select

  133. #define SDHC_XFERTYP_AC12EN   MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Auto CMD12 Enable

  134. #define SDHC_XFERTYP_BCEN   MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Block Count Enable

  135. #define SDHC_XFERTYP_DMAEN    MAKE_REG_MASK(0x3,0) //((uint32_t)0x00000001)   // DMA Enable

  136. 

  137. #define SDHC_PRSSTAT_DLSL_MASK    MAKE_REG_MASK(0xFF,24)  //((uint32_t)0xFF000000)    // DAT Line Signal Level

  138. #define SDHC_PRSSTAT_CLSL     MAKE_REG_MASK(0x1,23) //((uint32_t)0x00800000)    // CMD Line Signal Level

  139. #define SDHC_PRSSTAT_WPSPL      MAKE_REG_MASK(0x1,19) //

  140. #define SDHC_PRSSTAT_CDPL     MAKE_REG_MASK(0x1,18) //

  141. #define SDHC_PRSSTAT_CINS     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Card Inserted

  142. #define SDHC_PRSSTAT_TSCD     MAKE_REG_MASK(0x1,15)

  143. #define SDHC_PRSSTAT_RTR      MAKE_REG_MASK(0x1,12)

  144. #define SDHC_PRSSTAT_BREN     MAKE_REG_MASK(0x1,11) //((uint32_t)0x00000800)    // Buffer Read Enable

  145. #define SDHC_PRSSTAT_BWEN     MAKE_REG_MASK(0x1,10) //((uint32_t)0x00000400)    // Buffer Write Enable

  146. #define SDHC_PRSSTAT_RTA      MAKE_REG_MASK(0x1,9) //((uint32_t)0x00000200)   // Read Transfer Active

  147. #define SDHC_PRSSTAT_WTA      MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Write Transfer Active

  148. #define SDHC_PRSSTAT_SDOFF      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // SD Clock Gated Off Internally

  149. #define SDHC_PRSSTAT_PEROFF     MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // SDHC clock Gated Off Internally

  150. #define SDHC_PRSSTAT_HCKOFF     MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // System Clock Gated Off Internally

  151. #define SDHC_PRSSTAT_IPGOFF     MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Bus Clock Gated Off Internally

  152. #define SDHC_PRSSTAT_SDSTB      MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // SD Clock Stable

  153. #define SDHC_PRSSTAT_DLA      MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Data Line Active

  154. #define SDHC_PRSSTAT_CDIHB      MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Command Inhibit (DAT)

  155. #define SDHC_PRSSTAT_CIHB     MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Inhibit (CMD)

  156. 

  157. #define SDHC_PROTCT_NONEXACT_BLKRD  MAKE_REG_MASK(0x1,30) //

  158. #define SDHC_PROTCT_BURST_LENEN(n)  MAKE_REG_SET(n,0x7,12) //

  159. #define SDHC_PROCTL_WECRM     MAKE_REG_MASK(0x1,26) //((uint32_t)0x04000000)    // Wakeup Event Enable On SD Card Removal

  160. #define SDHC_PROCTL_WECINS      MAKE_REG_MASK(0x1,25) //((uint32_t)0x02000000)    // Wakeup Event Enable On SD Card Insertion

  161. #define SDHC_PROCTL_WECINT      MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Wakeup Event Enable On Card Interrupt

  162. #define SDHC_PROCTL_RD_DONE_NOBLK MAKE_REG_MASK(0x1,20) //

  163. #define SDHC_PROCTL_IABG      MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Interrupt At Block Gap

  164. #define SDHC_PROCTL_RWCTL     MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Read Wait Control

  165. #define SDHC_PROCTL_CREQ      MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Continue Request

  166. #define SDHC_PROCTL_SABGREQ     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Stop At Block Gap Request

  167. #define SDHC_PROCTL_DMAS(n)     MAKE_REG_SET(n,0x3,8) //(uint32_t)(((n) & 0x3)<<8)  // DMA Select

  168. #define SDHC_PROCTL_CDSS      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Detect Signal Selection

  169. #define SDHC_PROCTL_CDTL      MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Detect Test Level

  170. #define SDHC_PROCTL_EMODE(n)    MAKE_REG_SET(n,0x3,4) //(uint32_t)(((n) & 0x3)<<4)  // Endian Mode

  171. #define SDHC_PROCTL_EMODE_MASK  MAKE_REG_MASK(0x3,4) //(uint32_t)((0x3)<<4) // Endian Mode

  172. #define SDHC_PROCTL_D3CD      MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DAT3 As Card Detection Pin

  173. #define SDHC_PROCTL_DTW(n)      MAKE_REG_SET(n,0x3,1) //(uint32_t)(((n) & 0x3)<<1)  // Data Transfer Width, 0=1bit, 1=4bit, 2=8bit

  174. #define SDHC_PROCTL_DTW_MASK    MAKE_REG_MASK(0x3,1) //((uint32_t)0x00000006)

  175. #define SDHC_PROCTL_LCTL      MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // LED Control

  176. 

  177. #define SDHC_SYSCTL_RSTT      MAKE_REG_MASK(0x1,28) //

  178. #define SDHC_SYSCTL_INITA     MAKE_REG_MASK(0x1,27) //((uint32_t)0x08000000)    // Initialization Active

  179. #define SDHC_SYSCTL_RSTD      MAKE_REG_MASK(0x1,26) //((uint32_t)0x04000000)    // Software Reset For DAT Line

  180. #define SDHC_SYSCTL_RSTC      MAKE_REG_MASK(0x1,25) //((uint32_t)0x02000000)    // Software Reset For CMD Line

  181. #define SDHC_SYSCTL_RSTA      MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Software Reset For ALL

  182. #define SDHC_SYSCTL_DTOCV(n)  MAKE_REG_SET(n,0xF,16) //(uint32_t)(((n) & 0xF)<<16)  // Data Timeout Counter Value

  183. #define SDHC_SYSCTL_DTOCV_MASK    MAKE_REG_MASK(0xF,16) //((uint32_t)0x000F0000)

  184. #define SDHC_SYSCTL_SDCLKFS(n)    MAKE_REG_SET(n,0xFF,8) //(uint32_t)(((n) & 0xFF)<<8)  // SDCLK Frequency Select

  185. #define SDHC_SYSCTL_SDCLKFS_MASK  MAKE_REG_MASK(0xFF,8) //((uint32_t)0x0000FF00)

  186. #define SDHC_SYSCTL_DVS(n)      MAKE_REG_SET(n,0xF,4) //(uint32_t)(((n) & 0xF)<<4)  // Divisor

  187. #define SDHC_SYSCTL_DVS_MASK    MAKE_REG_MASK(0xF,4)  //((uint32_t)0x000000F0)

  188. 

  189. #define SDHC_SYSCTL_SDCLKEN   ((uint32_t)0x00000008)    // SD Clock Enable

  190. #define SDHC_SYSCTL_PEREN     ((uint32_t)0x00000004)    // Peripheral Clock Enable

  191. #define SDHC_SYSCTL_HCKEN     ((uint32_t)0x00000002)    // System Clock Enable

  192. #define SDHC_SYSCTL_IPGEN     ((uint32_t)0x00000001)    // IPG Clock Enable

  193. 

  194. #define SDHC_IRQSTAT_DMAE     MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error

  195. #define SDHC_IRQSTAT_TNE      MAKE_REG_MASK(0x1,26) //

  196. #define SDHC_IRQSTAT_AC12E    MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error

  197. #define SDHC_IRQSTAT_DEBE     MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error

  198. #define SDHC_IRQSTAT_DCE      MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error

  199. #define SDHC_IRQSTAT_DTOE     MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error

  200. #define SDHC_IRQSTAT_CIE      MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error

  201. #define SDHC_IRQSTAT_CEBE     MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error

  202. #define SDHC_IRQSTAT_CCE      MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error

  203. #define SDHC_IRQSTAT_CTOE     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error

  204. #define SDHC_IRQSTAT_TP       MAKE_REG_MASK(0x1,14) //

  205. #define SDHC_IRQSTAT_RTE      MAKE_REG_MASK(0x1,12) //

  206. #define SDHC_IRQSTAT_CINT     MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Card Interrupt

  207. #define SDHC_IRQSTAT_CRM      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Removal

  208. #define SDHC_IRQSTAT_CINS     MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Insertion

  209. #define SDHC_IRQSTAT_BRR      MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Buffer Read Ready

  210. #define SDHC_IRQSTAT_BWR      MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Buffer Write Ready

  211. #define SDHC_IRQSTAT_DINT     MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DMA Interrupt

  212. #define SDHC_IRQSTAT_BGE      MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Block Gap Event

  213. #define SDHC_IRQSTAT_TC       MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Transfer Complete

  214. #define SDHC_IRQSTAT_CC       MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Complete

  215. 

  216. #define SDHC_IRQSTATEN_DMAESEN    MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error Status Enable

  217. #define SDHC_IRQSTATEN_TNESEN   MAKE_REG_MASK(0x1,26) //

  218. #define SDHC_IRQSTATEN_AC12ESEN   MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error Status Enable

  219. #define SDHC_IRQSTATEN_DEBESEN    MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error Status Enable

  220. #define SDHC_IRQSTATEN_DCESEN   MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error Status Enable

  221. #define SDHC_IRQSTATEN_DTOESEN    MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error Status Enable

  222. #define SDHC_IRQSTATEN_CIESEN   MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error Status Enable

  223. #define SDHC_IRQSTATEN_CEBESEN    MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error Status Enable

  224. #define SDHC_IRQSTATEN_CCESEN   MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error Status Enable

  225. #define SDHC_IRQSTATEN_CTOESEN    MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error Status Enable

  226. #define SDHC_IRQSTATEN_TPSEN    MAKE_REG_MASK(0x1,14) //

  227. #define SDHC_IRQSTATEN_RTESEN   MAKE_REG_MASK(0x1,12) //

  228. #define SDHC_IRQSTATEN_CINTSEN    MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Card Interrupt Status Enable

  229. #define SDHC_IRQSTATEN_CRMSEN   MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Removal Status Enable

  230. #define SDHC_IRQSTATEN_CINSEN   MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Insertion Status Enable

  231. #define SDHC_IRQSTATEN_BRRSEN   MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Buffer Read Ready Status Enable

  232. #define SDHC_IRQSTATEN_BWRSEN   MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Buffer Write Ready Status Enable

  233. #define SDHC_IRQSTATEN_DINTSEN    MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DMA Interrupt Status Enable

  234. #define SDHC_IRQSTATEN_BGESEN   MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Block Gap Event Status Enable

  235. #define SDHC_IRQSTATEN_TCSEN    MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Transfer Complete Status Enable

  236. #define SDHC_IRQSTATEN_CCSEN    MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Complete Status Enable

  237. 

  238. #define SDHC_IRQSIGEN_DMAEIEN   MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error Interrupt Enable

  239. #define SDHC_IRQSIGEN_TNEIEN    MAKE_REG_MASK(0x1,26) //

  240. #define SDHC_IRQSIGEN_AC12EIEN    MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error Interrupt Enable

  241. #define SDHC_IRQSIGEN_DEBEIEN   MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error Interrupt Enable

  242. #define SDHC_IRQSIGEN_DCEIEN    MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error Interrupt Enable

  243. #define SDHC_IRQSIGEN_DTOEIEN   MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error Interrupt Enable

  244. #define SDHC_IRQSIGEN_CIEIEN    MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error Interrupt Enable

  245. #define SDHC_IRQSIGEN_CEBEIEN   MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error Interrupt Enable

  246. #define SDHC_IRQSIGEN_CCEIEN    MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error Interrupt Enable

  247. #define SDHC_IRQSIGEN_CTOEIEN   MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error Interrupt Enable

  248. #define SDHC_IRQSIGEN_TPIEN     MAKE_REG_MASK(0x1,14) //

  249. #define SDHC_IRQSIGEN_RTEIEN    MAKE_REG_MASK(0x1,12) //

  250. #define SDHC_IRQSIGEN_CINTIEN   MAKE_REG_MASK(0x1,8)  //((uint32_t)0x00000100)    // Card Interrupt Interrupt Enable

  251. #define SDHC_IRQSIGEN_CRMIEN    MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Card Removal Interrupt Enable

  252. #define SDHC_IRQSIGEN_CINSIEN   MAKE_REG_MASK(0x1,6)  //((uint32_t)0x00000040)    // Card Insertion Interrupt Enable

  253. #define SDHC_IRQSIGEN_BRRIEN    MAKE_REG_MASK(0x1,5)  //((uint32_t)0x00000020)    // Buffer Read Ready Interrupt Enable

  254. #define SDHC_IRQSIGEN_BWRIEN    MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Buffer Write Ready Interrupt Enable

  255. #define SDHC_IRQSIGEN_DINTIEN   MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // DMA Interrupt Interrupt Enable

  256. #define SDHC_IRQSIGEN_BGEIEN    MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Block Gap Event Interrupt Enable

  257. #define SDHC_IRQSIGEN_TCIEN     MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Transfer Complete Interrupt Enable

  258. #define SDHC_IRQSIGEN_CCIEN     MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Command Complete Interrupt Enable

  259. 

  260. #define SDHC_AC12ERR_SMPLCLK_SEL  MAKE_REG_MASK(0x1,23) //

  261. #define SDHC_AC12ERR_EXEC_TUNING  MAKE_REG_MASK(0x1,22) //

  262. #define SDHC_AC12ERR_CNIBAC12E    MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Command Not Issued By Auto CMD12 Error

  263. #define SDHC_AC12ERR_AC12IE     MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Auto CMD12 Index Error

  264. #define SDHC_AC12ERR_AC12CE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // Auto CMD12 CRC Error

  265. #define SDHC_AC12ERR_AC12EBE    MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Auto CMD12 End Bit Error

  266. #define SDHC_AC12ERR_AC12TOE    MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Auto CMD12 Timeout Error

  267. #define SDHC_AC12ERR_AC12NE     MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Auto CMD12 Not Executed

  268. 

  269. #define SDHC_HTCAPBLT_VS18      MAKE_REG_MASK(0x1,26) //

  270. #define SDHC_HTCAPBLT_VS30      MAKE_REG_MASK(0x1,25) //

  271. #define SDHC_HTCAPBLT_VS33      MAKE_REG_MASK(0x1,24) //

  272. #define SDHC_HTCAPBLT_SRS     MAKE_REG_MASK(0x1,23) //

  273. #define SDHC_HTCAPBLT_DMAS      MAKE_REG_MASK(0x1,22) //

  274. #define SDHC_HTCAPBLT_HSS     MAKE_REG_MASK(0x1,21) //

  275. #define SDHC_HTCAPBLT_ADMAS     MAKE_REG_MASK(0x1,20) //

  276. #define SDHC_HTCAPBLT_MBL_VAL   MAKE_REG_GET((USDHC1_HOST_CTRL_CAP),0x7,16) //

  277. #define SDHC_HTCAPBLT_RETUN_MODE  MAKE_REG_GET((USDHC1_HOST_CTRL_CAP),0x3,14) //

  278. #define SDHC_HTCAPBLT_TUNE_SDR50  MAKE_REG_MASK(0x1,13) //

  279. #define SDHC_HTCAPBLT_TIME_RETUN(n) MAKE_REG_SET(n,0xF,8) //

  280. 

  281. #define SDHC_WML_WR_BRSTLEN_MASK    MAKE_REG_MASK(0x1F,24)  //

  282. #define SDHC_WML_RD_BRSTLEN_MASK    MAKE_REG_MASK(0x1F,8)   //

  283. #define SDHC_WML_WR_WML_MASK      MAKE_REG_MASK(0xFF,16)  //

  284. #define SDHC_WML_RD_WML_MASK      MAKE_REG_MASK(0xFF,0)   //

  285. #define SDHC_WML_WR_BRSTLEN(n)    MAKE_REG_SET(n,0x1F,24) //(uint32_t)(((n) & 0x7F)<<16)  // Write Burst Len

  286. #define SDHC_WML_RD_BRSTLEN(n)    MAKE_REG_SET(n,0x1F,8)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Burst Len

  287. #define SDHC_WML_WR_WML(n)      MAKE_REG_SET(n,0xFF,16) //(uint32_t)(((n) & 0x7F)<<16)  // Write Watermark Level

  288. #define SDHC_WML_RD_WML(n)      MAKE_REG_SET(n,0xFF,0)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Watermark Level

  289. #define SDHC_WML_WRWML(n)     MAKE_REG_SET(n,0xFF,16) //(uint32_t)(((n) & 0x7F)<<16)  // Write Watermark Level

  290. #define SDHC_WML_RDWML(n)     MAKE_REG_SET(n,0xFF,0)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Watermark Level

  291. 

  292. // Teensy 4.0 only

  293. #define SDHC_MIX_CTRL_DMAEN     MAKE_REG_MASK(0x1,0)  //

  294. #define SDHC_MIX_CTRL_BCEN      MAKE_REG_MASK(0x1,1)  //

  295. #define SDHC_MIX_CTRL_AC12EN    MAKE_REG_MASK(0x1,2)  //

  296. #define SDHC_MIX_CTRL_DDR_EN    MAKE_REG_MASK(0x1,3)  //

  297. #define SDHC_MIX_CTRL_DTDSEL    MAKE_REG_MASK(0x1,4)  //

  298. #define SDHC_MIX_CTRL_MSBSEL    MAKE_REG_MASK(0x1,5)  //

  299. #define SDHC_MIX_CTRL_NIBBLE_POS  MAKE_REG_MASK(0x1,6)  //

  300. #define SDHC_MIX_CTRL_AC23EN    MAKE_REG_MASK(0x1,7)  //

  301. 

  302. #define SDHC_FEVT_CINT        MAKE_REG_MASK(0x1,31) //((uint32_t)0x80000000)    // Force Event Card Interrupt

  303. #define SDHC_FEVT_DMAE        MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // Force Event DMA Error

  304. #define SDHC_FEVT_AC12E       MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Force Event Auto CMD12 Error

  305. #define SDHC_FEVT_DEBE        MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Force Event Data End Bit Error

  306. #define SDHC_FEVT_DCE       MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Force Event Data CRC Error

  307. #define SDHC_FEVT_DTOE        MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Force Event Data Timeout Error

  308. #define SDHC_FEVT_CIE       MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Force Event Command Index Error

  309. #define SDHC_FEVT_CEBE        MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Force Event Command End Bit Error

  310. #define SDHC_FEVT_CCE       MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Force Event Command CRC Error

  311. #define SDHC_FEVT_CTOE        MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Force Event Command Timeout Error

  312. #define SDHC_FEVT_CNIBAC12E     MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Force Event Command Not Executed By Auto Command 12 Error

  313. #define SDHC_FEVT_AC12IE      MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Force Event Auto Command 12 Index Error

  314. #define SDHC_FEVT_AC12EBE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // Force Event Auto Command 12 End Bit Error

  315. #define SDHC_FEVT_AC12CE      MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Force Event Auto Command 12 CRC Error

  316. #define SDHC_FEVT_AC12TOE     MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Force Event Auto Command 12 Time Out Error

  317. #define SDHC_FEVT_AC12NE      MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Force Event Auto Command 12 Not Executed

  318. 

  319. #define SDHC_ADMAES_ADMADCE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)

  320. #define SDHC_ADMAES_ADMALME     MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)

  321. #define SDHC_ADMAES_ADMAES_MASK   MAKE_REG_MASK(0x3,0)  //((uint32_t)0x00000003)

  322. 

  323. #define SDHC_MMCBOOT_BOOTBLKCNT(n)  MAKE_REG_MASK(0xFF,16)  //(uint32_t)(((n) & 0xFFF)<<16) // stop at block gap value of automatic mode

  324. #define SDHC_MMCBOOT_AUTOSABGEN   MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // enable auto stop at block gap function

  325. #define SDHC_MMCBOOT_BOOTEN     MAKE_REG_MASK(0x1,6)  //((uint32_t)0x00000040)    // Boot Mode Enable

  326. #define SDHC_MMCBOOT_BOOTMODE   MAKE_REG_MASK(0x1,5)  //((uint32_t)0x00000020)    // Boot Mode Select

  327. #define SDHC_MMCBOOT_BOOTACK    MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Boot Ack Mode Select

  328. #define SDHC_MMCBOOT_DTOCVACK(n)  MAKE_REG_MASK(0xF,0)  //(uint32_t)(((n) & 0xF)<<0)  // Boot ACK Time Out Counter Value

  329. //#define SDHC_HOSTVER    (*(volatile uint32_t *)0x400B10FC) // Host Controller Version

  330. 

  331. #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK 0x3f

  332. #define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((n) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)

  333. #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f<<8)

  334. #define CCM_ANALOG_PFD_528_PFD1_FRAC(n) (((n)<<8) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)

  335. #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f<<16)

  336. #define CCM_ANALOG_PFD_528_PFD2_FRAC(n) (((n)<<16) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)

  337. #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK ((0x3f<<24)

  338. #define CCM_ANALOG_PFD_528_PFD3_FRAC(n) (((n)<<24) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)

  339. 

  340. #define SDHC_DSADDR       (USDHC1_DS_ADDR ) // DMA System Address register

  341. #define SDHC_BLKATTR      (USDHC1_BLK_ATT) // Block Attributes register

  342. #define SDHC_CMDARG       (USDHC1_CMD_ARG) // Command Argument register

  343. #define SDHC_XFERTYP      (USDHC1_CMD_XFR_TYP) // Transfer Type register

  344. #define SDHC_CMDRSP0      (USDHC1_CMD_RSP0) // Command Response 0

  345. #define SDHC_CMDRSP1      (USDHC1_CMD_RSP1) // Command Response 1

  346. #define SDHC_CMDRSP2      (USDHC1_CMD_RSP2) // Command Response 2

  347. #define SDHC_CMDRSP3      (USDHC1_CMD_RSP3) // Command Response 3

  348. #define SDHC_DATPORT      (USDHC1_DATA_BUFF_ACC_PORT) // Buffer Data Port register

  349. #define SDHC_PRSSTAT      (USDHC1_PRES_STATE) // Present State register

  350. #define SDHC_PROCTL       (USDHC1_PROT_CTRL) // Protocol Control register

  351. #define SDHC_SYSCTL       (USDHC1_SYS_CTRL) // System Control register

  352. #define SDHC_IRQSTAT      (USDHC1_INT_STATUS) // Interrupt Status register

  353. #define SDHC_IRQSTATEN      (USDHC1_INT_STATUS_EN) // Interrupt Status Enable register

  354. #define SDHC_IRQSIGEN     (USDHC1_INT_SIGNAL_EN) // Interrupt Signal Enable register

  355. #define SDHC_AC12ERR      (USDHC1_AUTOCMD12_ERR_STATUS) // Auto CMD12 Error Status Register

  356. #define SDHC_HTCAPBLT     (USDHC1_HOST_CTRL_CAP) // Host Controller Capabilities

  357. #define SDHC_WML        (USDHC1_WTMK_LVL) // Watermark Level Register

  358. #define SDHC_MIX_CTRL     (USDHC1_MIX_CTRL) // Mixer Control

  359. #define SDHC_FEVT       (USDHC1_FORCE_EVENT) // Force Event register

  360. #define SDHC_ADMAES       (USDHC1_ADMA_ERR_STATUS) // ADMA Error Status register

  361. #define SDHC_ADSADDR      (USDHC1_ADMA_SYS_ADDR) // ADMA System Addressregister

  362. #define SDHC_VENDOR       (USDHC1_VEND_SPEC) // Vendor Specific register

  363. #define SDHC_MMCBOOT      (USDHC1_MMC_BOOT) // MMC Boot register

  364. #define SDHC_VENDOR2    (USDHC2_VEND_SPEC2) // Vendor Specific2 register

  365. //

  366. //#define IRQ_SDHC    IRQ_SDHC1

  367. 

  368. #define SDHC_MAX_DVS (0xF + 1U)

  369. #define SDHC_MAX_CLKFS (0xFF + 1U)

  370. #define SDHC_PREV_DVS(x) ((x) -= 1U)

  371. #define SDHC_PREV_CLKFS(x, y) ((x) >>= (y))

  372. 

  373. #define CCM_CSCDR1_USDHC1_CLK_PODF_MASK (0x7<<11)

  374. #define CCM_CSCDR1_USDHC1_CLK_PODF(n) (((n)&0x7)<<11)

  375. 

  376. #define IOMUXC_SW_PAD_CTL_PAD_SRE     ((0x1<)<0)

  377. #define IOMUXC_SW_PAD_CTL_PAD_PKE     ((0x1)<<12)

  378. #define IOMUXC_SW_PAD_CTL_PAD_PUE       ((0x1)<<13)

  379. #define IOMUXC_SW_PAD_CTL_PAD_HYS       ((0x1)<<16)

  380. #define IOMUXC_SW_PAD_CTL_PAD_SPEED(n)  (((n)&0x3)<<6)

  381. #define IOMUXC_SW_PAD_CTL_PAD_PUS(n)    (((n)&0x3)<<14)

  382. #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK  ((0x3)<<14)

  383. #define IOMUXC_SW_PAD_CTL_PAD_DSE(n)    (((n)&0x7)<<3)

  384. #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK  ((0x7)<<3)

  385. 

  386. #endif // __IMXRT1062__

  387. 

  388. #define SDHC_IRQSIGEN_DMA_MASK (SDHC_IRQSIGEN_TCIEN | SDHC_IRQSIGEN_DINTIEN | SDHC_IRQSIGEN_DMAEIEN)

  389. #define CARD_STATUS_READY_FOR_DATA  (1UL << 8)

  390. 

  391. /******************************************************************************

  392.   Types

  393. ******************************************************************************/

  394. typedef struct {

  395.   uint8_t  status;

  396.   uint8_t  highCapacity;

  397.   uint8_t  version2;

  398.   uint8_t  tranSpeed;

  399.   uint32_t address;

  400.   uint32_t numBlocks;

  401.   uint32_t lastCardStatus;

  402. } SD_CARD_DESCRIPTOR;

  403. 

  404. /******************************************************************************

  405.   Global functions

  406. ******************************************************************************/

  407. 

  408. /******************************************************************************

  409.   Private variables

  410. ******************************************************************************/

  411. 

  412. static SD_CARD_DESCRIPTOR sdCardDesc;

  413. static volatile uint32_t dmaDone=0;

  414. //

  415. 

  416. /******************************************************************************

  417.   Forward declaration of private functions

  418. ******************************************************************************/

  419. static void sdhc_setSdclk(uint32_t kHzMax);

  420. 

  421. static uint8_t SDHC_Init(void);

  422. static void SDHC_InitGPIO(void);

  423. static void SDHC_ReleaseGPIO(void);

  424. //static void SDHC_SetClock(uint32_t sysctl);

  425. static uint32_t SDHC_WaitStatus(uint32_t mask);

  426. static int SDHC_ReadBlock(uint32_t* pData);

  427. static int SDHC_WriteBlock(const uint32_t* pData);

  428. static int SDHC_CMD_Do(uint32_t xfertyp);

  429. static int SDHC_CMD0_GoToIdle(void);

  430. static int SDHC_CMD2_Identify(void);

  431. static int SDHC_CMD3_GetAddress(void);

  432. static int SDHC_ACMD6_SetBusWidth(uint32_t address, uint32_t width);

  433. static int SDHC_CMD7_SelectCard(uint32_t address);

  434. static int SDHC_CMD8_SetInterface(uint32_t cond);

  435. static int SDHC_CMD9_GetParameters(uint32_t address);

  436. static int SDHC_CMD12_StopTransfer(void);

  437. static int SDHC_CMD12_StopTransferWaitForBusy(void);

  438. static int SDHC_CMD16_SetBlockSize(uint32_t block_size);

  439. static int SDHC_CMD17_ReadBlock(uint32_t sector);

  440. static int SDHC_CMD24_WriteBlock(uint32_t sector);

  441. static int SDHC_ACMD41_SendOperationCond(uint32_t cond);

  442. 

  443. /******************************************************************************

  444. 

  445.     Public functions

  446. 

  447. ******************************************************************************/

  448. uint8_t SDHC_CardGetType(void)

  449. {

  450.   if (sdCardDesc.status) return 0;

  451.   if (sdCardDesc.version2 == 0) return 1; // SD_CARD_TYPE_SD1

  452.   if (sdCardDesc.highCapacity == 0) return 2; // SD_CARD_TYPE_SD2

  453.   return 3; // SD_CARD_TYPE_SDHC

  454. }

  455. 

  456. //-----------------------------------------------------------------------------

  457. // initialize the SDHC Controller and SD Card

  458. // returns status of initialization(OK, nonInit, noCard, CardProtected)

  459. uint8_t SDHC_CardInit(void)

  460. {

  461.   uint8_t resS;

  462.   int resR;

  463. 

  464.   resS = SDHC_Init();

  465. 

  466.   sdCardDesc.status = resS;

  467.   sdCardDesc.address = 0;

  468.   sdCardDesc.highCapacity = 0;

  469.   sdCardDesc.version2 = 0;

  470.   sdCardDesc.numBlocks = 0;

  471. 

  472.   if (resS)

  473.     return resS;

  474. 

  475.   SDHC_IRQSIGEN = 0;

  476. 

  477.   resR = SDHC_CMD0_GoToIdle();

  478.   if (resR) {

  479.     sdCardDesc.status = SDHC_STATUS_NOINIT;

  480.     return SDHC_STATUS_NOINIT;

  481.   }

  482. 

  483.   resR = SDHC_CMD8_SetInterface(0x000001AA); // 3.3V and AA check pattern

  484.   if (resR == SDHC_RESULT_OK) {

  485.       if (SDHC_CMDRSP0 != 0x000001AA) {

  486.         sdCardDesc.status = SDHC_STATUS_NOINIT;

  487.         return SDHC_STATUS_NOINIT;

  488.       }

  489.       sdCardDesc.highCapacity = 1;

  490.   } else if (resR == SDHC_RESULT_NO_RESPONSE) {

  491.       // version 1 cards do not respond to CMD8

  492.   } else {

  493.     sdCardDesc.status = SDHC_STATUS_NOINIT;

  494.     return SDHC_STATUS_NOINIT;

  495.   }

  496. 

  497.   if (SDHC_ACMD41_SendOperationCond(0))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  498. 

  499.   if (SDHC_CMDRSP0 & 0x300000) {

  500.     uint32_t condition = 0x00300000;

  501.     if (sdCardDesc.highCapacity) condition |= 0x40000000;

  502.     //

  503.     uint32_t ii = 0;

  504.     do {

  505.       ii++;

  506.       if (SDHC_ACMD41_SendOperationCond(condition)) {

  507.         resS = SDHC_STATUS_NOINIT;

  508.         break;

  509.       }

  510.     } while ((!(SDHC_CMDRSP0 & 0x80000000)) && (ii < SDHC_INITIALIZATION_MAX_CNT));

  511. 

  512.     if (resS) return resS;

  513. 

  514.     if ((ii >= SDHC_INITIALIZATION_MAX_CNT) || (!(SDHC_CMDRSP0 & 0x40000000)))

  515.       sdCardDesc.highCapacity = 0;

  516.   }

  517. 

  518.   // Card identify

  519.   if (SDHC_CMD2_Identify())  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  520. 

  521.   // Get card address

  522.   if (SDHC_CMD3_GetAddress())  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  523. 

  524.   sdCardDesc.address = SDHC_CMDRSP0 & 0xFFFF0000;

  525. 

  526.   // Get card parameters

  527.   if (SDHC_CMD9_GetParameters(sdCardDesc.address))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  528. 

  529.   if (!(SDHC_CMDRSP3 & 0x00C00000)) {

  530.     uint32_t read_bl_len, c_size, c_size_mult;

  531. 

  532.     read_bl_len = (SDHC_CMDRSP2 >> 8) & 0x0F;

  533.     c_size = SDHC_CMDRSP2 & 0x03;

  534.     c_size = (c_size << 10) | (SDHC_CMDRSP1 >> 22);

  535.     c_size_mult = (SDHC_CMDRSP1 >> 7) & 0x07;

  536.     sdCardDesc.numBlocks = (c_size + 1) * (1 << (c_size_mult + 2)) * (1 << (read_bl_len - 9));

  537.   } else {

  538.     uint32_t c_size;

  539.     sdCardDesc.version2 = 1;

  540.     c_size = (SDHC_CMDRSP1 >> 8) & 0x003FFFFF;

  541.     sdCardDesc.numBlocks = (c_size + 1) << 10;

  542.   }

  543. 

  544.   // Select card

  545.   if (SDHC_CMD7_SelectCard(sdCardDesc.address)) return sdCardDesc.status = SDHC_STATUS_NOINIT;

  546. 

  547.   // Set Block Size to 512

  548.   // Block Size in SDHC Controller is already set to 512 by SDHC_Init();

  549.   // Set 512 Block size in SD card

  550.   if (SDHC_CMD16_SetBlockSize(SDHC_BLOCK_SIZE))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  551. 

  552.   // Set 4 bit data bus width

  553.   if (SDHC_ACMD6_SetBusWidth(sdCardDesc.address, 2))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  554. 

  555.   // Set Data bus width also in SDHC controller

  556.   SDHC_PROCTL &= ~SDHC_PROCTL_DTW_MASK;

  557.   SDHC_PROCTL |= SDHC_PROCTL_DTW(SDHC_PROCTL_DTW_4BIT);

  558. 

  559.   // De-Init GPIO

  560.   SDHC_ReleaseGPIO();

  561. 

  562.   // Set the SDHC default baud rate

  563.   sdhc_setSdclk(25000);

  564.   // SDHC_SetClock(SDHC_SYSCTL_25MHZ);

  565.   // TODO: use CMD6 and CMD9 to detect if card supports 50 MHz

  566.   // then use CMD4 to configure card to high speed mode,

  567.   // and SDHC_SetClock() for 50 MHz config

  568. 

  569.   // Init GPIO

  570.   SDHC_InitGPIO();

  571. 

  572.   return sdCardDesc.status;

  573. }

  574. 

  575. 

  576. //-----------------------------------------------------------------------------

  577. // FUNCTION:    SDHC_CardReadBlock (disk_read)

  578. // SCOPE:       SDHC public related function

  579. // DESCRIPTION: Function read block to disk

  580. //

  581. // PARAMETERS:  buff - pointer on buffer where read data should be stored

  582. //              sector - index of sector

  583. //

  584. // RETURNS:     result of operation

  585. //-----------------------------------------------------------------------------

  586. #if 1

  587. // read a block from disk, using polling

  588. //   buff - pointer on buffer where read data should be stored

  589. //   sector - index of start sector

  590. int SDHC_CardReadBlock(void * buff, uint32_t sector)

  591. {

  592.   int result;

  593.   uint32_t* pData = (uint32_t*)buff;

  594. 

  595.   // Check if this is ready

  596.   if (sdCardDesc.status != 0)

  597.      return SDHC_RESULT_NOT_READY;

  598. 

  599.   // Convert LBA to uint8_t address if needed

  600.   if (!sdCardDesc.highCapacity)

  601.     sector *= 512;

  602. 

  603.   SDHC_IRQSTAT = 0xffff;

  604. #if defined(__IMXRT1062__)

  605.   SDHC_MIX_CTRL |= SDHC_MIX_CTRL_DTDSEL;

  606. #endif

  607. 

  608.   // Just single block mode is needed

  609.   result = SDHC_CMD17_ReadBlock(sector);

  610.   if(result != SDHC_RESULT_OK) return result;

  611.   result = SDHC_ReadBlock(pData);

  612. 

  613.   // finish up

  614.   while (!(SDHC_IRQSTAT & SDHC_IRQSTAT_TC)) { }  // wait for transfer to complete

  615.   SDHC_IRQSTAT = (SDHC_IRQSTAT_TC | SDHC_IRQSTAT_BRR | SDHC_IRQSTAT_AC12E);

  616. 

  617.   return result;

  618. }

  619. #else

  620. // read a block from disk, using DMA & interrupts

  621. int SDHC_CardReadBlock(void * buff, uint32_t sector)

  622. {

  623.   int result=0;

  624.   uint32_t* pData = (uint32_t*)buff;

  625.   /* check alignment for DMA */

  626.   if (reinterpret_cast<uintptr_t>(static_cast<const void*>(buff)) % 4) {

  627.     return -1;

  628.   }

  629. //  Serial.print("Sector: "); Serial.println(sector); Serial.flush();

  630.   // Check if this is ready

  631.   if (sdCardDesc.status != 0) return SDHC_RESULT_NOT_READY;

  632. 

  633.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB));

  634. 

  635.   // Convert LBA to BYTE address if needed

  636.   if (!sdCardDesc.highCapacity)  sector *= 512;

  637. 

  638.   // clear status

  639.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  640. 

  641.   // use dma: disabling polling

  642.   uint32_t irqstat = SDHC_IRQSTATEN;

  643.   irqstat &= ~(SDHC_IRQSTATEN_BRRSEN | SDHC_IRQSTATEN_BWRSEN | SDHC_IRQSTATEN_CCSEN) ;

  644.   irqstat &= ~(SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN) ;

  645.   // enable status

  646.   irqstat |= SDHC_IRQSTATEN_DMAESEN | SDHC_IRQSTATEN_DINTSEN | SDHC_IRQSTATEN_TCSEN ;

  647.   SDHC_IRQSTATEN = irqstat;

  648. 

  649.   uint32_t sigen = SDHC_IRQSIGEN;

  650.   sigen |= SDHC_IRQSIGEN_DMA_MASK ;

  651. 

  652.   SDHC_SYSCTL |= SDHC_SYSCTL_HCKEN;

  653.   #if defined(__IMXRT1052__) || defined(__IMXRT1062__)

  654.     SDHC_MIX_CTRL |= SDHC_MIX_CTRL_DTDSEL ; // read

  655.     SDHC_MIX_CTRL |=  SDHC_MIX_CTRL_DMAEN ; // DMA

  656.   #endif

  657. 

  658.   uint32_t xfertyp = SDHC_XFERTYP_CMDINX(SDHC_CMD17) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) | SDHC_XFERTYP_DPSEL

  659.                      | SDHC_XFERTYP_DTDSEL | SDHC_XFERTYP_DMAEN;

  660. 

  661.   dmaDone=0;

  662.   SDHC_DSADDR  = (uint32_t)buff;

  663.   SDHC_CMDARG = sector;

  664.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  665.   SDHC_IRQSIGEN = sigen;

  666.   SDHC_XFERTYP = xfertyp;

  667.   //

  668.   while(!dmaDone);

  669.   SDHC_IRQSTAT &= (SDHC_IRQSTAT_CC | SDHC_IRQSTAT_TC);

  670. 

  671.   return result;

  672. }

  673. #endif

  674. 

  675. //-----------------------------------------------------------------------------

  676. // FUNCTION:    SDHC_CardWriteBlock (disk_write)

  677. // SCOPE:       SDHC public related function

  678. // DESCRIPTION: Function write block to disk

  679. //

  680. // PARAMETERS:  buff - pointer on buffer where is stored data

  681. //              sector - index of sector

  682. //

  683. // RETURNS:     result of operation

  684. //-----------------------------------------------------------------------------

  685. #if 1

  686. int SDHC_CardWriteBlock(const void * buff, uint32_t sector)

  687. {

  688.   int result;

  689.   const uint32_t *pData = (const uint32_t *)buff;

  690. 

  691.   // Check if this is ready

  692.   if (sdCardDesc.status != 0) return SDHC_RESULT_NOT_READY;

  693. 

  694.   // Convert LBA to uint8_t address if needed

  695.   if(!sdCardDesc.highCapacity)

  696.     sector *= 512;

  697. 

  698.   //SDHC_IRQSTAT = 0xffff;

  699.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  700. #if defined(__IMXRT1062__)

  701. 	SDHC_MIX_CTRL &= ~SDHC_MIX_CTRL_DTDSEL;

  702. #endif

  703. 

  704.   // Just single block mode is needed

  705.   result = SDHC_CMD24_WriteBlock(sector);

  706.   if (result != SDHC_RESULT_OK) return result;

  707.   result = SDHC_WriteBlock(pData);

  708. 

  709.   // finish up

  710.   while (!(SDHC_IRQSTAT & SDHC_IRQSTAT_TC)) { }  // wait for transfer to complete

  711.   SDHC_IRQSTAT = (SDHC_IRQSTAT_TC | SDHC_IRQSTAT_BWR | SDHC_IRQSTAT_AC12E);

  712. 

  713.   return result;

  714. }

  715. #else

  716. int SDHC_CardWriteBlock(const void * buff, uint32_t sector)

  717. {

  718.   int result=0;

  719.   const uint32_t *pData = (const uint32_t *)buff;

  720.   /* check alignment for DMA */

  721.   if (reinterpret_cast<uintptr_t>(static_cast<const void*>(buff)) % 4) {

  722.     return -1;

  723.   }

  724. 

  725.   // Check if this is ready

  726.   if (sdCardDesc.status != 0) return SDHC_RESULT_NOT_READY;

  727. 

  728.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) ;

  729. 

  730.   // Convert LBA to uint8_t address if needed

  731.   if (!sdCardDesc.highCapacity) sector *= 512;

  732. 

  733.   // clear status

  734.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  735. 

  736.   uint32_t irqstat = SDHC_IRQSTATEN;

  737.   // use dma: disabling polling

  738.   irqstat &= ~(SDHC_IRQSTATEN_BRRSEN | SDHC_IRQSTATEN_BWRSEN | SDHC_IRQSTATEN_CCSEN) ;

  739.   irqstat &= ~(SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN) ;

  740.   // enable status

  741.   irqstat |= /*SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN | */SDHC_IRQSTATEN_DMAESEN ;

  742.   irqstat |= SDHC_IRQSTATEN_DINTSEN | SDHC_IRQSTATEN_TCSEN ;

  743.   SDHC_IRQSTATEN = irqstat;

  744. 

  745.   uint32_t sigen = SDHC_IRQSIGEN;

  746.   sigen |= SDHC_IRQSIGEN_DMA_MASK ;

  747. 

  748.   SDHC_SYSCTL |= SDHC_SYSCTL_HCKEN;

  749. 

  750.   #if defined(__IMXRT1052__)

  751.     SDHC_MIX_CTRL &= ~ SDHC_MIX_CTRL_DTDSEL;  // write

  752.     SDHC_MIX_CTRL |=  SDHC_MIX_CTRL_DMAEN ;   //DMA

  753.   #endif

  754. 

  755.   uint32_t xfertyp = SDHC_XFERTYP_CMDINX(SDHC_CMD24) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) | SDHC_XFERTYP_DPSEL

  756.                      | SDHC_XFERTYP_DMAEN;

  757. 

  758.   dmaDone=0;

  759.   SDHC_DSADDR  = (uint32_t)buff;

  760.   SDHC_CMDARG = sector;

  761.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  762.   SDHC_IRQSIGEN = sigen;

  763.   SDHC_XFERTYP = xfertyp;

  764.   //

  765.   while(!dmaDone);

  766.   SDHC_IRQSTAT &= (SDHC_IRQSTAT_CC | SDHC_IRQSTAT_TC);

  767. 

  768.   while(SDHC_PRSSTAT & SDHC_PRSSTAT_DLA);

  769. 

  770.   //check for uSD status

  771.   do

  772.   { while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) ;

  773.     SDHC_IRQSTATEN |= SDHC_IRQSTATEN_CCSEN;

  774.     SDHC_IRQSTAT=SDHC_IRQSTAT;

  775.     // CMD13 to check uSD status

  776.     xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD13) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  777.     //

  778.     SDHC_CMDARG = sdCardDesc.address;

  779.     SDHC_XFERTYP = xfertyp;

  780.     while(!(SDHC_IRQSTAT & SDHC_IRQSTAT_CC)); SDHC_IRQSTAT &= SDHC_IRQSTAT_CC;

  781.   } while(SDHC_CMDRSP0 & 0x200); // while data?

  782. //  } while(!(SDHC_CMDRSP0 & CARD_STATUS_READY_FOR_DATA ));

  783. 

  784.   return result;

  785. }

  786. #endif

  787. 

  788. /******************************************************************************

  789. 

  790.     Private functions

  791. 

  792. ******************************************************************************/

  793. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  794.   // Teensy 3.5 & 3.6

  795.   // initialize the SDHC Controller signals

  796.   static void SDHC_InitGPIO(void)

  797.   {

  798.     PORTE_PCR0 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D1  */

  799.     PORTE_PCR1 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D0  */

  800.     PORTE_PCR2 = PORT_PCR_MUX(4) | PORT_PCR_DSE;                             /* SDHC.CLK */

  801.     PORTE_PCR3 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.CMD */

  802.     PORTE_PCR4 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D3  */

  803.     PORTE_PCR5 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D2  */

  804.   }

  805. 

  806.   // release the SDHC Controller signals

  807.   static void SDHC_ReleaseGPIO(void)

  808.   {

  809.     PORTE_PCR0 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D1  */

  810.     PORTE_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D0  */

  811.     PORTE_PCR2 = 0;           /* SDHC.CLK */

  812.     PORTE_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.CMD */

  813.     PORTE_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS; /* PULLUP SDHC.D3  */

  814.     PORTE_PCR5 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D2  */

  815.   }

  816. 

  817.   void initClock()

  818.   {

  819.   #ifdef HAS_KINETIS_MPU

  820.     // Allow SDHC Bus Master access.

  821.     MPU_RGDAAC0 |= 0x0C000000;

  822.   #endif

  823.     // Enable SDHC clock.

  824.     SIM_SCGC3 |= SIM_SCGC3_SDHC;

  825.   }

  826. 

  827.   uint32_t sdhcClock()

  828.   { return F_CPU;

  829.   }

  830. 

  831. #else

  832.   // Teensy 4.0

  833.   static void SDHC_InitGPIO(void)

  834.   {

  835.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 0; //DAT2  

  836.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 0; //DAT3  

  837.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 0; //CMD   

  838.       //3.3V                                           

  839.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 0; //CLK   

  840.       //GND                                           

  841.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 0; //DAT0 

  842.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 0; //DAT1 

  843.   

  844.       const uint32_t CLOCK_MASK = IOMUXC_SW_PAD_CTL_PAD_PKE |

  845.                                   IOMUXC_SW_PAD_CTL_PAD_DSE(1) |

  846.                                   IOMUXC_SW_PAD_CTL_PAD_SPEED(2);

  847.   

  848.       const uint32_t DATA_MASK = CLOCK_MASK |

  849.                                  (IOMUXC_SW_PAD_CTL_PAD_PUE | IOMUXC_SW_PAD_CTL_PAD_PUS(1));

  850.   

  851.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = DATA_MASK;

  852.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = DATA_MASK;

  853.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = DATA_MASK;

  854.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = CLOCK_MASK;

  855.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = DATA_MASK;

  856.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = DATA_MASK;

  857.   }

  858.   

  859.   static void SDHC_ReleaseGPIO(void)

  860.   {

  861.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 5; //GPIO3_IO16

  862.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 5; //GPIO3_IO17

  863.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 5; //GPIO3_IO12

  864.     //3.3V

  865.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 5; //GPIO3_IO13

  866.     //GND

  867.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 5; //GPIO3_IO14

  868.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 5; //GPIO3_IO15

  869.   }

  870.   

  871.   void initClock()

  872.   {

  873.     /* set PDF_528 PLL2PFD0 */

  874.     CCM_ANALOG_PFD_528 |= (1 << 7);

  875.     CCM_ANALOG_PFD_528 &= ~(0x3F << 0);

  876.     CCM_ANALOG_PFD_528 |= ((24) & 0x3F << 0); // 12 - 35

  877.     CCM_ANALOG_PFD_528 &= ~(1 << 7);

  878.   

  879.     /* Enable USDHC clock. */

  880.     CCM_CCGR6 |= CCM_CCGR6_USDHC1(CCM_CCGR_ON);

  881.     CCM_CSCDR1 &= ~(CCM_CSCDR1_USDHC1_CLK_PODF_MASK);

  882.     //

  883.     //  CCM_CSCMR1 &= ~(CCM_CSCMR1_USDHC1_CLK_SEL);     // PLL2PFD2

  884.     CCM_CSCMR1 |= CCM_CSCMR1_USDHC1_CLK_SEL;          // PLL2PFD0

  885.     CCM_CSCDR1 |= CCM_CSCDR1_USDHC1_CLK_PODF((7)); // &0x7

  886.   

  887.     // for testing

  888.     //CCM_CCOSR = CCM_CCOSR_CLKO1_EN | CCM_CCOSR_CLKO1_DIV(7) | CCM_CCOSR_CLKO1_SEL(1); //(1: SYS_PLL/2)

  889.     //IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 6; //CCM_CLKO1 (0 is USDHC1_DAT2)

  890.     // for testing

  891.     //CCM_CCOSR |= (CCM_CCOSR_CLKO2_EN | CCM_CCOSR_CLKO2_DIV(7) | CCM_CCOSR_CLKO2_SEL(3)); //(3: usdhc1_clk_root))

  892.     //IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 6; //CCM_CLKO2 (0 is USDHC1_DAT3)

  893.   }

  894.   

  895.   uint32_t sdhcClock()

  896.   {

  897.     uint32_t divider = ((CCM_CSCDR1 >> 11) & 0x7) + 1;

  898.     uint32_t PLL2PFD0 = (528000000U * 3) / ((CCM_ANALOG_PFD_528 & 0x3F) / 6) / divider;

  899.     return PLL2PFD0;

  900.   }

  901. 

  902. #endif

  903. /* //may be useful for debugging

  904. static void printRegs()

  905. {

  906. // Serial.print("DS_ADDR: "); Serial.println(SDHC_DSADDR,HEX);        // DMA System Address register

  907.  Serial.print("BLK_ATT:       "); Serial.println(SDHC_BLKATTR,HEX);       // Block Attributes register

  908. // Serial.print("CMD_ARG: "); Serial.println(SDHC_CMDARG,HEX);        // Command Argument register

  909. // Serial.print("CMD_XFR_TYP: "); Serial.println(SDHC_XFERTYP,HEX);    // Transfer Type register

  910. // Serial.print("CMD_RSP0: "); Serial.println(SDHC_CMDRSP0,HEX);       // Command Response 0

  911. // Serial.print("CMD_RSP1: "); Serial.println(SDHC_CMDRSP1,HEX);       // Command Response 1

  912. // Serial.print("CMD_RSP2: "); Serial.println(SDHC_CMDRSP2,HEX);       // Command Response 2

  913. // Serial.print("CMD_RSP3: "); Serial.println(SDHC_CMDRSP3,HEX);       // Command Response 3

  914. // Serial.print("DATA_BUFF_ACC_POR: "); Serial.println(SDHC_DATPORT,HEX); // Buffer Data Port register

  915.  Serial.print("PRES_STATE:    "); Serial.println(SDHC_PRSSTAT,HEX);     // Present State register

  916.  Serial.print("PROT_CTRL:     "); Serial.println(SDHC_PROCTL,HEX);      // Protocol Control register

  917.  Serial.print("SYS_CTRL:      "); Serial.println(SDHC_SYSCTL,HEX);        // System Control register

  918.  Serial.print("INT_STATUS:    "); Serial.println(SDHC_IRQSTAT,HEX);      // Interrupt Status register

  919.  Serial.print("INT_STATUS_EN: "); Serial.println(SDHC_IRQSTATEN,HEX);    // Interrupt Status Enable register

  920.  Serial.print("INT_SIGNAL_EN: "); Serial.println(SDHC_IRQSIGEN,HEX);      // Interrupt Signal Enable register

  921. // Serial.print("AUTOCMD12_ERR_STATUS: "); Serial.println(SDHC_AC12ERR,HEX); // Auto CMD12 Error Status Register

  922.  Serial.print("HOST_CTRL_CAP: "); Serial.println(SDHC_HTCAPBLT,HEX);  // Host Controller Capabilities

  923.  Serial.print("WTMK_LVL:      "); Serial.println(SDHC_WML,HEX);        // Watermark Level Register

  924.  #if defined(__IMXRT1052__)

  925.  Serial.print("MIX_CTRL:      "); Serial.println(SDHC_MIX_CTRL,HEX);     // Mixer Control

  926.  #endif

  927. // Serial.print("FORCE_EVENT:   "); Serial.println(SDHC_FEVT,HEX);      // Force Event register

  928. // Serial.print("ADMA_ERR_STATUS: "); Serial.println(SDHC_ADMAES,HEX); // ADMA Error Status register

  929. // Serial.print("ADMA_SYS_ADDR: "); Serial.println(SDHC_ADSADDR,HEX);  // ADMA System Addressregister

  930.  Serial.print("VEND_SPEC:     "); Serial.println(SDHC_VENDOR,HEX);       // Vendor Specific register

  931. // Serial.print("MMC_BOOT:      "); Serial.println(SDHC_MMCBOOT,HEX);      // MMC Boot register

  932.  #if defined(__IMXRT1052__)

  933.  Serial.print("VEND_SPEC2:    "); Serial.println(SDHC_VENDOR2,HEX);    // Vendor Specific2 register

  934.  #endif

  935. }

  936. */

  937. 

  938. static void sdhc_setSdclk(uint32_t kHzMax) {

  939.   const uint32_t DVS_LIMIT = 0X10;

  940.   const uint32_t SDCLKFS_LIMIT = 0X100;

  941.   uint32_t dvs = 1;

  942.   uint32_t sdclkfs = 1;

  943.   uint32_t maxSdclk = 1000 * kHzMax;

  944. 

  945.   //  uint32_t f_pll = F_CPU;

  946.   uint32_t f_pll = sdhcClock();

  947. 

  948.   while ((f_pll / (sdclkfs * DVS_LIMIT) > maxSdclk) && (sdclkfs < SDCLKFS_LIMIT)) {

  949.     sdclkfs <<= 1;

  950.   }

  951.   while ((f_pll / (sdclkfs * dvs) > maxSdclk) && (dvs < DVS_LIMIT)) {

  952.     dvs++;

  953.   }

  954.   //uint32_t m_sdClkKhz = f_pll / (1000 * sdclkfs * dvs);

  955. 

  956.   sdclkfs >>= 1;

  957.   dvs--;

  958. 

  959. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  960.   // Disable SDHC clock.

  961.   SDHC_SYSCTL &= ~SDHC_SYSCTL_SDCLKEN;

  962. #endif

  963. 

  964.   // Change dividers.

  965.   uint32_t sysctl = SDHC_SYSCTL & ~(SDHC_SYSCTL_DTOCV_MASK

  966.                                     | SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK);

  967. 

  968.   SDHC_SYSCTL = sysctl | SDHC_SYSCTL_DTOCV(0x0E) | SDHC_SYSCTL_DVS(dvs)

  969.                 | SDHC_SYSCTL_SDCLKFS(sdclkfs);

  970. 

  971.   // Wait until the SDHC clock is stable.

  972.   while (!(SDHC_PRSSTAT & SDHC_PRSSTAT_SDSTB)) { }

  973. 

  974. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  975.   // Enable the SDHC clock.

  976.   SDHC_SYSCTL |= SDHC_SYSCTL_SDCLKEN;

  977. #endif

  978. 

  979. //  Serial.printf("setSdclk: %d %d : %x %x\n\r", f_pll, m_sdClkKhz, sdclkfs, dvs);

  980. }

  981. 

  982. #if 0

  983. void sdhc_isr(void)

  984. { SDHC_IRQSIGEN &= ~SDHC_IRQSIGEN_DMA_MASK;

  985.   //

  986. //  Serial.print("IRQ1: "); Serial.println(SDHC_IRQSTAT,HEX);

  987.   while(!(SDHC_IRQSTAT & SDHC_IRQSTAT_TC));//  SDHC_IRQSTAT &= ~SDHC_IRQSTAT_TC;

  988. 

  989.   #if defined(__IMXRT1052__)

  990.     SDHC_MIX_CTRL &= ~(SDHC_MIX_CTRL_AC23EN | SDHC_MIX_CTRL_DMAEN) ;  

  991.   #endif

  992.   // for T3.6, seems not to hurt for T4  

  993.   if(SDHC_SYSCTL & SDHC_SYSCTL_HCKEN) SDHC_SYSCTL &=  ~SDHC_SYSCTL_HCKEN;

  994.   SDHC_PROCTL &= ~SDHC_PROCTL_D3CD; SDHC_PROCTL |=  SDHC_PROCTL_D3CD;

  995. 

  996.   dmaDone=1;

  997. }

  998. #endif

  999. 

  1000. // initialize the SDHC Controller

  1001. // returns status of initialization(OK, nonInit, noCard, CardProtected)

  1002. static uint8_t SDHC_Init(void)

  1003. {

  1004.   initClock();

  1005. 

  1006.   // De-init GPIO - to prevent unwanted clocks on bus

  1007.   SDHC_ReleaseGPIO();

  1008. 

  1009.   #if defined (__IMXRT1062__)

  1010.     //SDHC_SYSCTL   |= 0xF;

  1011.     SDHC_MIX_CTRL = 0x80000000;

  1012.   #endif

  1013. 

  1014.   /* Reset SDHC */

  1015.   SDHC_SYSCTL |= SDHC_SYSCTL_RSTA | SDHC_SYSCTL_SDCLKFS(0x80);

  1016.   while (SDHC_SYSCTL & SDHC_SYSCTL_RSTA) ; // wait

  1017. 

  1018.   /* Set the SDHC initial baud rate divider and start */

  1019.   sdhc_setSdclk(400);

  1020. 

  1021.   /* Poll inhibit bits */

  1022.   while (SDHC_PRSSTAT & (SDHC_PRSSTAT_CIHB | SDHC_PRSSTAT_CDIHB)) ;

  1023. 

  1024.   /* Init GPIO again */

  1025.   SDHC_InitGPIO();

  1026. 

  1027.   /* Initial values */ // to do - Check values

  1028.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  1029.   //SDHC_PROCTL &= ~SDHC_PROCTL_DMAS(3); // clear ADMA

  1030.   //SDHC_PROCTL |=  SDHC_PROCTL_D3CD;

  1031.   //SDHC_PROCTL = SDHC_PROCTL_EMODE(SDHC_PROCTL_EMODE_INVARIANT) | SDHC_PROCTL_D3CD;

  1032.   SDHC_PROCTL = (SDHC_PROCTL & ~(SDHC_PROCTL_EMODE(3)))

  1033. 	| (SDHC_PROCTL_EMODE(SDHC_PROCTL_EMODE_INVARIANT) | SDHC_PROCTL_D3CD );

  1034.   //SDHC_WML = SDHC_WML_RDWML(SDHC_FIFO_BUFFER_SIZE) | SDHC_WML_WRWML(SDHC_FIFO_BUFFER_SIZE);

  1035.   //Serial.printf("SDHC_WML = %08X\n", SDHC_WML); // prints 08100810 (good)

  1036.   //#if defined(__IMXRT1062__)

  1037.     //SDHC_VENDOR = 0x2000F801; // (1<<29 | 0x1F<<11 | 1);

  1038.     //SDHC_VENDOR2 &= ~(1<<12); //switch off ACMD23 sharing SDMA

  1039.   //#endif

  1040. 

  1041.   /* Enable requests */

  1042.   // clear interrupt status

  1043.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  1044. 

  1045. #if 1

  1046.   SDHC_IRQSTATEN = SDHC_IRQSTATEN_DMAESEN | SDHC_IRQSTATEN_AC12ESEN | SDHC_IRQSTATEN_DEBESEN |

  1047. 	SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_DTOESEN | SDHC_IRQSTATEN_CIESEN |

  1048. 	SDHC_IRQSTATEN_CEBESEN | SDHC_IRQSTATEN_CCESEN | SDHC_IRQSTATEN_CTOESEN |

  1049. 	SDHC_IRQSTATEN_BRRSEN | SDHC_IRQSTATEN_BWRSEN | SDHC_IRQSTATEN_DINTSEN |

  1050. 	SDHC_IRQSTATEN_CRMSEN | SDHC_IRQSTATEN_TCSEN | SDHC_IRQSTATEN_CCSEN;

  1051. #else

  1052.   SDHC_IRQSTATEN =  //SDHC_IRQSTAT_CRM | SDHC_IRQSTATEN_CIESEN |

  1053.                     SDHC_IRQSTATEN_TCSEN | SDHC_IRQSTATEN_CCSEN;

  1054. 

  1055.   attachInterruptVector(IRQ_SDHC, sdhc_isr);

  1056.   NVIC_SET_PRIORITY(IRQ_SDHC, 6 * 16);

  1057.   NVIC_ENABLE_IRQ(IRQ_SDHC);

  1058. #endif

  1059. 

  1060.   // initial clocks... SD spec says only 74 clocks are needed, but if Teensy rebooted

  1061.   // while the card was in middle of an operation, thousands of clock cycles can be

  1062.   // needed to get the card to complete a prior command and return to a usable state.

  1063.   for (int ii = 0; ii < 1500; ii++) {

  1064.     SDHC_SYSCTL |= SDHC_SYSCTL_INITA;

  1065.     while (SDHC_SYSCTL & SDHC_SYSCTL_INITA) ;

  1066.   }

  1067. 

  1068.   // to do - check if this needed

  1069.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CRM;

  1070.   // Check card

  1071.   if (SDHC_PRSSTAT & SDHC_PRSSTAT_CINS) {

  1072.     return 0;

  1073.   } else {

  1074.     return SDHC_STATUS_NODISK;

  1075.   }

  1076. }

  1077. 

  1078. /******************************************************************************

  1079. 

  1080.     Private SD Card functions

  1081. 

  1082. ******************************************************************************/

  1083. 

  1084. // waits for status bits sets

  1085. static uint32_t SDHC_WaitStatus(uint32_t mask)

  1086. {

  1087.   uint32_t             result;

  1088.   uint32_t             timeout = 1 << 24;

  1089.   do

  1090.   { result = SDHC_IRQSTAT & mask;

  1091.     timeout--;

  1092.   } while (!result && (timeout));

  1093.   if (timeout) return result;

  1094.   return 0;

  1095. }

  1096. 

  1097. // reads one block

  1098. static int SDHC_ReadBlock(uint32_t* pData)

  1099. {

  1100. 	uint32_t i, irqstat;

  1101. 	const uint32_t i_max = ((SDHC_BLOCK_SIZE) / (4 * SDHC_FIFO_BUFFER_SIZE));

  1102. 

  1103. 	for (i = 0; i < i_max; i++) {

  1104. 		irqstat = SDHC_IRQSTAT;

  1105. 		SDHC_IRQSTAT = irqstat | SDHC_IRQSTAT_BRR;

  1106. 		if (irqstat & (SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE)) {

  1107. 			SDHC_IRQSTAT = irqstat | SDHC_IRQSTAT_BRR |

  1108. 				SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE;

  1109. 			SDHC_CMD12_StopTransferWaitForBusy();

  1110. 			return SDHC_RESULT_ERROR;

  1111. 		}

  1112. 		while (!(SDHC_PRSSTAT & SDHC_PRSSTAT_BREN)) { };

  1113. 		*pData++ = SDHC_DATPORT;

  1114. 		*pData++ = SDHC_DATPORT;

  1115. 		*pData++ = SDHC_DATPORT;

  1116. 		*pData++ = SDHC_DATPORT;

  1117. 		*pData++ = SDHC_DATPORT;

  1118. 		*pData++ = SDHC_DATPORT;

  1119. 		*pData++ = SDHC_DATPORT;

  1120. 		*pData++ = SDHC_DATPORT;

  1121. 		*pData++ = SDHC_DATPORT;

  1122. 		*pData++ = SDHC_DATPORT;

  1123. 		*pData++ = SDHC_DATPORT;

  1124. 		*pData++ = SDHC_DATPORT;

  1125. 		*pData++ = SDHC_DATPORT;

  1126. 		*pData++ = SDHC_DATPORT;

  1127. 		*pData++ = SDHC_DATPORT;

  1128. 		*pData++ = SDHC_DATPORT;

  1129. 	}

  1130. 	return SDHC_RESULT_OK;

  1131. }

  1132. 

  1133. // writes one block

  1134. static int SDHC_WriteBlock(const uint32_t* pData)

  1135. {

  1136. 	uint32_t i, i_max, j;

  1137. 	i_max = ((SDHC_BLOCK_SIZE) / (4 * SDHC_FIFO_BUFFER_SIZE));

  1138. 

  1139. 	for(i = 0; i < i_max; i++) {

  1140. 		while (!(SDHC_IRQSTAT & SDHC_IRQSTAT_BWR)) ; // wait

  1141. 		if (SDHC_IRQSTAT & (SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE)) {

  1142. 			SDHC_IRQSTAT |= SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE |

  1143. 				SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_BWR;

  1144. 			(void)SDHC_CMD12_StopTransferWaitForBusy();

  1145. 			return SDHC_RESULT_ERROR;

  1146. 		}

  1147. 		for(j=0; j<SDHC_FIFO_BUFFER_SIZE; j++) {

  1148. 			SDHC_DATPORT = *pData++;

  1149. 		}

  1150. 		SDHC_IRQSTAT |= SDHC_IRQSTAT_BWR;

  1151. 

  1152. 		if (SDHC_IRQSTAT & (SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE)) {

  1153. 			SDHC_IRQSTAT |= SDHC_IRQSTAT_DEBE | SDHC_IRQSTAT_DCE |

  1154. 				SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_BWR;

  1155. 			(void)SDHC_CMD12_StopTransferWaitForBusy();

  1156. 			return SDHC_RESULT_ERROR;

  1157. 		}

  1158. 	}

  1159. 	return SDHC_RESULT_OK;

  1160. }

  1161. 

  1162. // sends the command to SDcard

  1163. static int SDHC_CMD_Do(uint32_t xfertyp)

  1164. {

  1165.   // Card removal check preparation

  1166.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CRM;

  1167. 

  1168.   // Wait for cmd line idle // to do timeout PRSSTAT[CDIHB] and the PRSSTAT[CIHB]

  1169.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) { };

  1170.   SDHC_XFERTYP = xfertyp;

  1171. 

  1172.   /* Wait for response */

  1173.   const uint32_t mask = SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE | SDHC_IRQSTAT_CC;

  1174.   if (SDHC_WaitStatus(mask) != SDHC_IRQSTAT_CC) {

  1175.       //SDHC_IRQSTAT |= mask;

  1176.       SDHC_IRQSTAT |= (mask | SDHC_IRQSTAT_CTOE);

  1177.       return SDHC_RESULT_ERROR;

  1178.   }

  1179.   /* Check card removal */

  1180.   if (SDHC_IRQSTAT & SDHC_IRQSTAT_CRM) {

  1181.       SDHC_IRQSTAT |= SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;

  1182.       return SDHC_RESULT_NOT_READY;

  1183.   }

  1184. 

  1185.   /* Get response, if available */

  1186.   if (SDHC_IRQSTAT & SDHC_IRQSTAT_CTOE) {

  1187.       SDHC_IRQSTAT |= SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;

  1188.       return SDHC_RESULT_NO_RESPONSE;

  1189.   }

  1190.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CC;

  1191. 

  1192.   return SDHC_RESULT_OK;

  1193. }

  1194. 

  1195. // sends CMD0 to put SDCARD to idle

  1196. static int SDHC_CMD0_GoToIdle(void)

  1197. {

  1198.   uint32_t xfertyp;

  1199.   int result;

  1200. 

  1201.   SDHC_CMDARG = 0;

  1202. 

  1203.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD0) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_NO));

  1204. 

  1205.   result = SDHC_CMD_Do(xfertyp);

  1206. 

  1207.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1208.   return result;

  1209. }

  1210. 

  1211. // sends CMD2 to identify card

  1212. static int SDHC_CMD2_Identify(void)

  1213. {

  1214.   uint32_t xfertyp;

  1215.   int result;

  1216. 

  1217.   SDHC_CMDARG = 0;

  1218. 

  1219.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD2) | SDHC_XFERTYP_CCCEN

  1220.             | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_136));

  1221. 

  1222.   result = SDHC_CMD_Do(xfertyp);

  1223. 

  1224.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1225. 

  1226.   return result;

  1227. }

  1228. 

  1229. // sends CMD 3 to get address

  1230. static int SDHC_CMD3_GetAddress(void)

  1231. {

  1232.   uint32_t xfertyp;

  1233.   int result;

  1234. 

  1235.   SDHC_CMDARG = 0;

  1236. 

  1237.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD3) | SDHC_XFERTYP_CICEN |

  1238.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1239. 

  1240.   result = SDHC_CMD_Do(xfertyp);

  1241. 

  1242.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1243.   return result;

  1244. }

  1245. 

  1246. // sends ACMD6 to set bus width

  1247. static int SDHC_ACMD6_SetBusWidth(uint32_t address, uint32_t width)

  1248. {

  1249.   uint32_t xfertyp;

  1250.   int result;

  1251. 

  1252.   SDHC_CMDARG = address;

  1253.   // first send CMD 55 Application specific command

  1254.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD55) | SDHC_XFERTYP_CICEN |

  1255.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1256. 

  1257.   result = SDHC_CMD_Do(xfertyp);

  1258.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0;} else { return result; }

  1259.   SDHC_CMDARG = width;

  1260. 

  1261.   // Send CMD6

  1262.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD6) | SDHC_XFERTYP_CICEN |

  1263.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1264. 

  1265.   result = SDHC_CMD_Do(xfertyp);

  1266. 

  1267.   if (result == SDHC_RESULT_OK) {  (void)SDHC_CMDRSP0; }

  1268.   return result;

  1269. }

  1270. 

  1271. 

  1272. // sends CMD 7 to select card

  1273. static int SDHC_CMD7_SelectCard(uint32_t address)

  1274. {

  1275.   uint32_t xfertyp;

  1276.   int result;

  1277. 

  1278.   SDHC_CMDARG = address;

  1279. 

  1280.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD7) | SDHC_XFERTYP_CICEN |

  1281.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48BUSY));

  1282. 

  1283.   result = SDHC_CMD_Do(xfertyp);

  1284. 

  1285.   if (result == SDHC_RESULT_OK) {(void)SDHC_CMDRSP0; }

  1286.   return result;

  1287. }

  1288. 

  1289. // CMD8 to send interface condition

  1290. static int SDHC_CMD8_SetInterface(uint32_t cond)

  1291. {

  1292.   uint32_t xfertyp;

  1293.   int result;

  1294. 

  1295.   SDHC_CMDARG = cond;

  1296. 

  1297.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD8) | SDHC_XFERTYP_CICEN |

  1298.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1299. 

  1300.   result = SDHC_CMD_Do(xfertyp);

  1301. 

  1302.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1303.   return result;

  1304. }

  1305. 

  1306. // sends CMD 9 to get interface condition

  1307. static int SDHC_CMD9_GetParameters(uint32_t address)

  1308. {

  1309.   uint32_t xfertyp;

  1310.   int result;

  1311. 

  1312.   SDHC_CMDARG = address;

  1313. 

  1314.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD9) | SDHC_XFERTYP_CCCEN |

  1315.              SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_136));

  1316. 

  1317.   result = SDHC_CMD_Do(xfertyp);

  1318. 

  1319.   if (result == SDHC_RESULT_OK) {

  1320.     //(void)SDHC_CMDRSP0;

  1321.     sdCardDesc.tranSpeed = SDHC_CMDRSP2 >> 24;

  1322.   }

  1323. 

  1324.   return result;

  1325. }

  1326. 

  1327. // sends CMD12 to stop transfer

  1328. static int SDHC_CMD12_StopTransfer(void)

  1329. {

  1330.   uint32_t xfertyp;

  1331.   int result;

  1332. 

  1333.   SDHC_CMDARG = 0;

  1334.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD12) | SDHC_XFERTYP_CMDTYP(SDHC_XFERTYP_CMDTYP_ABORT) |

  1335.              SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48BUSY));

  1336. 

  1337.   result = SDHC_CMD_Do(xfertyp);

  1338. 

  1339.   if (result == SDHC_RESULT_OK) { }

  1340.   return result;

  1341. }

  1342. 

  1343. // sends CMD12 to stop transfer and first waits to ready SDCArd

  1344. static int SDHC_CMD12_StopTransferWaitForBusy(void)

  1345. {

  1346.   uint32_t timeOut = 1000;

  1347.   int result;

  1348.   do {

  1349.     result = SDHC_CMD12_StopTransfer();

  1350.     timeOut--;

  1351.   } while (timeOut && (SDHC_PRSSTAT & SDHC_PRSSTAT_DLA) && result == SDHC_RESULT_OK);

  1352. 

  1353.   if (result != SDHC_RESULT_OK)  return result;

  1354.   if (!timeOut)  return SDHC_RESULT_NO_RESPONSE;

  1355. 

  1356.   return SDHC_RESULT_OK;

  1357. }

  1358. 

  1359. // sends CMD16 to set block size

  1360. static int SDHC_CMD16_SetBlockSize(uint32_t block_size)

  1361. {

  1362.   uint32_t xfertyp;

  1363.   int result;

  1364. 

  1365.   SDHC_CMDARG = block_size;

  1366. 

  1367.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD16) | SDHC_XFERTYP_CICEN |

  1368.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1369. 

  1370.   result = SDHC_CMD_Do(xfertyp);

  1371. 

  1372.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1373. 

  1374.   return result;

  1375. }

  1376. 

  1377. // sends CMD17 to read one block

  1378. static int SDHC_CMD17_ReadBlock(uint32_t sector)

  1379. {

  1380.   uint32_t xfertyp;

  1381.   int result;

  1382. 

  1383.   SDHC_CMDARG = sector;

  1384. 

  1385.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | 512;

  1386. 

  1387.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD17) | SDHC_XFERTYP_CICEN |

  1388.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) |

  1389.              SDHC_XFERTYP_DTDSEL | SDHC_XFERTYP_DPSEL);

  1390. 

  1391.   result = SDHC_CMD_Do(xfertyp);

  1392.   if (result == SDHC_RESULT_OK) { ( void)SDHC_CMDRSP0; }

  1393. 

  1394.   return result;

  1395. }

  1396. 

  1397. // sends CMD24 to write one block

  1398. static int SDHC_CMD24_WriteBlock(uint32_t sector)

  1399. {

  1400.   uint32_t xfertyp;

  1401.   int result;

  1402. 

  1403.   SDHC_CMDARG = sector;

  1404.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | 512;

  1405. 

  1406.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD24) | SDHC_XFERTYP_CICEN |

  1407.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) |

  1408.              SDHC_XFERTYP_DPSEL);

  1409. 

  1410.   result = SDHC_CMD_Do(xfertyp);

  1411.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1412. 

  1413.   return result;

  1414. }

  1415. 

  1416. // ACMD 41 to send operation condition

  1417. static int SDHC_ACMD41_SendOperationCond(uint32_t cond)

  1418. {

  1419.   uint32_t xfertyp;

  1420.   int result;

  1421. 

  1422.   SDHC_CMDARG = 0;

  1423.   // first send CMD 55 Application specific command

  1424.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD55) | SDHC_XFERTYP_CICEN |

  1425.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1426. 

  1427.   result = SDHC_CMD_Do(xfertyp);

  1428. 

  1429.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; } else { return result; }

  1430. 

  1431.   SDHC_CMDARG = cond;

  1432. 

  1433.   // Send 41CMD

  1434.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_ACMD41) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1435.   result = SDHC_CMD_Do(xfertyp);

  1436. 

  1437.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1438. 

  1439.   return result;

  1440. }

  1441. #endif // __MK64FX512__ or __MK66FX1M0__ or __IMXRT1052__