Freescale Semiconductor, Inc.
Freescale
Kinetis_K
MK64F12
1.6
MK64F12 Freescale Microcontroller
Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
CM4
r0p1
little
true
false
true
4
false
8
32
FTFE_FlashConfig
Flash configuration field
NV_
0x400
0
0x10
registers
BACKKEY3
Backdoor Comparison Key 3.
0
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
0xFF
0xFF
KEY
Backdoor Comparison Key.
0
8
read-only
FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
0xFF
0xFF
PROT
P-Flash Region Protect
0
8
read-only
FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
0xFF
0xFF
PROT
P-Flash Region Protect
0
8
read-only
FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
0xFF
0xFF
PROT
P-Flash Region Protect
0
8
read-only
FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
0xFF
0xFF
PROT
P-Flash Region Protect
0
8
read-only
FSEC
Non-volatile Flash Security Register
0xC
8
read-only
0xFF
0xFF
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
MEEN
no description available
4
2
read-only
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
FOPT
Non-volatile Flash Option Register
0xD
8
read-only
0xFF
0xFF
LPBOOT
no description available
0
1
read-only
00
Low-power boot
#0
01
Normal boot
#1
EZPORT_DIS
no description available
1
1
read-only
00
EzPort operation is disabled
#0
01
EzPort operation is enabled
#1
FEPROT
Non-volatile EERAM Protection Register
0xE
8
read-only
0xFF
0xFF
EPROT
no description available
0
8
read-only
FDPROT
Non-volatile D-Flash Protection Register
0xF
8
read-only
0xFF
0xFF
DPROT
D-Flash Region Protect
0
8
read-only
AIPS0
AIPS-Lite Bridge
AIPS
AIPS0_
0x40000000
0
0x84
registers
MPRA
Master Privilege Register A
0
32
read-write
0x77700000
0xFFFFFFFF
MPL5
Master 5 Privilege Level
8
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW5
Master 5 Trusted For Writes
9
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR5
Master 5 Trusted For Read
10
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL4
Master 4 Privilege Level
12
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW4
Master 4 Trusted For Writes
13
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR4
Master 4 Trusted For Read
14
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL3
Master 3 Privilege Level
16
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW3
Master 3 Trusted For Writes
17
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR3
Master 3 Trusted For Read
18
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL2
Master 2 Privilege Level
20
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW2
Master 2 Trusted For Writes
21
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR2
Master 2 Trusted For Read
22
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL1
Master 1 Privilege Level
24
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW1
Master 1 Trusted for Writes
25
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR1
Master 1 Trusted for Read
26
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL0
Master 0 Privilege Level
28
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW0
Master 0 Trusted For Writes
29
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR0
Master 0 Trusted For Read
30
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
PACRA
Peripheral Access Control Register
0x20
32
read-write
0x50004000
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRB
Peripheral Access Control Register
0x24
32
read-write
0x44004400
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRC
Peripheral Access Control Register
0x28
32
read-write
0
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRD
Peripheral Access Control Register
0x2C
32
read-write
0x4
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRE
Peripheral Access Control Register
0x40
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRF
Peripheral Access Control Register
0x44
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRG
Peripheral Access Control Register
0x48
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRH
Peripheral Access Control Register
0x4C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRI
Peripheral Access Control Register
0x50
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRJ
Peripheral Access Control Register
0x54
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRK
Peripheral Access Control Register
0x58
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRL
Peripheral Access Control Register
0x5C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRM
Peripheral Access Control Register
0x60
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRN
Peripheral Access Control Register
0x64
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRO
Peripheral Access Control Register
0x68
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRP
Peripheral Access Control Register
0x6C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRU
Peripheral Access Control Register
0x80
32
read-write
0x44000000
0xFFFFFFFF
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
AIPS1
AIPS-Lite Bridge
AIPS
AIPS1_
0x40080000
0
0x84
registers
MPRA
Master Privilege Register A
0
32
read-write
0x77700000
0xFFFFFFFF
MPL5
Master 5 Privilege Level
8
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW5
Master 5 Trusted For Writes
9
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR5
Master 5 Trusted For Read
10
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL4
Master 4 Privilege Level
12
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW4
Master 4 Trusted For Writes
13
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR4
Master 4 Trusted For Read
14
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL3
Master 3 Privilege Level
16
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW3
Master 3 Trusted For Writes
17
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR3
Master 3 Trusted For Read
18
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL2
Master 2 Privilege Level
20
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW2
Master 2 Trusted For Writes
21
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR2
Master 2 Trusted For Read
22
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL1
Master 1 Privilege Level
24
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW1
Master 1 Trusted for Writes
25
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR1
Master 1 Trusted for Read
26
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
MPL0
Master 0 Privilege Level
28
1
read-write
0
Accesses from this master are forced to user-mode.
#0
1
Accesses from this master are not forced to user-mode.
#1
MTW0
Master 0 Trusted For Writes
29
1
read-write
0
This master is not trusted for write accesses.
#0
1
This master is trusted for write accesses.
#1
MTR0
Master 0 Trusted For Read
30
1
read-write
0
This master is not trusted for read accesses.
#0
1
This master is trusted for read accesses.
#1
PACRA
Peripheral Access Control Register
0x20
32
read-write
0x50000000
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRB
Peripheral Access Control Register
0x24
32
read-write
0
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRC
Peripheral Access Control Register
0x28
32
read-write
0
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRD
Peripheral Access Control Register
0x2C
32
read-write
0
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRE
Peripheral Access Control Register
0x40
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRF
Peripheral Access Control Register
0x44
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRG
Peripheral Access Control Register
0x48
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRH
Peripheral Access Control Register
0x4C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRI
Peripheral Access Control Register
0x50
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRJ
Peripheral Access Control Register
0x54
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRK
Peripheral Access Control Register
0x58
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRL
Peripheral Access Control Register
0x5C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRM
Peripheral Access Control Register
0x60
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRN
Peripheral Access Control Register
0x64
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRO
Peripheral Access Control Register
0x68
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRP
Peripheral Access Control Register
0x6C
32
read-write
0x44444444
0xFFFFFFFF
TP7
Trusted Protect
0
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP7
Write Protect
1
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP7
Supervisor Protect
2
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP6
Trusted Protect
4
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP6
Write Protect
5
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP6
Supervisor Protect
6
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP5
Trusted Protect
8
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP5
Write Protect
9
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP5
Supervisor Protect
10
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP4
Trusted Protect
12
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP4
Write Protect
13
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP4
Supervisor Protect
14
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP3
Trusted Protect
16
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP3
Write Protect
17
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP3
Supervisor Protect
18
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP2
Trusted Protect
20
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP2
Write Protect
21
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP2
Supervisor Protect
22
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
PACRU
Peripheral Access Control Register
0x80
32
read-write
0x44000000
0xFFFFFFFF
TP1
Trusted Protect
24
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP1
Write Protect
25
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP1
Supervisor Protect
26
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
TP0
Trusted Protect
28
1
read-write
0
Accesses from an untrusted master are allowed.
#0
1
Accesses from an untrusted master are not allowed.
#1
WP0
Write Protect
29
1
read-write
0
This peripheral allows write accesses.
#0
1
This peripheral is write protected.
#1
SP0
Supervisor Protect
30
1
read-write
0
This peripheral does not require supervisor privilege level for accesses.
#0
1
This peripheral requires supervisor privilege level for accesses.
#1
AXBS
Crossbar switch
AXBS_
0x40004000
0
0xD04
registers
5
0x100
0,1,2,3,4
PRS%s
Priority Registers Slave
0
32
read-write
0x543210
0xFFFFFFFF
M0
Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
0
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
M1
Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
4
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
M2
Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
8
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
M3
Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
12
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
M4
Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
16
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
M5
Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
20
3
read-write
000
This master has level 1, or highest, priority when accessing the slave port.
#000
001
This master has level 2 priority when accessing the slave port.
#001
010
This master has level 3 priority when accessing the slave port.
#010
011
This master has level 4 priority when accessing the slave port.
#011
100
This master has level 5 priority when accessing the slave port.
#100
101
This master has level 6 priority when accessing the slave port.
#101
110
This master has level 7 priority when accessing the slave port.
#110
111
This master has level 8, or lowest, priority when accessing the slave port.
#111
5
0x100
0,1,2,3,4
CRS%s
Control Register
0x10
32
read-write
0
0xFFFFFFFF
PARK
Park
0
3
read-write
000
Park on master port M0
#000
001
Park on master port M1
#001
010
Park on master port M2
#010
011
Park on master port M3
#011
100
Park on master port M4
#100
101
Park on master port M5
#101
110
Park on master port M6
#110
111
Park on master port M7
#111
PCTL
Parking Control
4
2
read-write
00
When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
#00
01
When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
#01
10
When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
#10
ARB
Arbitration Mode
8
2
read-write
00
Fixed priority
#00
01
Round-robin, or rotating, priority
#01
HLP
Halt Low Priority
30
1
read-write
0
The low power mode request has the highest priority for arbitration on this slave port
#0
1
The low power mode request has the lowest initial priority for arbitration on this slave port
#1
RO
Read Only
31
1
read-write
0
The slave port's registers are writeable
#0
1
The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
#1
6
0x100
0,1,2,3,4,5
MGPCR%s
Master General Purpose Control Register
0x800
32
read-write
0
0xFFFFFFFF
AULB
Arbitrates On Undefined Length Bursts
0
3
read-write
000
No arbitration is allowed during an undefined length burst
#000
001
Arbitration is allowed at any time during an undefined length burst
#001
010
Arbitration is allowed after four beats of an undefined length burst
#010
011
Arbitration is allowed after eight beats of an undefined length burst
#011
100
Arbitration is allowed after 16 beats of an undefined length burst
#100
DMA
Enhanced direct memory access controller
DMA_
0x40008000
0
0x1200
registers
DMA0
0
DMA1
1
DMA2
2
DMA3
3
DMA4
4
DMA5
5
DMA6
6
DMA7
7
DMA8
8
DMA9
9
DMA10
10
DMA11
11
DMA12
12
DMA13
13
DMA14
14
DMA15
15
DMA_Error
16
CR
Control Register
0
32
read-write
0
0xFFFFFFFF
EDBG
Enable Debug
1
1
read-write
0
When in debug mode, the DMA continues to operate.
#0
1
When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
#1
ERCA
Enable Round Robin Channel Arbitration
2
1
read-write
0
Fixed priority arbitration is used for channel selection .
#0
1
Round robin arbitration is used for channel selection .
#1
HOE
Halt On Error
4
1
read-write
0
Normal operation
#0
1
Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
#1
HALT
Halt DMA Operations
5
1
read-write
0
Normal operation
#0
1
Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
#1
CLM
Continuous Link Mode
6
1
read-write
0
A minor loop channel link made to itself goes through channel arbitration before being activated again.
#0
1
A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
#1
EMLM
Enable Minor Loop Mapping
7
1
read-write
0
Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
#0
1
Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
#1
ECX
Error Cancel Transfer
16
1
read-write
0
Normal operation
#0
1
Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
#1
CX
Cancel Transfer
17
1
read-write
0
Normal operation
#0
1
Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
#1
ES
Error Status Register
0x4
32
read-only
0
0xFFFFFFFF
DBE
Destination Bus Error
0
1
read-only
0
No destination bus error
#0
1
The last recorded error was a bus error on a destination write
#1
SBE
Source Bus Error
1
1
read-only
0
No source bus error
#0
1
The last recorded error was a bus error on a source read
#1
SGE
Scatter/Gather Configuration Error
2
1
read-only
0
No scatter/gather configuration error
#0
1
The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
#1
NCE
NBYTES/CITER Configuration Error
3
1
read-only
0
No NBYTES/CITER configuration error
#0
1
The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
#1
DOE
Destination Offset Error
4
1
read-only
0
No destination offset configuration error
#0
1
The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
#1
DAE
Destination Address Error
5
1
read-only
0
No destination address configuration error
#0
1
The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
#1
SOE
Source Offset Error
6
1
read-only
0
No source offset configuration error
#0
1
The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
#1
SAE
Source Address Error
7
1
read-only
0
No source address configuration error.
#0
1
The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
#1
ERRCHN
Error Channel Number or Canceled Channel Number
8
4
read-only
CPE
Channel Priority Error
14
1
read-only
0
No channel priority error
#0
1
The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
#1
ECX
Transfer Canceled
16
1
read-only
0
No canceled transfers
#0
1
The last recorded entry was a canceled transfer by the error cancel transfer input
#1
VLD
Logical OR of all ERR status bits
31
1
read-only
0
No ERR bits are set
#0
1
At least one ERR bit is set indicating a valid error exists that has not been cleared
#1
ERQ
Enable Request Register
0xC
32
read-write
0
0xFFFFFFFF
ERQ0
Enable DMA Request 0
0
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ1
Enable DMA Request 1
1
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ2
Enable DMA Request 2
2
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ3
Enable DMA Request 3
3
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ4
Enable DMA Request 4
4
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ5
Enable DMA Request 5
5
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ6
Enable DMA Request 6
6
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ7
Enable DMA Request 7
7
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ8
Enable DMA Request 8
8
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ9
Enable DMA Request 9
9
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ10
Enable DMA Request 10
10
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ11
Enable DMA Request 11
11
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ12
Enable DMA Request 12
12
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ13
Enable DMA Request 13
13
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ14
Enable DMA Request 14
14
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
ERQ15
Enable DMA Request 15
15
1
read-write
0
The DMA request signal for the corresponding channel is disabled
#0
1
The DMA request signal for the corresponding channel is enabled
#1
EEI
Enable Error Interrupt Register
0x14
32
read-write
0
0xFFFFFFFF
EEI0
Enable Error Interrupt 0
0
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI1
Enable Error Interrupt 1
1
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI2
Enable Error Interrupt 2
2
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI3
Enable Error Interrupt 3
3
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI4
Enable Error Interrupt 4
4
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI5
Enable Error Interrupt 5
5
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI6
Enable Error Interrupt 6
6
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI7
Enable Error Interrupt 7
7
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI8
Enable Error Interrupt 8
8
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI9
Enable Error Interrupt 9
9
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI10
Enable Error Interrupt 10
10
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI11
Enable Error Interrupt 11
11
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI12
Enable Error Interrupt 12
12
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI13
Enable Error Interrupt 13
13
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI14
Enable Error Interrupt 14
14
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
EEI15
Enable Error Interrupt 15
15
1
read-write
0
The error signal for corresponding channel does not generate an error interrupt
#0
1
The assertion of the error signal for corresponding channel generates an error interrupt request
#1
CEEI
Clear Enable Error Interrupt Register
0x18
8
write-only
0
0xFF
CEEI
Clear Enable Error Interrupt
0
4
write-only
CAEE
Clear All Enable Error Interrupts
6
1
write-only
0
Clear only the EEI bit specified in the CEEI field
#0
1
Clear all bits in EEI
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
SEEI
Set Enable Error Interrupt Register
0x19
8
write-only
0
0xFF
SEEI
Set Enable Error Interrupt
0
4
write-only
SAEE
Sets All Enable Error Interrupts
6
1
write-only
0
Set only the EEI bit specified in the SEEI field.
#0
1
Sets all bits in EEI
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
CERQ
Clear Enable Request Register
0x1A
8
write-only
0
0xFF
CERQ
Clear Enable Request
0
4
write-only
CAER
Clear All Enable Requests
6
1
write-only
0
Clear only the ERQ bit specified in the CERQ field
#0
1
Clear all bits in ERQ
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
SERQ
Set Enable Request Register
0x1B
8
write-only
0
0xFF
SERQ
Set enable request
0
4
write-only
SAER
Set All Enable Requests
6
1
write-only
0
Set only the ERQ bit specified in the SERQ field
#0
1
Set all bits in ERQ
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
CDNE
Clear DONE Status Bit Register
0x1C
8
write-only
0
0xFF
CDNE
Clear DONE Bit
0
4
write-only
CADN
Clears All DONE Bits
6
1
write-only
0
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
#0
1
Clears all bits in TCDn_CSR[DONE]
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
SSRT
Set START Bit Register
0x1D
8
write-only
0
0xFF
SSRT
Set START Bit
0
4
write-only
SAST
Set All START Bits (activates all channels)
6
1
write-only
0
Set only the TCDn_CSR[START] bit specified in the SSRT field
#0
1
Set all bits in TCDn_CSR[START]
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
CERR
Clear Error Register
0x1E
8
write-only
0
0xFF
CERR
Clear Error Indicator
0
4
write-only
CAEI
Clear All Error Indicators
6
1
write-only
0
Clear only the ERR bit specified in the CERR field
#0
1
Clear all bits in ERR
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
CINT
Clear Interrupt Request Register
0x1F
8
write-only
0
0xFF
CINT
Clear Interrupt Request
0
4
write-only
CAIR
Clear All Interrupt Requests
6
1
write-only
0
Clear only the INT bit specified in the CINT field
#0
1
Clear all bits in INT
#1
NOP
No Op enable
7
1
write-only
0
Normal operation
#0
1
No operation, ignore the other bits in this register
#1
INT
Interrupt Request Register
0x24
32
read-write
0
0xFFFFFFFF
INT0
Interrupt Request 0
0
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT1
Interrupt Request 1
1
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT2
Interrupt Request 2
2
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT3
Interrupt Request 3
3
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT4
Interrupt Request 4
4
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT5
Interrupt Request 5
5
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT6
Interrupt Request 6
6
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT7
Interrupt Request 7
7
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT8
Interrupt Request 8
8
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT9
Interrupt Request 9
9
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT10
Interrupt Request 10
10
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT11
Interrupt Request 11
11
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT12
Interrupt Request 12
12
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT13
Interrupt Request 13
13
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT14
Interrupt Request 14
14
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
INT15
Interrupt Request 15
15
1
read-write
0
The interrupt request for corresponding channel is cleared
#0
1
The interrupt request for corresponding channel is active
#1
ERR
Error Register
0x2C
32
read-write
0
0xFFFFFFFF
ERR0
Error In Channel 0
0
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR1
Error In Channel 1
1
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR2
Error In Channel 2
2
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR3
Error In Channel 3
3
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR4
Error In Channel 4
4
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR5
Error In Channel 5
5
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR6
Error In Channel 6
6
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR7
Error In Channel 7
7
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR8
Error In Channel 8
8
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR9
Error In Channel 9
9
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR10
Error In Channel 10
10
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR11
Error In Channel 11
11
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR12
Error In Channel 12
12
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR13
Error In Channel 13
13
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR14
Error In Channel 14
14
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
ERR15
Error In Channel 15
15
1
read-write
0
An error in the corresponding channel has not occurred
#0
1
An error in the corresponding channel has occurred
#1
HRS
Hardware Request Status Register
0x34
32
read-only
0
0xFFFFFFFF
HRS0
Hardware Request Status Channel 0
0
1
read-only
0
A hardware service request for channel 0 is not present
#0
1
A hardware service request for channel 0 is present
#1
HRS1
Hardware Request Status Channel 1
1
1
read-only
0
A hardware service request for channel 1 is not present
#0
1
A hardware service request for channel 1 is present
#1
HRS2
Hardware Request Status Channel 2
2
1
read-only
0
A hardware service request for channel 2 is not present
#0
1
A hardware service request for channel 2 is present
#1
HRS3
Hardware Request Status Channel 3
3
1
read-only
0
A hardware service request for channel 3 is not present
#0
1
A hardware service request for channel 3 is present
#1
HRS4
Hardware Request Status Channel 4
4
1
read-only
0
A hardware service request for channel 4 is not present
#0
1
A hardware service request for channel 4 is present
#1
HRS5
Hardware Request Status Channel 5
5
1
read-only
0
A hardware service request for channel 5 is not present
#0
1
A hardware service request for channel 5 is present
#1
HRS6
Hardware Request Status Channel 6
6
1
read-only
0
A hardware service request for channel 6 is not present
#0
1
A hardware service request for channel 6 is present
#1
HRS7
Hardware Request Status Channel 7
7
1
read-only
0
A hardware service request for channel 7 is not present
#0
1
A hardware service request for channel 7 is present
#1
HRS8
Hardware Request Status Channel 8
8
1
read-only
0
A hardware service request for channel 8 is not present
#0
1
A hardware service request for channel 8 is present
#1
HRS9
Hardware Request Status Channel 9
9
1
read-only
0
A hardware service request for channel 9 is not present
#0
1
A hardware service request for channel 9 is present
#1
HRS10
Hardware Request Status Channel 10
10
1
read-only
0
A hardware service request for channel 10 is not present
#0
1
A hardware service request for channel 10 is present
#1
HRS11
Hardware Request Status Channel 11
11
1
read-only
0
A hardware service request for channel 11 is not present
#0
1
A hardware service request for channel 11 is present
#1
HRS12
Hardware Request Status Channel 12
12
1
read-only
0
A hardware service request for channel 12 is not present
#0
1
A hardware service request for channel 12 is present
#1
HRS13
Hardware Request Status Channel 13
13
1
read-only
0
A hardware service request for channel 13 is not present
#0
1
A hardware service request for channel 13 is present
#1
HRS14
Hardware Request Status Channel 14
14
1
read-only
0
A hardware service request for channel 14 is not present
#0
1
A hardware service request for channel 14 is present
#1
HRS15
Hardware Request Status Channel 15
15
1
read-only
0
A hardware service request for channel 15 is not present
#0
1
A hardware service request for channel 15 is present
#1
16
0x1
3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12
DCHPRI%s
Channel n Priority Register
0x100
8
read-write
0
0xFF
CHPRI
Channel n Arbitration Priority
0
4
read-write
DPA
Disable Preempt Ability
6
1
read-write
0
Channel n can suspend a lower priority channel
#0
1
Channel n cannot suspend any channel, regardless of channel priority
#1
ECP
Enable Channel Preemption
7
1
read-write
0
Channel n cannot be suspended by a higher priority channel's service request
#0
1
Channel n can be temporarily suspended by the service request of a higher priority channel
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_SADDR
TCD Source Address
0x1000
32
read-write
0
0
SADDR
Source Address
0
32
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_SOFF
TCD Signed Source Address Offset
0x1004
16
read-write
0
0
SOFF
Source address signed offset
0
16
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_ATTR
TCD Transfer Attributes
0x1006
16
read-write
0
0
DSIZE
Destination Data Transfer Size
0
3
read-write
DMOD
Destination Address Modulo
3
5
read-write
SSIZE
Source data transfer size
8
3
read-write
000
8-bit
#000
001
16-bit
#001
010
32-bit
#010
100
16-byte
#100
101
32-byte
#101
SMOD
Source Address Modulo.
11
5
read-write
0
Source address modulo feature is disabled
#00000
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_NBYTES_MLNO
TCD Minor Byte Count (Minor Loop Disabled)
DMA
0x1008
32
read-write
0
0
NBYTES
Minor Byte Transfer Count
0
32
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_NBYTES_MLOFFNO
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
DMA
0x1008
32
read-write
0
0
NBYTES
Minor Byte Transfer Count
0
30
read-write
DMLOE
Destination Minor Loop Offset enable
30
1
read-write
0
The minor loop offset is not applied to the DADDR
#0
1
The minor loop offset is applied to the DADDR
#1
SMLOE
Source Minor Loop Offset Enable
31
1
read-write
0
The minor loop offset is not applied to the SADDR
#0
1
The minor loop offset is applied to the SADDR
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_NBYTES_MLOFFYES
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
DMA
0x1008
32
read-write
0
0
NBYTES
Minor Byte Transfer Count
0
10
read-write
MLOFF
If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
10
20
read-write
DMLOE
Destination Minor Loop Offset enable
30
1
read-write
0
The minor loop offset is not applied to the DADDR
#0
1
The minor loop offset is applied to the DADDR
#1
SMLOE
Source Minor Loop Offset Enable
31
1
read-write
0
The minor loop offset is not applied to the SADDR
#0
1
The minor loop offset is applied to the SADDR
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_SLAST
TCD Last Source Address Adjustment
0x100C
32
read-write
0
0
SLAST
Last source Address Adjustment
0
32
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_DADDR
TCD Destination Address
0x1010
32
read-write
0
0
DADDR
Destination Address
0
32
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_DOFF
TCD Signed Destination Address Offset
0x1014
16
read-write
0
0
DOFF
Destination Address Signed offset
0
16
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_CITER_ELINKNO
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
DMA
0x1016
16
read-write
0
0
CITER
Current Major Iteration Count
0
15
read-write
ELINK
Enable channel-to-channel linking on minor-loop complete
15
1
read-write
0
The channel-to-channel linking is disabled
#0
1
The channel-to-channel linking is enabled
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_CITER_ELINKYES
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
DMA
0x1016
16
read-write
0
0
CITER
Current Major Iteration Count
0
9
read-write
LINKCH
Link Channel Number
9
4
read-write
ELINK
Enable channel-to-channel linking on minor-loop complete
15
1
read-write
0
The channel-to-channel linking is disabled
#0
1
The channel-to-channel linking is enabled
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_DLASTSGA
TCD Last Destination Address Adjustment/Scatter Gather Address
0x1018
32
read-write
0
0
DLASTSGA
Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
0
32
read-write
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_CSR
TCD Control and Status
0x101C
16
read-write
0
0xC1
START
Channel Start
0
1
read-write
0
The channel is not explicitly started
#0
1
The channel is explicitly started via a software initiated service request
#1
INTMAJOR
Enable an interrupt when major iteration count completes
1
1
read-write
0
The end-of-major loop interrupt is disabled
#0
1
The end-of-major loop interrupt is enabled
#1
INTHALF
Enable an interrupt when major counter is half complete.
2
1
read-write
0
The half-point interrupt is disabled
#0
1
The half-point interrupt is enabled
#1
DREQ
Disable Request
3
1
read-write
0
The channel's ERQ bit is not affected
#0
1
The channel's ERQ bit is cleared when the major loop is complete
#1
ESG
Enable Scatter/Gather Processing
4
1
read-write
0
The current channel's TCD is normal format.
#0
1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
#1
MAJORELINK
Enable channel-to-channel linking on major loop complete
5
1
read-write
0
The channel-to-channel linking is disabled
#0
1
The channel-to-channel linking is enabled
#1
ACTIVE
Channel Active
6
1
read-write
DONE
Channel Done
7
1
read-write
MAJORLINKCH
Link Channel Number
8
4
read-write
BWC
Bandwidth Control
14
2
read-write
00
No eDMA engine stalls
#00
10
eDMA engine stalls for 4 cycles after each r/w
#10
11
eDMA engine stalls for 8 cycles after each r/w
#11
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_BITER_ELINKNO
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
DMA
0x101E
16
read-write
0
0
BITER
Starting Major Iteration Count
0
15
read-write
ELINK
Enables channel-to-channel linking on minor loop complete
15
1
read-write
0
The channel-to-channel linking is disabled
#0
1
The channel-to-channel linking is enabled
#1
16
0x20
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
TCD%s_BITER_ELINKYES
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
DMA
0x101E
16
read-write
0
0
BITER
Starting Major Iteration Count
0
9
read-write
LINKCH
Link Channel Number
9
4
read-write
ELINK
Enables channel-to-channel linking on minor loop complete
15
1
read-write
0
The channel-to-channel linking is disabled
#0
1
The channel-to-channel linking is enabled
#1
FB
FlexBus external bus interface
FB_
0x4000C000
0
0x64
registers
6
0xC
0,1,2,3,4,5
CSAR%s
Chip Select Address Register
0
32
read-write
0
0xFFFFFFFF
BA
Base Address
16
16
read-write
6
0xC
0,1,2,3,4,5
CSMR%s
Chip Select Mask Register
0x4
32
read-write
0
0xFFFFFFFF
V
Valid
0
1
read-write
0
Chip-select is invalid.
#0
1
Chip-select is valid.
#1
WP
Write Protect
8
1
read-write
0
Write accesses are allowed.
#0
1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
#1
BAM
Base Address Mask
16
16
read-write
0
The corresponding address bit in CSAR is used in the chip-select decode.
#0
1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
#1
6
0xC
0,1,2,3,4,5
CSCR%s
Chip Select Control Register
0x8
32
read-write
0x3FFC00
0xFFFFFFFF
BSTW
Burst-Write Enable
3
1
read-write
0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#0
1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
#1
BSTR
Burst-Read Enable
4
1
read-write
0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#0
1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
#1
BEM
Byte-Enable Mode
5
1
read-write
0
FB_BE is asserted for data write only.
#0
1
FB_BE is asserted for data read and write accesses.
#1
PS
Port Size
6
2
read-write
00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#00
01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#01
1X
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
#1x
AA
Auto-Acknowledge Enable
8
1
read-write
0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#0
1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
#1
BLS
Byte-Lane Shift
9
1
read-write
0
Not shifted. Data is left-aligned on FB_AD.
#0
1
Shifted. Data is right-aligned on FB_AD.
#1
WS
Wait States
10
6
read-write
WRAH
Write Address Hold or Deselect
16
2
read-write
00
1 cycle (default for all but FB_CS0 )
#00
01
2 cycles
#01
10
3 cycles
#10
11
4 cycles (default for FB_CS0 )
#11
RDAH
Read Address Hold or Deselect
18
2
read-write
00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#00
01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#01
10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#10
11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
#11
ASET
Address Setup
20
2
read-write
00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#00
01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#01
10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#10
11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
#11
EXTS
Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted.
22
1
read-write
0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#0
1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
#1
SWSEN
Secondary Wait State Enable
23
1
read-write
0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#0
1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
#1
SWS
Secondary Wait States
26
6
read-write
CSPMCR
Chip Select port Multiplexing Control Register
0x60
32
read-write
0
0xFFFFFFFF
GROUP5
FlexBus Signal Group 5 Multiplex control
12
4
read-write
0000
FB_TA
#0000
0001
FB_CS3 . You must also write 1b to CSCR[AA].
#0001
0010
FB_BE_7_0 . You must also write 1b to CSCR[AA].
#0010
GROUP4
FlexBus Signal Group 4 Multiplex control
16
4
read-write
0000
FB_TBST
#0000
0001
FB_CS2
#0001
0010
FB_BE_15_8
#0010
GROUP3
FlexBus Signal Group 3 Multiplex control
20
4
read-write
0000
FB_CS5
#0000
0001
FB_TSIZ1
#0001
0010
FB_BE_23_16
#0010
GROUP2
FlexBus Signal Group 2 Multiplex control
24
4
read-write
0000
FB_CS4
#0000
0001
FB_TSIZ0
#0001
0010
FB_BE_31_24
#0010
GROUP1
FlexBus Signal Group 1 Multiplex control
28
4
read-write
0000
FB_ALE
#0000
0001
FB_CS1
#0001
0010
FB_TS
#0010
MPU
Memory protection unit
MPU_
0x4000D000
0
0x830
registers
CESR
Control/Error Status Register
0
32
read-write
0x815101
0xFFFFFFFF
VLD
Valid
0
1
read-write
0
MPU is disabled. All accesses from all bus masters are allowed.
#0
1
MPU is enabled
#1
NRGD
Number Of Region Descriptors
8
4
read-only
0000
8 region descriptors
#0000
0001
12 region descriptors
#0001
0010
16 region descriptors
#0010
NSP
Number Of Slave Ports
12
4
read-only
HRL
Hardware Revision Level
16
4
read-only
SPERR
Slave Port n Error
27
5
read-write
0
No error has occurred for slave port n.
#00000
1
An error has occurred for slave port n.
#00001
5
0x8
0,1,2,3,4
EAR%s
Error Address Register, slave port n
0x10
32
read-only
0
0xFFFFFFFF
EADDR
Error Address
0
32
read-only
5
0x8
0,1,2,3,4
EDR%s
Error Detail Register, slave port n
0x14
32
read-only
0
0xFFFFFFFF
ERW
Error Read/Write
0
1
read-only
0
Read
#0
1
Write
#1
EATTR
Error Attributes
1
3
read-only
000
User mode, instruction access
#000
001
User mode, data access
#001
010
Supervisor mode, instruction access
#010
011
Supervisor mode, data access
#011
EMN
Error Master Number
4
4
read-only
EPID
Error Process Identification
8
8
read-only
EACD
Error Access Control Detail
16
16
read-only
12
0x10
0,1,2,3,4,5,6,7,8,9,10,11
RGD%s_WORD0
Region Descriptor n, Word 0
0x400
32
read-write
0
0xFFFFFFFF
SRTADDR
Start Address
5
27
read-write
12
0x10
0,1,2,3,4,5,6,7,8,9,10,11
RGD%s_WORD1
Region Descriptor n, Word 1
0x404
32
read-write
0xFFFFFFFF
0xFFFFFFFF
ENDADDR
End Address
5
27
read-write
12
0x10
0,1,2,3,4,5,6,7,8,9,10,11
RGD%s_WORD2
Region Descriptor n, Word 2
0x408
32
read-write
0x61F7DF
0xFFFFFFFF
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#000
1
Allows the given access type to occur
#001
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
12
0x10
0,1,2,3,4,5,6,7,8,9,10,11
RGD%s_WORD3
Region Descriptor n, Word 3
0x40C
32
read-write
0x1
0xFFFFFFFF
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
PIDMASK
Process Identifier Mask
16
8
read-write
PID
Process Identifier
24
8
read-write
12
0x4
0,1,2,3,4,5,6,7,8,9,10,11
RGDAAC%s
Region Descriptor Alternate Access Control n
0x800
32
read-write
0x61F7DF
0xFFFFFFFF
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#000
1
Allows the given access type to occur
#001
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
FMC
Flash Memory Controller
FMC_
0x4001F000
0
0x280
registers
PFAPR
Flash Access Protection Register
0
32
read-write
0xF8003F
0xFFFFFFFF
M0AP
Master 0 Access Protection
0
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M1AP
Master 1 Access Protection
2
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M2AP
Master 2 Access Protection
4
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M3AP
Master 3 Access Protection
6
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M4AP
Master 4 Access Protection
8
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M5AP
Master 5 Access Protection
10
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M6AP
Master 6 Access Protection
12
2
read-write
00
No access may be performed by this master
#00
01
Only read accesses may be performed by this master
#01
10
Only write accesses may be performed by this master
#10
11
Both read and write accesses may be performed by this master
#11
M7AP
Master 7 Access Protection
14
2
read-write
00
No access may be performed by this master.
#00
01
Only read accesses may be performed by this master.
#01
10
Only write accesses may be performed by this master.
#10
11
Both read and write accesses may be performed by this master.
#11
M0PFD
Master 0 Prefetch Disable
16
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M1PFD
Master 1 Prefetch Disable
17
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M2PFD
Master 2 Prefetch Disable
18
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M3PFD
Master 3 Prefetch Disable
19
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M4PFD
Master 4 Prefetch Disable
20
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M5PFD
Master 5 Prefetch Disable
21
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M6PFD
Master 6 Prefetch Disable
22
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
M7PFD
Master 7 Prefetch Disable
23
1
read-write
0
Prefetching for this master is enabled.
#0
1
Prefetching for this master is disabled.
#1
PFB0CR
Flash Bank 0 Control Register
0x4
32
read-write
0x3004001F
0xFFFFFFFF
B0SEBE
Bank 0 Single Entry Buffer Enable
0
1
read-write
0
Single entry buffer is disabled.
#0
1
Single entry buffer is enabled.
#1
B0IPE
Bank 0 Instruction Prefetch Enable
1
1
read-write
0
Do not prefetch in response to instruction fetches.
#0
1
Enable prefetches in response to instruction fetches.
#1
B0DPE
Bank 0 Data Prefetch Enable
2
1
read-write
0
Do not prefetch in response to data references.
#0
1
Enable prefetches in response to data references.
#1
B0ICE
Bank 0 Instruction Cache Enable
3
1
read-write
0
Do not cache instruction fetches.
#0
1
Cache instruction fetches.
#1
B0DCE
Bank 0 Data Cache Enable
4
1
read-write
0
Do not cache data references.
#0
1
Cache data references.
#1
CRC
Cache Replacement Control
5
3
read-write
000
LRU replacement algorithm per set across all four ways
#000
010
Independent LRU with ways [0-1] for ifetches, [2-3] for data
#010
011
Independent LRU with ways [0-2] for ifetches, [3] for data
#011
B0MW
Bank 0 Memory Width
17
2
read-only
00
32 bits
#00
01
64 bits
#01
10
128 bits
#10
S_B_INV
Invalidate Prefetch Speculation Buffer
19
1
write-only
0
Speculation buffer and single entry buffer are not affected.
#0
1
Invalidate (clear) speculation buffer and single entry buffer.
#1
CINV_WAY
Cache Invalidate Way x
20
4
write-only
0
No cache way invalidation for the corresponding cache
#0000
1
Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
#0001
CLCK_WAY
Cache Lock Way x
24
4
read-write
0
Cache way is unlocked and may be displaced
#0000
1
Cache way is locked and its contents are not displaced
#0001
B0RWSC
Bank 0 Read Wait State Control
28
4
read-only
PFB1CR
Flash Bank 1 Control Register
0x8
32
read-write
0x3004001F
0xFFFFFFFF
B1SEBE
Bank 1 Single Entry Buffer Enable
0
1
read-write
0
Single entry buffer is disabled.
#0
1
Single entry buffer is enabled.
#1
B1IPE
Bank 1 Instruction Prefetch Enable
1
1
read-write
0
Do not prefetch in response to instruction fetches.
#0
1
Enable prefetches in response to instruction fetches.
#1
B1DPE
Bank 1 Data Prefetch Enable
2
1
read-write
0
Do not prefetch in response to data references.
#0
1
Enable prefetches in response to data references.
#1
B1ICE
Bank 1 Instruction Cache Enable
3
1
read-write
0
Do not cache instruction fetches.
#0
1
Cache instruction fetches.
#1
B1DCE
Bank 1 Data Cache Enable
4
1
read-write
0
Do not cache data references.
#0
1
Cache data references.
#1
B1MW
Bank 1 Memory Width
17
2
read-only
00
32 bits
#00
01
64 bits
#01
10
128 bits
#10
B1RWSC
Bank 1 Read Wait State Control
28
4
read-only
4
0x4
0,1,2,3
TAGVDW0S%s
Cache Tag Storage
0x100
32
read-write
0
0xFFFFFFFF
valid
1-bit valid for cache entry
0
1
read-write
tag
14-bit tag for cache entry
5
14
read-write
4
0x4
0,1,2,3
TAGVDW1S%s
Cache Tag Storage
0x110
32
read-write
0
0xFFFFFFFF
valid
1-bit valid for cache entry
0
1
read-write
tag
14-bit tag for cache entry
5
14
read-write
4
0x4
0,1,2,3
TAGVDW2S%s
Cache Tag Storage
0x120
32
read-write
0
0xFFFFFFFF
valid
1-bit valid for cache entry
0
1
read-write
tag
14-bit tag for cache entry
5
14
read-write
4
0x4
0,1,2,3
TAGVDW3S%s
Cache Tag Storage
0x130
32
read-write
0
0xFFFFFFFF
valid
1-bit valid for cache entry
0
1
read-write
tag
14-bit tag for cache entry
5
14
read-write
4
0x8
0,1,2,3
DATAW0S%sU
Cache Data Storage (upper word)
0x200
32
read-write
0
0xFFFFFFFF
data
Bits [63:32] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW0S%sL
Cache Data Storage (lower word)
0x204
32
read-write
0
0xFFFFFFFF
data
Bits [31:0] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW1S%sU
Cache Data Storage (upper word)
0x220
32
read-write
0
0xFFFFFFFF
data
Bits [63:32] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW1S%sL
Cache Data Storage (lower word)
0x224
32
read-write
0
0xFFFFFFFF
data
Bits [31:0] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW2S%sU
Cache Data Storage (upper word)
0x240
32
read-write
0
0xFFFFFFFF
data
Bits [63:32] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW2S%sL
Cache Data Storage (lower word)
0x244
32
read-write
0
0xFFFFFFFF
data
Bits [31:0] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW3S%sU
Cache Data Storage (upper word)
0x260
32
read-write
0
0xFFFFFFFF
data
Bits [63:32] of data entry
0
32
read-write
4
0x8
0,1,2,3
DATAW3S%sL
Cache Data Storage (lower word)
0x264
32
read-write
0
0xFFFFFFFF
data
Bits [31:0] of data entry
0
32
read-write
FTFE
Flash Memory Interface
FTFE_
0x40020000
0
0x18
registers
FTFE
18
Read_Collision
19
FSTAT
Flash Status Register
0
8
read-write
0
0xFF
MGSTAT0
Memory Controller Command Completion Status Flag
0
1
read-only
FPVIOL
Flash Protection Violation Flag
4
1
read-write
0
No protection violation detected
#0
1
Protection violation detected
#1
ACCERR
Flash Access Error Flag
5
1
read-write
0
No access error detected
#0
1
Access error detected
#1
RDCOLERR
FTFE Read Collision Error Flag
6
1
read-write
0
No collision error detected
#0
1
Collision error detected
#1
CCIF
Command Complete Interrupt Flag
7
1
read-write
0
FTFE command or EEPROM file system operation in progress
#0
1
FTFE command or EEPROM file system operation has completed
#1
FCNFG
Flash Configuration Register
0x1
8
read-write
0
0xFF
EEERDY
For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access
0
1
read-only
0
For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
#0
1
For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup.
#1
RAMRDY
RAM Ready
1
1
read-only
0
For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available.
#0
1
For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available.
#1
PFLSH
FTFE configuration
2
1
read-only
0
For devices with FlexNVM: FTFE configuration supports two program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved
#0
1
For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks
#1
SWAP
Swap
3
1
read-only
0
For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0 block is located at relative address 0x0000
#0
1
For devices with FlexNVM: Reserved For devices with program flash only: Program flash 1 block is located at relative address 0x0000
#1
ERSSUSP
Erase Suspend
4
1
read-write
0
No suspend requested
#0
1
Suspend the current Erase Flash Sector command execution.
#1
ERSAREQ
Erase All Request
5
1
read-only
0
No request or request complete
#0
1
Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
#1
RDCOLLIE
Read Collision Error Interrupt Enable
6
1
read-write
0
Read collision error interrupt disabled
#0
1
Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).
#1
CCIE
Command Complete Interrupt Enable
7
1
read-write
0
Command complete interrupt disabled
#0
1
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
#1
FSEC
Flash Security Register
0x2
8
read-only
0
0
SEC
Flash Security
0
2
read-only
00
MCU security status is secure
#00
01
MCU security status is secure
#01
10
MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.)
#10
11
MCU security status is secure
#11
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
00
Freescale factory access granted
#00
01
Freescale factory access denied
#01
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
MEEN
Mass Erase Enable Bits
4
2
read-only
00
Mass erase is enabled
#00
01
Mass erase is enabled
#01
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
00
Backdoor key access disabled
#00
01
Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
#01
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
FOPT
Flash Option Register
0x3
8
read-only
0
0
OPT
Nonvolatile Option
0
8
read-only
12
0x1
3,2,1,0,7,6,5,4,B,A,9,8
FCCOB%s
Flash Common Command Object Registers
0x4
8
read-write
0
0xFF
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
4
0x1
3,2,1,0
FPROT%s
Program Flash Protection Registers
0x10
8
read-write
0
0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FEPROT
EEPROM Protection Register
0x16
8
read-write
0
0
EPROT
EEPROM Region Protect
0
8
read-write
0
For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected
#0
1
For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected
#1
FDPROT
Data Flash Protection Register
0x17
8
read-write
0
0
DPROT
Data Flash Region Protect
0
8
read-write
0
Data Flash region is protected
#0
1
Data Flash region is not protected
#1
DMAMUX
DMA channel multiplexor
DMAMUX_
0x40021000
0
0x10
registers
16
0x1
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
CHCFG%s
Channel Configuration register
0
8
read-write
0
0xFF
SOURCE
DMA Channel Source (Slot)
0
6
read-write
0
Disable_Signal
#0
2
UART0_Rx_Signal
#10
3
UART0_Tx_Signal
#11
4
UART1_Rx_Signal
#100
5
UART1_Tx_Signal
#101
6
UART2_Rx_Signal
#110
7
UART2_Tx_Signal
#111
8
UART3_Rx_Signal
#1000
9
UART3_Tx_Signal
#1001
10
UART4_Signal
#1010
11
UART5_Signal
#1011
12
I2S0_Rx_Signal
#1100
13
I2S0_Tx_Signal
#1101
14
SPI0_Rx_Signal
#1110
15
SPI0_Tx_Signal
#1111
16
SPI1_Signal
#10000
17
SPI2_Signal
#10001
18
I2C0_Signal
#10010
19
I2C1_I2C2_Signal
#10011
20
FTM0_Channel0_Signal
#10100
21
FTM0_Channel1_Signal
#10101
22
FTM0_Channel2_Signal
#10110
23
FTM0_Channel3_Signal
#10111
24
FTM0_Channel4_Signal
#11000
25
FTM0_Channel5_Signal
#11001
26
FTM0_Channel6_Signal
#11010
27
FTM0_Channel7_Signal
#11011
28
FTM1_Channel0_Signal
#11100
29
FTM1_Channel1_Signal
#11101
30
FTM2_Channel0_Signal
#11110
31
FTM2_Channel1_Signal
#11111
32
FTM3_Channel0_Signal
#100000
33
FTM3_Channel1_Signal
#100001
34
FTM3_Channel2_Signal
#100010
35
FTM3_Channel3_Signal
#100011
36
FTM3_Channel4_Signal
#100100
37
FTM3_Channel5_Signal
#100101
38
FTM3_Channel6_Signal
#100110
39
FTM3_Channel7_Signal
#100111
40
ADC0_Signal
#101000
41
ADC1_Signal
#101001
42
CMP0_Signal
#101010
43
CMP1_Signal
#101011
44
CMP2_Signal
#101100
45
DAC0_Signal
#101101
46
DAC1_Signal
#101110
47
CMT_Signal
#101111
48
PDB_Signal
#110000
49
PortA_Signal
#110001
50
PortB_Signal
#110010
51
PortC_Signal
#110011
52
PortD_Signal
#110100
53
PortE_Signal
#110101
54
IEEE1588Timer0_Signal
#110110
55
IEEE1588Timer1_Signal
#110111
56
IEEE1588Timer2_Signal
#111000
57
IEEE1588Timer3_Signal
#111001
58
AlwaysOn58_Signal
#111010
59
AlwaysOn59_Signal
#111011
60
AlwaysOn60_Signal
#111100
61
AlwaysOn61_Signal
#111101
62
AlwaysOn62_Signal
#111110
63
AlwaysOn63_Signal
#111111
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
CAN0
Flex Controller Area Network module
CAN0_
0x40024000
0
0x8C0
registers
CAN0_ORed_Message_buffer
75
CAN0_Bus_Off
76
CAN0_Error
77
CAN0_Tx_Warning
78
CAN0_Rx_Warning
79
CAN0_Wake_Up
80
MCR
Module Configuration Register
0
32
read-write
0xD890000F
0xFFFFFFFF
MAXMB
Number Of The Last Message Buffer
0
7
read-write
IDAM
ID Acceptance Mode
8
2
read-write
00
Format A: One full ID (standard and extended) per ID Filter Table element.
#00
01
Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
#01
10
Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
#10
11
Format D: All frames rejected.
#11
AEN
Abort Enable
12
1
read-write
0
Abort disabled.
#0
1
Abort enabled.
#1
LPRIOEN
Local Priority Enable
13
1
read-write
0
Local Priority disabled.
#0
1
Local Priority enabled.
#1
IRMQ
Individual Rx Masking And Queue Enable
16
1
read-write
0
Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
#0
1
Individual Rx masking and queue feature are enabled.
#1
SRXDIS
Self Reception Disable
17
1
read-write
0
Self reception enabled.
#0
1
Self reception disabled.
#1
WAKSRC
Wake Up Source
19
1
read-write
0
FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
#0
1
FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
#1
LPMACK
Low-Power Mode Acknowledge
20
1
read-only
0
FlexCAN is not in a low-power mode.
#0
1
FlexCAN is in a low-power mode.
#1
WRNEN
Warning Interrupt Enable
21
1
read-write
0
TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
#0
1
TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
#1
SLFWAK
Self Wake Up
22
1
read-write
0
FlexCAN Self Wake Up feature is disabled.
#0
1
FlexCAN Self Wake Up feature is enabled.
#1
SUPV
Supervisor Mode
23
1
read-write
0
FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses .
#0
1
FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .
#1
FRZACK
Freeze Mode Acknowledge
24
1
read-only
0
FlexCAN not in Freeze mode, prescaler running.
#0
1
FlexCAN in Freeze mode, prescaler stopped.
#1
SOFTRST
Soft Reset
25
1
read-write
0
No reset request.
#0
1
Resets the registers affected by soft reset.
#1
WAKMSK
Wake Up Interrupt Mask
26
1
read-write
0
Wake Up Interrupt is disabled.
#0
1
Wake Up Interrupt is enabled.
#1
NOTRDY
FlexCAN Not Ready
27
1
read-only
0
FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
#0
1
FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
#1
HALT
Halt FlexCAN
28
1
read-write
0
No Freeze mode request.
#0
1
Enters Freeze mode if the FRZ bit is asserted.
#1
RFEN
Rx FIFO Enable
29
1
read-write
0
Rx FIFO not enabled.
#0
1
Rx FIFO enabled.
#1
FRZ
Freeze Enable
30
1
read-write
0
Not enabled to enter Freeze mode.
#0
1
Enabled to enter Freeze mode.
#1
MDIS
Module Disable
31
1
read-write
0
Enable the FlexCAN module.
#0
1
Disable the FlexCAN module.
#1
CTRL1
Control 1 register
0x4
32
read-write
0
0xFFFFFFFF
PROPSEG
Propagation Segment
0
3
read-write
LOM
Listen-Only Mode
3
1
read-write
0
Listen-Only mode is deactivated.
#0
1
FlexCAN module operates in Listen-Only mode.
#1
LBUF
Lowest Buffer Transmitted First
4
1
read-write
0
Buffer with highest priority is transmitted first.
#0
1
Lowest number buffer is transmitted first.
#1
TSYN
Timer Sync
5
1
read-write
0
Timer Sync feature disabled
#0
1
Timer Sync feature enabled
#1
BOFFREC
Bus Off Recovery
6
1
read-write
0
Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B.
#0
1
Automatic recovering from Bus Off state disabled.
#1
SMP
CAN Bit Sampling
7
1
read-write
0
Just one sample is used to determine the bit value.
#0
1
Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
#1
RWRNMSK
Rx Warning Interrupt Mask
10
1
read-write
0
Rx Warning Interrupt disabled.
#0
1
Rx Warning Interrupt enabled.
#1
TWRNMSK
Tx Warning Interrupt Mask
11
1
read-write
0
Tx Warning Interrupt disabled.
#0
1
Tx Warning Interrupt enabled.
#1
LPB
Loop Back Mode
12
1
read-write
0
Loop Back disabled.
#0
1
Loop Back enabled.
#1
CLKSRC
CAN Engine Clock Source
13
1
read-write
0
The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
#0
1
The CAN engine clock source is the peripheral clock.
#1
ERRMSK
Error Mask
14
1
read-write
0
Error interrupt disabled.
#0
1
Error interrupt enabled.
#1
BOFFMSK
Bus Off Mask
15
1
read-write
0
Bus Off interrupt disabled.
#0
1
Bus Off interrupt enabled.
#1
PSEG2
Phase Segment 2
16
3
read-write
PSEG1
Phase Segment 1
19
3
read-write
RJW
Resync Jump Width
22
2
read-write
PRESDIV
Prescaler Division Factor
24
8
read-write
TIMER
Free Running Timer
0x8
32
read-write
0
0xFFFFFFFF
TIMER
Timer Value
0
16
read-write
RXMGMASK
Rx Mailboxes Global Mask Register
0x10
32
read-write
0xFFFFFFFF
0xFFFFFFFF
MG
Rx Mailboxes Global Mask Bits
0
32
read-write
0
The corresponding bit in the filter is "don't care."
#0
1
The corresponding bit in the filter is checked.
#1
RX14MASK
Rx 14 Mask register
0x14
32
read-write
0xFFFFFFFF
0xFFFFFFFF
RX14M
Rx Buffer 14 Mask Bits
0
32
read-write
0
The corresponding bit in the filter is "don't care."
#0
1
The corresponding bit in the filter is checked.
#1
RX15MASK
Rx 15 Mask register
0x18
32
read-write
0xFFFFFFFF
0xFFFFFFFF
RX15M
Rx Buffer 15 Mask Bits
0
32
read-write
0
The corresponding bit in the filter is "don't care."
#0
1
The corresponding bit in the filter is checked.
#1
ECR
Error Counter
0x1C
32
read-write
0
0xFFFFFFFF
TXERRCNT
Transmit Error Counter
0
8
read-write
RXERRCNT
Receive Error Counter
8
8
read-write
ESR1
Error and Status 1 register
0x20
32
read-write
0
0xFFFFFFFF
WAKINT
Wake-Up Interrupt
0
1
read-write
0
No such occurrence.
#0
1
Indicates a recessive to dominant transition was received on the CAN bus.
#1
ERRINT
Error Interrupt
1
1
read-write
0
No such occurrence.
#0
1
Indicates setting of any Error Bit in the Error and Status Register.
#1
BOFFINT
Bus Off Interrupt
2
1
read-write
0
No such occurrence.
#0
1
FlexCAN module entered Bus Off state.
#1
RX
FlexCAN In Reception
3
1
read-only
0
FlexCAN is not receiving a message.
#0
1
FlexCAN is receiving a message.
#1
FLTCONF
Fault Confinement State
4
2
read-only
00
Error Active
#00
01
Error Passive
#01
1x
Bus Off
#1x
TX
FlexCAN In Transmission
6
1
read-only
0
FlexCAN is not transmitting a message.
#0
1
FlexCAN is transmitting a message.
#1
IDLE
This bit indicates when CAN bus is in IDLE state
7
1
read-only
0
No such occurrence.
#0
1
CAN bus is now IDLE.
#1
RXWRN
Rx Error Warning
8
1
read-only
0
No such occurrence.
#0
1
RXERRCNT is greater than or equal to 96.
#1
TXWRN
TX Error Warning
9
1
read-only
0
No such occurrence.
#0
1
TXERRCNT is greater than or equal to 96.
#1
STFERR
Stuffing Error
10
1
read-only
0
No such occurrence.
#0
1
A Stuffing Error occurred since last read of this register.
#1
FRMERR
Form Error
11
1
read-only
0
No such occurrence.
#0
1
A Form Error occurred since last read of this register.
#1
CRCERR
Cyclic Redundancy Check Error
12
1
read-only
0
No such occurrence.
#0
1
A CRC error occurred since last read of this register.
#1
ACKERR
Acknowledge Error
13
1
read-only
0
No such occurrence.
#0
1
An ACK error occurred since last read of this register.
#1
BIT0ERR
Bit0 Error
14
1
read-only
0
No such occurrence.
#0
1
At least one bit sent as dominant is received as recessive.
#1
BIT1ERR
Bit1 Error
15
1
read-only
0
No such occurrence.
#0
1
At least one bit sent as recessive is received as dominant.
#1
RWRNINT
Rx Warning Interrupt Flag
16
1
read-write
0
No such occurrence.
#0
1
The Rx error counter transitioned from less than 96 to greater than or equal to 96.
#1
TWRNINT
Tx Warning Interrupt Flag
17
1
read-write
0
No such occurrence.
#0
1
The Tx error counter transitioned from less than 96 to greater than or equal to 96.
#1
SYNCH
CAN Synchronization Status
18
1
read-only
0
FlexCAN is not synchronized to the CAN bus.
#0
1
FlexCAN is synchronized to the CAN bus.
#1
IMASK1
Interrupt Masks 1 register
0x28
32
read-write
0
0xFFFFFFFF
BUFLM
Buffer MB i Mask
0
32
read-write
0
The corresponding buffer Interrupt is disabled.
#0
1
The corresponding buffer Interrupt is enabled.
#1
IFLAG1
Interrupt Flags 1 register
0x30
32
read-write
0
0xFFFFFFFF
BUF0I
Buffer MB0 Interrupt Or "reserved"
0
1
read-write
0
The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
#0
1
The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
#1
BUF4TO1I
Buffer MB i Interrupt Or "reserved"
1
4
read-write
0
The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
#0000
1
The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
#0001
BUF5I
Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
5
1
read-write
0
No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
#0
1
MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1
#1
BUF6I
Buffer MB6 Interrupt Or "Rx FIFO Warning"
6
1
read-write
0
No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
#0
1
MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
#1
BUF7I
Buffer MB7 Interrupt Or "Rx FIFO Overflow"
7
1
read-write
0
No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
#0
1
MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
#1
BUF31TO8I
Buffer MBi Interrupt
8
24
read-write
0
The corresponding buffer has no occurrence of successfully completed transmission or reception.
#0
1
The corresponding buffer has successfully completed transmission or reception.
#1
CTRL2
Control 2 register
0x34
32
read-write
0xB00000
0xFFFFFFFF
EACEN
Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
16
1
read-write
0
Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
#0
1
Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
#1
RRS
Remote Request Storing
17
1
read-write
0
Remote Response Frame is generated.
#0
1
Remote Request Frame is stored.
#1
MRP
Mailboxes Reception Priority
18
1
read-write
0
Matching starts from Rx FIFO and continues on Mailboxes.
#0
1
Matching starts from Mailboxes and continues on Rx FIFO.
#1
TASD
Tx Arbitration Start Delay
19
5
read-write
RFFN
Number Of Rx FIFO Filters
24
4
read-write
WRMFRZ
Write-Access To Memory In Freeze Mode
28
1
read-write
0
Maintain the write access restrictions.
#0
1
Enable unrestricted write access to FlexCAN memory.
#1
ESR2
Error and Status 2 register
0x38
32
read-only
0
0xFFFFFFFF
IMB
Inactive Mailbox
13
1
read-only
0
If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
#0
1
If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
#1
VPS
Valid Priority Status
14
1
read-only
0
Contents of IMB and LPTM are invalid.
#0
1
Contents of IMB and LPTM are valid.
#1
LPTM
Lowest Priority Tx Mailbox
16
7
read-only
CRCR
CRC Register
0x44
32
read-only
0
0xFFFFFFFF
TXCRC
CRC Transmitted
0
15
read-only
MBCRC
CRC Mailbox
16
7
read-only
RXFGMASK
Rx FIFO Global Mask register
0x48
32
read-write
0xFFFFFFFF
0xFFFFFFFF
FGM
Rx FIFO Global Mask Bits
0
32
read-write
0
The corresponding bit in the filter is "don't care."
#0
1
The corresponding bit in the filter is checked.
#1
RXFIR
Rx FIFO Information Register
0x4C
32
read-only
0
0
IDHIT
Identifier Acceptance Filter Hit Indicator
0
9
read-only
CS0
Message Buffer 0 CS Register
0x80
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID0
Message Buffer 0 ID Register
0x84
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD00
Message Buffer 0 WORD0 Register
0x88
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD10
Message Buffer 0 WORD1 Register
0x8C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS1
Message Buffer 1 CS Register
0x90
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID1
Message Buffer 1 ID Register
0x94
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD01
Message Buffer 1 WORD0 Register
0x98
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD11
Message Buffer 1 WORD1 Register
0x9C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS2
Message Buffer 2 CS Register
0xA0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID2
Message Buffer 2 ID Register
0xA4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD02
Message Buffer 2 WORD0 Register
0xA8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD12
Message Buffer 2 WORD1 Register
0xAC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS3
Message Buffer 3 CS Register
0xB0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID3
Message Buffer 3 ID Register
0xB4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD03
Message Buffer 3 WORD0 Register
0xB8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD13
Message Buffer 3 WORD1 Register
0xBC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS4
Message Buffer 4 CS Register
0xC0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID4
Message Buffer 4 ID Register
0xC4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD04
Message Buffer 4 WORD0 Register
0xC8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD14
Message Buffer 4 WORD1 Register
0xCC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS5
Message Buffer 5 CS Register
0xD0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID5
Message Buffer 5 ID Register
0xD4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD05
Message Buffer 5 WORD0 Register
0xD8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD15
Message Buffer 5 WORD1 Register
0xDC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS6
Message Buffer 6 CS Register
0xE0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID6
Message Buffer 6 ID Register
0xE4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD06
Message Buffer 6 WORD0 Register
0xE8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD16
Message Buffer 6 WORD1 Register
0xEC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS7
Message Buffer 7 CS Register
0xF0
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID7
Message Buffer 7 ID Register
0xF4
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD07
Message Buffer 7 WORD0 Register
0xF8
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD17
Message Buffer 7 WORD1 Register
0xFC
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS8
Message Buffer 8 CS Register
0x100
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID8
Message Buffer 8 ID Register
0x104
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD08
Message Buffer 8 WORD0 Register
0x108
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD18
Message Buffer 8 WORD1 Register
0x10C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS9
Message Buffer 9 CS Register
0x110
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID9
Message Buffer 9 ID Register
0x114
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD09
Message Buffer 9 WORD0 Register
0x118
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD19
Message Buffer 9 WORD1 Register
0x11C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS10
Message Buffer 10 CS Register
0x120
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID10
Message Buffer 10 ID Register
0x124
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD010
Message Buffer 10 WORD0 Register
0x128
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD110
Message Buffer 10 WORD1 Register
0x12C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS11
Message Buffer 11 CS Register
0x130
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID11
Message Buffer 11 ID Register
0x134
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD011
Message Buffer 11 WORD0 Register
0x138
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD111
Message Buffer 11 WORD1 Register
0x13C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS12
Message Buffer 12 CS Register
0x140
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID12
Message Buffer 12 ID Register
0x144
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD012
Message Buffer 12 WORD0 Register
0x148
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD112
Message Buffer 12 WORD1 Register
0x14C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS13
Message Buffer 13 CS Register
0x150
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID13
Message Buffer 13 ID Register
0x154
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD013
Message Buffer 13 WORD0 Register
0x158
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD113
Message Buffer 13 WORD1 Register
0x15C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS14
Message Buffer 14 CS Register
0x160
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID14
Message Buffer 14 ID Register
0x164
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD014
Message Buffer 14 WORD0 Register
0x168
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD114
Message Buffer 14 WORD1 Register
0x16C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
CS15
Message Buffer 15 CS Register
0x170
32
read-write
0
0xFFFFFFFF
TIME_STAMP
Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
0
16
read-write
DLC
Length of the data to be stored/transmitted.
16
4
read-write
RTR
Remote Transmission Request. One/zero for remote/data frame.
20
1
read-write
IDE
ID Extended. One/zero for extended/standard format frame.
21
1
read-write
SRR
Substitute Remote Request. Contains a fixed recessive bit.
22
1
read-write
CODE
Reserved
24
4
read-write
ID15
Message Buffer 15 ID Register
0x174
32
read-write
0
0xFFFFFFFF
EXT
Contains extended (LOW word) identifier of message buffer.
0
18
read-write
STD
Contains standard/extended (HIGH word) identifier of message buffer.
18
11
read-write
PRIO
Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
29
3
read-write
WORD015
Message Buffer 15 WORD0 Register
0x178
32
read-write
0
0xFFFFFFFF
DATA_BYTE_3
Data byte 3 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_2
Data byte 2 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_1
Data byte 1 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_0
Data byte 0 of Rx/Tx frame.
24
8
read-write
WORD115
Message Buffer 15 WORD1 Register
0x17C
32
read-write
0
0xFFFFFFFF
DATA_BYTE_7
Data byte 7 of Rx/Tx frame.
0
8
read-write
DATA_BYTE_6
Data byte 6 of Rx/Tx frame.
8
8
read-write
DATA_BYTE_5
Data byte 5 of Rx/Tx frame.
16
8
read-write
DATA_BYTE_4
Data byte 4 of Rx/Tx frame.
24
8
read-write
16
0x4
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
RXIMR%s
Rx Individual Mask Registers
0x880
32
read-write
0
0
MI
Individual Mask Bits
0
32
read-write
0
The corresponding bit in the filter is "don't care."
#0
1
The corresponding bit in the filter is checked.
#1
RNG
Random Number Generator Accelerator
RNG_
0x40029000
0
0x10
registers
RNG
23
CR
RNGA Control Register
0
32
read-write
0
0xFFFFFFFF
GO
Go
0
1
read-write
0
Disabled
#0
1
Enabled
#1
HA
High Assurance
1
1
read-write
0
Disabled
#0
1
Enabled
#1
INTM
Interrupt Mask
2
1
read-write
0
Not masked
#0
1
Masked
#1
CLRI
Clear Interrupt
3
1
write-only
0
Do not clear the interrupt.
#0
1
Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
#1
SLP
Sleep
4
1
read-write
0
Normal mode
#0
1
Sleep (low-power) mode
#1
SR
RNGA Status Register
0x4
32
read-only
0x10000
0xFFFFFFFF
SECV
Security Violation
0
1
read-only
0
No security violation
#0
1
Security violation
#1
LRS
Last Read Status
1
1
read-only
0
No underflow
#0
1
Underflow
#1
ORU
Output Register Underflow
2
1
read-only
0
No underflow
#0
1
Underflow
#1
ERRI
Error Interrupt
3
1
read-only
0
No underflow
#0
1
Underflow
#1
SLP
Sleep
4
1
read-only
0
Normal mode
#0
1
Sleep (low-power) mode
#1
OREG_LVL
Output Register Level
8
8
read-only
0
No words (empty)
#0
1
One word (valid)
#1
OREG_SIZE
Output Register Size
16
8
read-only
1
One word (this value is fixed)
#1
ER
RNGA Entropy Register
0x8
32
write-only
0
0xFFFFFFFF
EXT_ENT
External Entropy
0
32
write-only
OR
RNGA Output Register
0xC
32
read-only
0
0xFFFFFFFF
RANDOUT
Random Output
0
32
read-only
0
Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
#0
SPI0
Serial Peripheral Interface
SPI
SPI0_
0x4002C000
0
0x8C
registers
SPI0
26
MCR
Module Configuration Register
0
32
read-write
0x4001
0xFFFFFFFF
HALT
Halt
0
1
read-write
0
Start transfers.
#0
1
Stop transfers.
#1
SMPL_PT
Sample Point
8
2
read-write
00
0 protocol clock cycles between SCK edge and SIN sample
#00
01
1 protocol clock cycle between SCK edge and SIN sample
#01
10
2 protocol clock cycles between SCK edge and SIN sample
#10
CLR_RXF
Flushes the RX FIFO
10
1
write-only
0
Do not clear the RX FIFO counter.
#0
1
Clear the RX FIFO counter.
#1
CLR_TXF
Clear TX FIFO
11
1
write-only
0
Do not clear the TX FIFO counter.
#0
1
Clear the TX FIFO counter.
#1
DIS_RXF
Disable Receive FIFO
12
1
read-write
0
RX FIFO is enabled.
#0
1
RX FIFO is disabled.
#1
DIS_TXF
Disable Transmit FIFO
13
1
read-write
0
TX FIFO is enabled.
#0
1
TX FIFO is disabled.
#1
MDIS
Module Disable
14
1
read-write
0
Enables the module clocks.
#0
1
Allows external logic to disable the module clocks.
#1
DOZE
Doze Enable
15
1
read-write
0
Doze mode has no effect on the module.
#0
1
Doze mode disables the module.
#1
PCSIS
Peripheral Chip Select x Inactive State
16
6
read-write
0
The inactive state of PCSx is low.
#0
1
The inactive state of PCSx is high.
#1
ROOE
Receive FIFO Overflow Overwrite Enable
24
1
read-write
0
Incoming data is ignored.
#0
1
Incoming data is shifted into the shift register.
#1
PCSSE
Peripheral Chip Select Strobe Enable
25
1
read-write
0
PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
#0
1
PCS5/ PCSS is used as an active-low PCS Strobe signal.
#1
MTFE
Modified Timing Format Enable
26
1
read-write
0
Modified SPI transfer format disabled.
#0
1
Modified SPI transfer format enabled.
#1
FRZ
Freeze
27
1
read-write
0
Do not halt serial transfers in Debug mode.
#0
1
Halt serial transfers in Debug mode.
#1
DCONF
SPI Configuration.
28
2
read-only
00
SPI
#00
CONT_SCKE
Continuous SCK Enable
30
1
read-write
0
Continuous SCK disabled.
#0
1
Continuous SCK enabled.
#1
MSTR
Master/Slave Mode Select
31
1
read-write
0
Enables Slave mode
#0
1
Enables Master mode
#1
TCR
Transfer Count Register
0x8
32
read-write
0
0xFFFFFFFF
SPI_TCNT
SPI Transfer Counter
16
16
read-write
2
0x4
0,1
CTAR%s
Clock and Transfer Attributes Register (In Master Mode)
SPI0
0xC
32
read-write
0x78000000
0xFFFFFFFF
BR
Baud Rate Scaler
0
4
read-write
DT
Delay After Transfer Scaler
4
4
read-write
ASC
After SCK Delay Scaler
8
4
read-write
CSSCK
PCS to SCK Delay Scaler
12
4
read-write
PBR
Baud Rate Prescaler
16
2
read-write
00
Baud Rate Prescaler value is 2.
#00
01
Baud Rate Prescaler value is 3.
#01
10
Baud Rate Prescaler value is 5.
#10
11
Baud Rate Prescaler value is 7.
#11
PDT
Delay after Transfer Prescaler
18
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PASC
After SCK Delay Prescaler
20
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PCSSCK
PCS to SCK Delay Prescaler
22
2
read-write
00
PCS to SCK Prescaler value is 1.
#00
01
PCS to SCK Prescaler value is 3.
#01
10
PCS to SCK Prescaler value is 5.
#10
11
PCS to SCK Prescaler value is 7.
#11
LSBFE
LSB First
24
1
read-write
0
Data is transferred MSB first.
#0
1
Data is transferred LSB first.
#1
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
4
read-write
DBR
Double Baud Rate
31
1
read-write
0
The baud rate is computed normally with a 50/50 duty cycle.
#0
1
The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
#1
CTAR_SLAVE
Clock and Transfer Attributes Register (In Slave Mode)
SPI0
0xC
32
read-write
0x78000000
0xFFFFFFFF
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
5
read-write
SR
Status Register
0x2C
32
read-write
0x2000000
0xFFFFFFFF
POPNXTPTR
Pop Next Pointer
0
4
read-only
RXCTR
RX FIFO Counter
4
4
read-only
TXNXTPTR
Transmit Next Pointer
8
4
read-only
TXCTR
TX FIFO Counter
12
4
read-only
RFDF
Receive FIFO Drain Flag
17
1
read-write
0
RX FIFO is empty.
#0
1
RX FIFO is not empty.
#1
RFOF
Receive FIFO Overflow Flag
19
1
read-write
0
No Rx FIFO overflow.
#0
1
Rx FIFO overflow has occurred.
#1
TFFF
Transmit FIFO Fill Flag
25
1
read-write
0
TX FIFO is full.
#0
1
TX FIFO is not full.
#1
TFUF
Transmit FIFO Underflow Flag
27
1
read-write
0
No TX FIFO underflow.
#0
1
TX FIFO underflow has occurred.
#1
EOQF
End of Queue Flag
28
1
read-write
0
EOQ is not set in the executing command.
#0
1
EOQ is set in the executing SPI command.
#1
TXRXS
TX and RX Status
30
1
read-write
0
Transmit and receive operations are disabled (The module is in Stopped state).
#0
1
Transmit and receive operations are enabled (The module is in Running state).
#1
TCF
Transfer Complete Flag
31
1
read-write
0
Transfer not complete.
#0
1
Transfer complete.
#1
RSER
DMA/Interrupt Request Select and Enable Register
0x30
32
read-write
0
0xFFFFFFFF
RFDF_DIRS
Receive FIFO Drain DMA or Interrupt Request Select
16
1
read-write
0
Interrupt request.
#0
1
DMA request.
#1
RFDF_RE
Receive FIFO Drain Request Enable
17
1
read-write
0
RFDF interrupt or DMA requests are disabled.
#0
1
RFDF interrupt or DMA requests are enabled.
#1
RFOF_RE
Receive FIFO Overflow Request Enable
19
1
read-write
0
RFOF interrupt requests are disabled.
#0
1
RFOF interrupt requests are enabled.
#1
TFFF_DIRS
Transmit FIFO Fill DMA or Interrupt Request Select
24
1
read-write
0
TFFF flag generates interrupt requests.
#0
1
TFFF flag generates DMA requests.
#1
TFFF_RE
Transmit FIFO Fill Request Enable
25
1
read-write
0
TFFF interrupts or DMA requests are disabled.
#0
1
TFFF interrupts or DMA requests are enabled.
#1
TFUF_RE
Transmit FIFO Underflow Request Enable
27
1
read-write
0
TFUF interrupt requests are disabled.
#0
1
TFUF interrupt requests are enabled.
#1
EOQF_RE
Finished Request Enable
28
1
read-write
0
EOQF interrupt requests are disabled.
#0
1
EOQF interrupt requests are enabled.
#1
TCF_RE
Transmission Complete Request Enable
31
1
read-write
0
TCF interrupt requests are disabled.
#0
1
TCF interrupt requests are enabled.
#1
PUSHR
PUSH TX FIFO Register In Master Mode
SPI0
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-write
PCS
Select which PCS signals are to be asserted for the transfer
16
6
read-write
0
Negate the PCS[x] signal.
#0
1
Assert the PCS[x] signal.
#1
CTCNT
Clear Transfer Counter
26
1
read-write
0
Do not clear the TCR[TCNT] field.
#0
1
Clear the TCR[TCNT] field.
#1
EOQ
End Of Queue
27
1
read-write
0
The SPI data is not the last data to transfer.
#0
1
The SPI data is the last data to transfer.
#1
CTAS
Clock and Transfer Attributes Select
28
3
read-write
000
CTAR0
#000
001
CTAR1
#001
CONT
Continuous Peripheral Chip Select Enable
31
1
read-write
0
Return PCSn signals to their inactive state between transfers.
#0
1
Keep PCSn signals asserted between transfers.
#1
PUSHR_SLAVE
PUSH TX FIFO Register In Slave Mode
SPI0
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
32
read-write
POPR
POP RX FIFO Register
0x38
32
read-only
0
0xFFFFFFFF
RXDATA
Received Data
0
32
read-only
4
0x4
0,1,2,3
TXFR%s
Transmit FIFO Registers
0x3C
32
read-only
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-only
TXCMD_TXDATA
Transmit Command or Transmit Data
16
16
read-only
4
0x4
0,1,2,3
RXFR%s
Receive FIFO Registers
0x7C
32
read-only
0
0xFFFFFFFF
RXDATA
Receive Data
0
32
read-only
SPI1
Serial Peripheral Interface
SPI
SPI1_
0x4002D000
0
0x8C
registers
SPI1
27
MCR
Module Configuration Register
0
32
read-write
0x4001
0xFFFFFFFF
HALT
Halt
0
1
read-write
0
Start transfers.
#0
1
Stop transfers.
#1
SMPL_PT
Sample Point
8
2
read-write
00
0 protocol clock cycles between SCK edge and SIN sample
#00
01
1 protocol clock cycle between SCK edge and SIN sample
#01
10
2 protocol clock cycles between SCK edge and SIN sample
#10
CLR_RXF
Flushes the RX FIFO
10
1
write-only
0
Do not clear the RX FIFO counter.
#0
1
Clear the RX FIFO counter.
#1
CLR_TXF
Clear TX FIFO
11
1
write-only
0
Do not clear the TX FIFO counter.
#0
1
Clear the TX FIFO counter.
#1
DIS_RXF
Disable Receive FIFO
12
1
read-write
0
RX FIFO is enabled.
#0
1
RX FIFO is disabled.
#1
DIS_TXF
Disable Transmit FIFO
13
1
read-write
0
TX FIFO is enabled.
#0
1
TX FIFO is disabled.
#1
MDIS
Module Disable
14
1
read-write
0
Enables the module clocks.
#0
1
Allows external logic to disable the module clocks.
#1
DOZE
Doze Enable
15
1
read-write
0
Doze mode has no effect on the module.
#0
1
Doze mode disables the module.
#1
PCSIS
Peripheral Chip Select x Inactive State
16
6
read-write
0
The inactive state of PCSx is low.
#0
1
The inactive state of PCSx is high.
#1
ROOE
Receive FIFO Overflow Overwrite Enable
24
1
read-write
0
Incoming data is ignored.
#0
1
Incoming data is shifted into the shift register.
#1
PCSSE
Peripheral Chip Select Strobe Enable
25
1
read-write
0
PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
#0
1
PCS5/ PCSS is used as an active-low PCS Strobe signal.
#1
MTFE
Modified Timing Format Enable
26
1
read-write
0
Modified SPI transfer format disabled.
#0
1
Modified SPI transfer format enabled.
#1
FRZ
Freeze
27
1
read-write
0
Do not halt serial transfers in Debug mode.
#0
1
Halt serial transfers in Debug mode.
#1
DCONF
SPI Configuration.
28
2
read-only
00
SPI
#00
CONT_SCKE
Continuous SCK Enable
30
1
read-write
0
Continuous SCK disabled.
#0
1
Continuous SCK enabled.
#1
MSTR
Master/Slave Mode Select
31
1
read-write
0
Enables Slave mode
#0
1
Enables Master mode
#1
TCR
Transfer Count Register
0x8
32
read-write
0
0xFFFFFFFF
SPI_TCNT
SPI Transfer Counter
16
16
read-write
2
0x4
0,1
CTAR%s
Clock and Transfer Attributes Register (In Master Mode)
SPI1
0xC
32
read-write
0x78000000
0xFFFFFFFF
BR
Baud Rate Scaler
0
4
read-write
DT
Delay After Transfer Scaler
4
4
read-write
ASC
After SCK Delay Scaler
8
4
read-write
CSSCK
PCS to SCK Delay Scaler
12
4
read-write
PBR
Baud Rate Prescaler
16
2
read-write
00
Baud Rate Prescaler value is 2.
#00
01
Baud Rate Prescaler value is 3.
#01
10
Baud Rate Prescaler value is 5.
#10
11
Baud Rate Prescaler value is 7.
#11
PDT
Delay after Transfer Prescaler
18
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PASC
After SCK Delay Prescaler
20
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PCSSCK
PCS to SCK Delay Prescaler
22
2
read-write
00
PCS to SCK Prescaler value is 1.
#00
01
PCS to SCK Prescaler value is 3.
#01
10
PCS to SCK Prescaler value is 5.
#10
11
PCS to SCK Prescaler value is 7.
#11
LSBFE
LSB First
24
1
read-write
0
Data is transferred MSB first.
#0
1
Data is transferred LSB first.
#1
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
4
read-write
DBR
Double Baud Rate
31
1
read-write
0
The baud rate is computed normally with a 50/50 duty cycle.
#0
1
The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
#1
CTAR_SLAVE
Clock and Transfer Attributes Register (In Slave Mode)
SPI1
0xC
32
read-write
0x78000000
0xFFFFFFFF
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
5
read-write
SR
Status Register
0x2C
32
read-write
0x2000000
0xFFFFFFFF
POPNXTPTR
Pop Next Pointer
0
4
read-only
RXCTR
RX FIFO Counter
4
4
read-only
TXNXTPTR
Transmit Next Pointer
8
4
read-only
TXCTR
TX FIFO Counter
12
4
read-only
RFDF
Receive FIFO Drain Flag
17
1
read-write
0
RX FIFO is empty.
#0
1
RX FIFO is not empty.
#1
RFOF
Receive FIFO Overflow Flag
19
1
read-write
0
No Rx FIFO overflow.
#0
1
Rx FIFO overflow has occurred.
#1
TFFF
Transmit FIFO Fill Flag
25
1
read-write
0
TX FIFO is full.
#0
1
TX FIFO is not full.
#1
TFUF
Transmit FIFO Underflow Flag
27
1
read-write
0
No TX FIFO underflow.
#0
1
TX FIFO underflow has occurred.
#1
EOQF
End of Queue Flag
28
1
read-write
0
EOQ is not set in the executing command.
#0
1
EOQ is set in the executing SPI command.
#1
TXRXS
TX and RX Status
30
1
read-write
0
Transmit and receive operations are disabled (The module is in Stopped state).
#0
1
Transmit and receive operations are enabled (The module is in Running state).
#1
TCF
Transfer Complete Flag
31
1
read-write
0
Transfer not complete.
#0
1
Transfer complete.
#1
RSER
DMA/Interrupt Request Select and Enable Register
0x30
32
read-write
0
0xFFFFFFFF
RFDF_DIRS
Receive FIFO Drain DMA or Interrupt Request Select
16
1
read-write
0
Interrupt request.
#0
1
DMA request.
#1
RFDF_RE
Receive FIFO Drain Request Enable
17
1
read-write
0
RFDF interrupt or DMA requests are disabled.
#0
1
RFDF interrupt or DMA requests are enabled.
#1
RFOF_RE
Receive FIFO Overflow Request Enable
19
1
read-write
0
RFOF interrupt requests are disabled.
#0
1
RFOF interrupt requests are enabled.
#1
TFFF_DIRS
Transmit FIFO Fill DMA or Interrupt Request Select
24
1
read-write
0
TFFF flag generates interrupt requests.
#0
1
TFFF flag generates DMA requests.
#1
TFFF_RE
Transmit FIFO Fill Request Enable
25
1
read-write
0
TFFF interrupts or DMA requests are disabled.
#0
1
TFFF interrupts or DMA requests are enabled.
#1
TFUF_RE
Transmit FIFO Underflow Request Enable
27
1
read-write
0
TFUF interrupt requests are disabled.
#0
1
TFUF interrupt requests are enabled.
#1
EOQF_RE
Finished Request Enable
28
1
read-write
0
EOQF interrupt requests are disabled.
#0
1
EOQF interrupt requests are enabled.
#1
TCF_RE
Transmission Complete Request Enable
31
1
read-write
0
TCF interrupt requests are disabled.
#0
1
TCF interrupt requests are enabled.
#1
PUSHR
PUSH TX FIFO Register In Master Mode
SPI1
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-write
PCS
Select which PCS signals are to be asserted for the transfer
16
6
read-write
0
Negate the PCS[x] signal.
#0
1
Assert the PCS[x] signal.
#1
CTCNT
Clear Transfer Counter
26
1
read-write
0
Do not clear the TCR[TCNT] field.
#0
1
Clear the TCR[TCNT] field.
#1
EOQ
End Of Queue
27
1
read-write
0
The SPI data is not the last data to transfer.
#0
1
The SPI data is the last data to transfer.
#1
CTAS
Clock and Transfer Attributes Select
28
3
read-write
000
CTAR0
#000
001
CTAR1
#001
CONT
Continuous Peripheral Chip Select Enable
31
1
read-write
0
Return PCSn signals to their inactive state between transfers.
#0
1
Keep PCSn signals asserted between transfers.
#1
PUSHR_SLAVE
PUSH TX FIFO Register In Slave Mode
SPI1
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
32
read-write
POPR
POP RX FIFO Register
0x38
32
read-only
0
0xFFFFFFFF
RXDATA
Received Data
0
32
read-only
4
0x4
0,1,2,3
TXFR%s
Transmit FIFO Registers
0x3C
32
read-only
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-only
TXCMD_TXDATA
Transmit Command or Transmit Data
16
16
read-only
4
0x4
0,1,2,3
RXFR%s
Receive FIFO Registers
0x7C
32
read-only
0
0xFFFFFFFF
RXDATA
Receive Data
0
32
read-only
SPI2
Serial Peripheral Interface
SPI
SPI2_
0x400AC000
0
0x8C
registers
SPI2
65
MCR
Module Configuration Register
0
32
read-write
0x4001
0xFFFFFFFF
HALT
Halt
0
1
read-write
0
Start transfers.
#0
1
Stop transfers.
#1
SMPL_PT
Sample Point
8
2
read-write
00
0 protocol clock cycles between SCK edge and SIN sample
#00
01
1 protocol clock cycle between SCK edge and SIN sample
#01
10
2 protocol clock cycles between SCK edge and SIN sample
#10
CLR_RXF
Flushes the RX FIFO
10
1
write-only
0
Do not clear the RX FIFO counter.
#0
1
Clear the RX FIFO counter.
#1
CLR_TXF
Clear TX FIFO
11
1
write-only
0
Do not clear the TX FIFO counter.
#0
1
Clear the TX FIFO counter.
#1
DIS_RXF
Disable Receive FIFO
12
1
read-write
0
RX FIFO is enabled.
#0
1
RX FIFO is disabled.
#1
DIS_TXF
Disable Transmit FIFO
13
1
read-write
0
TX FIFO is enabled.
#0
1
TX FIFO is disabled.
#1
MDIS
Module Disable
14
1
read-write
0
Enables the module clocks.
#0
1
Allows external logic to disable the module clocks.
#1
DOZE
Doze Enable
15
1
read-write
0
Doze mode has no effect on the module.
#0
1
Doze mode disables the module.
#1
PCSIS
Peripheral Chip Select x Inactive State
16
6
read-write
0
The inactive state of PCSx is low.
#0
1
The inactive state of PCSx is high.
#1
ROOE
Receive FIFO Overflow Overwrite Enable
24
1
read-write
0
Incoming data is ignored.
#0
1
Incoming data is shifted into the shift register.
#1
PCSSE
Peripheral Chip Select Strobe Enable
25
1
read-write
0
PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
#0
1
PCS5/ PCSS is used as an active-low PCS Strobe signal.
#1
MTFE
Modified Timing Format Enable
26
1
read-write
0
Modified SPI transfer format disabled.
#0
1
Modified SPI transfer format enabled.
#1
FRZ
Freeze
27
1
read-write
0
Do not halt serial transfers in Debug mode.
#0
1
Halt serial transfers in Debug mode.
#1
DCONF
SPI Configuration.
28
2
read-only
00
SPI
#00
CONT_SCKE
Continuous SCK Enable
30
1
read-write
0
Continuous SCK disabled.
#0
1
Continuous SCK enabled.
#1
MSTR
Master/Slave Mode Select
31
1
read-write
0
Enables Slave mode
#0
1
Enables Master mode
#1
TCR
Transfer Count Register
0x8
32
read-write
0
0xFFFFFFFF
SPI_TCNT
SPI Transfer Counter
16
16
read-write
2
0x4
0,1
CTAR%s
Clock and Transfer Attributes Register (In Master Mode)
SPI2
0xC
32
read-write
0x78000000
0xFFFFFFFF
BR
Baud Rate Scaler
0
4
read-write
DT
Delay After Transfer Scaler
4
4
read-write
ASC
After SCK Delay Scaler
8
4
read-write
CSSCK
PCS to SCK Delay Scaler
12
4
read-write
PBR
Baud Rate Prescaler
16
2
read-write
00
Baud Rate Prescaler value is 2.
#00
01
Baud Rate Prescaler value is 3.
#01
10
Baud Rate Prescaler value is 5.
#10
11
Baud Rate Prescaler value is 7.
#11
PDT
Delay after Transfer Prescaler
18
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PASC
After SCK Delay Prescaler
20
2
read-write
00
Delay after Transfer Prescaler value is 1.
#00
01
Delay after Transfer Prescaler value is 3.
#01
10
Delay after Transfer Prescaler value is 5.
#10
11
Delay after Transfer Prescaler value is 7.
#11
PCSSCK
PCS to SCK Delay Prescaler
22
2
read-write
00
PCS to SCK Prescaler value is 1.
#00
01
PCS to SCK Prescaler value is 3.
#01
10
PCS to SCK Prescaler value is 5.
#10
11
PCS to SCK Prescaler value is 7.
#11
LSBFE
LSB First
24
1
read-write
0
Data is transferred MSB first.
#0
1
Data is transferred LSB first.
#1
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
4
read-write
DBR
Double Baud Rate
31
1
read-write
0
The baud rate is computed normally with a 50/50 duty cycle.
#0
1
The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
#1
CTAR_SLAVE
Clock and Transfer Attributes Register (In Slave Mode)
SPI2
0xC
32
read-write
0x78000000
0xFFFFFFFF
CPHA
Clock Phase
25
1
read-write
0
Data is captured on the leading edge of SCK and changed on the following edge.
#0
1
Data is changed on the leading edge of SCK and captured on the following edge.
#1
CPOL
Clock Polarity
26
1
read-write
0
The inactive state value of SCK is low.
#0
1
The inactive state value of SCK is high.
#1
FMSZ
Frame Size
27
5
read-write
SR
Status Register
0x2C
32
read-write
0x2000000
0xFFFFFFFF
POPNXTPTR
Pop Next Pointer
0
4
read-only
RXCTR
RX FIFO Counter
4
4
read-only
TXNXTPTR
Transmit Next Pointer
8
4
read-only
TXCTR
TX FIFO Counter
12
4
read-only
RFDF
Receive FIFO Drain Flag
17
1
read-write
0
RX FIFO is empty.
#0
1
RX FIFO is not empty.
#1
RFOF
Receive FIFO Overflow Flag
19
1
read-write
0
No Rx FIFO overflow.
#0
1
Rx FIFO overflow has occurred.
#1
TFFF
Transmit FIFO Fill Flag
25
1
read-write
0
TX FIFO is full.
#0
1
TX FIFO is not full.
#1
TFUF
Transmit FIFO Underflow Flag
27
1
read-write
0
No TX FIFO underflow.
#0
1
TX FIFO underflow has occurred.
#1
EOQF
End of Queue Flag
28
1
read-write
0
EOQ is not set in the executing command.
#0
1
EOQ is set in the executing SPI command.
#1
TXRXS
TX and RX Status
30
1
read-write
0
Transmit and receive operations are disabled (The module is in Stopped state).
#0
1
Transmit and receive operations are enabled (The module is in Running state).
#1
TCF
Transfer Complete Flag
31
1
read-write
0
Transfer not complete.
#0
1
Transfer complete.
#1
RSER
DMA/Interrupt Request Select and Enable Register
0x30
32
read-write
0
0xFFFFFFFF
RFDF_DIRS
Receive FIFO Drain DMA or Interrupt Request Select
16
1
read-write
0
Interrupt request.
#0
1
DMA request.
#1
RFDF_RE
Receive FIFO Drain Request Enable
17
1
read-write
0
RFDF interrupt or DMA requests are disabled.
#0
1
RFDF interrupt or DMA requests are enabled.
#1
RFOF_RE
Receive FIFO Overflow Request Enable
19
1
read-write
0
RFOF interrupt requests are disabled.
#0
1
RFOF interrupt requests are enabled.
#1
TFFF_DIRS
Transmit FIFO Fill DMA or Interrupt Request Select
24
1
read-write
0
TFFF flag generates interrupt requests.
#0
1
TFFF flag generates DMA requests.
#1
TFFF_RE
Transmit FIFO Fill Request Enable
25
1
read-write
0
TFFF interrupts or DMA requests are disabled.
#0
1
TFFF interrupts or DMA requests are enabled.
#1
TFUF_RE
Transmit FIFO Underflow Request Enable
27
1
read-write
0
TFUF interrupt requests are disabled.
#0
1
TFUF interrupt requests are enabled.
#1
EOQF_RE
Finished Request Enable
28
1
read-write
0
EOQF interrupt requests are disabled.
#0
1
EOQF interrupt requests are enabled.
#1
TCF_RE
Transmission Complete Request Enable
31
1
read-write
0
TCF interrupt requests are disabled.
#0
1
TCF interrupt requests are enabled.
#1
PUSHR
PUSH TX FIFO Register In Master Mode
SPI2
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-write
PCS
Select which PCS signals are to be asserted for the transfer
16
6
read-write
0
Negate the PCS[x] signal.
#0
1
Assert the PCS[x] signal.
#1
CTCNT
Clear Transfer Counter
26
1
read-write
0
Do not clear the TCR[TCNT] field.
#0
1
Clear the TCR[TCNT] field.
#1
EOQ
End Of Queue
27
1
read-write
0
The SPI data is not the last data to transfer.
#0
1
The SPI data is the last data to transfer.
#1
CTAS
Clock and Transfer Attributes Select
28
3
read-write
000
CTAR0
#000
001
CTAR1
#001
CONT
Continuous Peripheral Chip Select Enable
31
1
read-write
0
Return PCSn signals to their inactive state between transfers.
#0
1
Keep PCSn signals asserted between transfers.
#1
PUSHR_SLAVE
PUSH TX FIFO Register In Slave Mode
SPI2
0x34
32
read-write
0
0xFFFFFFFF
TXDATA
Transmit Data
0
32
read-write
POPR
POP RX FIFO Register
0x38
32
read-only
0
0xFFFFFFFF
RXDATA
Received Data
0
32
read-only
4
0x4
0,1,2,3
TXFR%s
Transmit FIFO Registers
0x3C
32
read-only
0
0xFFFFFFFF
TXDATA
Transmit Data
0
16
read-only
TXCMD_TXDATA
Transmit Command or Transmit Data
16
16
read-only
4
0x4
0,1,2,3
RXFR%s
Receive FIFO Registers
0x7C
32
read-only
0
0xFFFFFFFF
RXDATA
Receive Data
0
32
read-only
I2S0
Inter-IC Sound / Synchronous Audio Interface
I2S0_
0x4002F000
0
0x108
registers
I2S0_Tx
28
I2S0_Rx
29
TCSR
SAI Transmit Control Register
0
32
read-write
0
0xFFFFFFFF
FRDE
FIFO Request DMA Enable
0
1
read-write
0
Disables the DMA request.
#0
1
Enables the DMA request.
#1
FWDE
FIFO Warning DMA Enable
1
1
read-write
0
Disables the DMA request.
#0
1
Enables the DMA request.
#1
FRIE
FIFO Request Interrupt Enable
8
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
FWIE
FIFO Warning Interrupt Enable
9
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
FEIE
FIFO Error Interrupt Enable
10
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
SEIE
Sync Error Interrupt Enable
11
1
read-write
0
Disables interrupt.
#0
1
Enables interrupt.
#1
WSIE
Word Start Interrupt Enable
12
1
read-write
0
Disables interrupt.
#0
1
Enables interrupt.
#1
FRF
FIFO Request Flag
16
1
read-only
0
Transmit FIFO watermark has not been reached.
#0
1
Transmit FIFO watermark has been reached.
#1
FWF
FIFO Warning Flag
17
1
read-only
0
No enabled transmit FIFO is empty.
#0
1
Enabled transmit FIFO is empty.
#1
FEF
FIFO Error Flag
18
1
read-write
0
Transmit underrun not detected.
#0
1
Transmit underrun detected.
#1
SEF
Sync Error Flag
19
1
read-write
0
Sync error not detected.
#0
1
Frame sync error detected.
#1
WSF
Word Start Flag
20
1
read-write
0
Start of word not detected.
#0
1
Start of word detected.
#1
SR
Software Reset
24
1
read-write
0
No effect.
#0
1
Software reset.
#1
FR
FIFO Reset
25
1
write-only
0
No effect.
#0
1
FIFO reset.
#1
BCE
Bit Clock Enable
28
1
read-write
0
Transmit bit clock is disabled.
#0
1
Transmit bit clock is enabled.
#1
DBGE
Debug Enable
29
1
read-write
0
Transmitter is disabled in Debug mode, after completing the current frame.
#0
1
Transmitter is enabled in Debug mode.
#1
STOPE
Stop Enable
30
1
read-write
0
Transmitter disabled in Stop mode.
#0
1
Transmitter enabled in Stop mode.
#1
TE
Transmitter Enable
31
1
read-write
0
Transmitter is disabled.
#0
1
Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
#1
TCR1
SAI Transmit Configuration 1 Register
0x4
32
read-write
0
0xFFFFFFFF
TFW
Transmit FIFO Watermark
0
3
read-write
TCR2
SAI Transmit Configuration 2 Register
0x8
32
read-write
0
0xFFFFFFFF
DIV
Bit Clock Divide
0
8
read-write
BCD
Bit Clock Direction
24
1
read-write
0
Bit clock is generated externally in Slave mode.
#0
1
Bit clock is generated internally in Master mode.
#1
BCP
Bit Clock Polarity
25
1
read-write
0
Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#0
1
Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
#1
MSEL
MCLK Select
26
2
read-write
00
Bus Clock selected.
#00
01
Master Clock (MCLK) 1 option selected.
#01
10
Master Clock (MCLK) 2 option selected.
#10
11
Master Clock (MCLK) 3 option selected.
#11
BCI
Bit Clock Input
28
1
read-write
0
No effect.
#0
1
Internal logic is clocked as if bit clock was externally generated.
#1
BCS
Bit Clock Swap
29
1
read-write
0
Use the normal bit clock source.
#0
1
Swap the bit clock source.
#1
SYNC
Synchronous Mode
30
2
read-write
00
Asynchronous mode.
#00
01
Synchronous with receiver.
#01
10
Synchronous with another SAI transmitter.
#10
11
Synchronous with another SAI receiver.
#11
TCR3
SAI Transmit Configuration 3 Register
0xC
32
read-write
0
0xFFFFFFFF
WDFL
Word Flag Configuration
0
5
read-write
TCE
Transmit Channel Enable
16
2
read-write
0
Transmit data channel N is disabled.
#00
1
Transmit data channel N is enabled.
#01
TCR4
SAI Transmit Configuration 4 Register
0x10
32
read-write
0
0xFFFFFFFF
FSD
Frame Sync Direction
0
1
read-write
0
Frame sync is generated externally in Slave mode.
#0
1
Frame sync is generated internally in Master mode.
#1
FSP
Frame Sync Polarity
1
1
read-write
0
Frame sync is active high.
#0
1
Frame sync is active low.
#1
FSE
Frame Sync Early
3
1
read-write
0
Frame sync asserts with the first bit of the frame.
#0
1
Frame sync asserts one bit before the first bit of the frame.
#1
MF
MSB First
4
1
read-write
0
LSB is transmitted first.
#0
1
MSB is transmitted first.
#1
SYWD
Sync Width
8
5
read-write
FRSZ
Frame size
16
5
read-write
TCR5
SAI Transmit Configuration 5 Register
0x14
32
read-write
0
0xFFFFFFFF
FBT
First Bit Shifted
8
5
read-write
W0W
Word 0 Width
16
5
read-write
WNW
Word N Width
24
5
read-write
2
0x4
0,1
TDR%s
SAI Transmit Data Register
0x20
32
write-only
0
0xFFFFFFFF
TDR
Transmit Data Register
0
32
write-only
2
0x4
0,1
TFR%s
SAI Transmit FIFO Register
0x40
32
read-only
0
0xFFFFFFFF
RFP
Read FIFO Pointer
0
4
read-only
WFP
Write FIFO Pointer
16
4
read-only
TMR
SAI Transmit Mask Register
0x60
32
read-write
0
0xFFFFFFFF
TWM
Transmit Word Mask
0
32
read-write
0
Word N is enabled.
#0
1
Word N is masked. The transmit data pins are tri-stated when masked.
#1
RCSR
SAI Receive Control Register
0x80
32
read-write
0
0xFFFFFFFF
FRDE
FIFO Request DMA Enable
0
1
read-write
0
Disables the DMA request.
#0
1
Enables the DMA request.
#1
FWDE
FIFO Warning DMA Enable
1
1
read-write
0
Disables the DMA request.
#0
1
Enables the DMA request.
#1
FRIE
FIFO Request Interrupt Enable
8
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
FWIE
FIFO Warning Interrupt Enable
9
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
FEIE
FIFO Error Interrupt Enable
10
1
read-write
0
Disables the interrupt.
#0
1
Enables the interrupt.
#1
SEIE
Sync Error Interrupt Enable
11
1
read-write
0
Disables interrupt.
#0
1
Enables interrupt.
#1
WSIE
Word Start Interrupt Enable
12
1
read-write
0
Disables interrupt.
#0
1
Enables interrupt.
#1
FRF
FIFO Request Flag
16
1
read-only
0
Receive FIFO watermark not reached.
#0
1
Receive FIFO watermark has been reached.
#1
FWF
FIFO Warning Flag
17
1
read-only
0
No enabled receive FIFO is full.
#0
1
Enabled receive FIFO is full.
#1
FEF
FIFO Error Flag
18
1
read-write
0
Receive overflow not detected.
#0
1
Receive overflow detected.
#1
SEF
Sync Error Flag
19
1
read-write
0
Sync error not detected.
#0
1
Frame sync error detected.
#1
WSF
Word Start Flag
20
1
read-write
0
Start of word not detected.
#0
1
Start of word detected.
#1
SR
Software Reset
24
1
read-write
0
No effect.
#0
1
Software reset.
#1
FR
FIFO Reset
25
1
write-only
0
No effect.
#0
1
FIFO reset.
#1
BCE
Bit Clock Enable
28
1
read-write
0
Receive bit clock is disabled.
#0
1
Receive bit clock is enabled.
#1
DBGE
Debug Enable
29
1
read-write
0
Receiver is disabled in Debug mode, after completing the current frame.
#0
1
Receiver is enabled in Debug mode.
#1
STOPE
Stop Enable
30
1
read-write
0
Receiver disabled in Stop mode.
#0
1
Receiver enabled in Stop mode.
#1
RE
Receiver Enable
31
1
read-write
0
Receiver is disabled.
#0
1
Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
#1
RCR1
SAI Receive Configuration 1 Register
0x84
32
read-write
0
0xFFFFFFFF
RFW
Receive FIFO Watermark
0
3
read-write
RCR2
SAI Receive Configuration 2 Register
0x88
32
read-write
0
0xFFFFFFFF
DIV
Bit Clock Divide
0
8
read-write
BCD
Bit Clock Direction
24
1
read-write
0
Bit clock is generated externally in Slave mode.
#0
1
Bit clock is generated internally in Master mode.
#1
BCP
Bit Clock Polarity
25
1
read-write
0
Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#0
1
Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
#1
MSEL
MCLK Select
26
2
read-write
00
Bus Clock selected.
#00
01
Master Clock (MCLK) 1 option selected.
#01
10
Master Clock (MCLK) 2 option selected.
#10
11
Master Clock (MCLK) 3 option selected.
#11
BCI
Bit Clock Input
28
1
read-write
0
No effect.
#0
1
Internal logic is clocked as if bit clock was externally generated.
#1
BCS
Bit Clock Swap
29
1
read-write
0
Use the normal bit clock source.
#0
1
Swap the bit clock source.
#1
SYNC
Synchronous Mode
30
2
read-write
00
Asynchronous mode.
#00
01
Synchronous with transmitter.
#01
10
Synchronous with another SAI receiver.
#10
11
Synchronous with another SAI transmitter.
#11
RCR3
SAI Receive Configuration 3 Register
0x8C
32
read-write
0
0xFFFFFFFF
WDFL
Word Flag Configuration
0
5
read-write
RCE
Receive Channel Enable
16
2
read-write
0
Receive data channel N is disabled.
#00
1
Receive data channel N is enabled.
#01
RCR4
SAI Receive Configuration 4 Register
0x90
32
read-write
0
0xFFFFFFFF
FSD
Frame Sync Direction
0
1
read-write
0
Frame Sync is generated externally in Slave mode.
#0
1
Frame Sync is generated internally in Master mode.
#1
FSP
Frame Sync Polarity
1
1
read-write
0
Frame sync is active high.
#0
1
Frame sync is active low.
#1
FSE
Frame Sync Early
3
1
read-write
0
Frame sync asserts with the first bit of the frame.
#0
1
Frame sync asserts one bit before the first bit of the frame.
#1
MF
MSB First
4
1
read-write
0
LSB is received first.
#0
1
MSB is received first.
#1
SYWD
Sync Width
8
5
read-write
FRSZ
Frame Size
16
5
read-write
RCR5
SAI Receive Configuration 5 Register
0x94
32
read-write
0
0xFFFFFFFF
FBT
First Bit Shifted
8
5
read-write
W0W
Word 0 Width
16
5
read-write
WNW
Word N Width
24
5
read-write
2
0x4
0,1
RDR%s
SAI Receive Data Register
0xA0
32
read-only
0
0xFFFFFFFF
RDR
Receive Data Register
0
32
read-only
2
0x4
0,1
RFR%s
SAI Receive FIFO Register
0xC0
32
read-only
0
0xFFFFFFFF
RFP
Read FIFO Pointer
0
4
read-only
WFP
Write FIFO Pointer
16
4
read-only
RMR
SAI Receive Mask Register
0xE0
32
read-write
0
0xFFFFFFFF
RWM
Receive Word Mask
0
32
read-write
0
Word N is enabled.
#0
1
Word N is masked.
#1
MCR
SAI MCLK Control Register
0x100
32
read-write
0
0xFFFFFFFF
MICS
MCLK Input Clock Select
24
2
read-write
00
MCLK divider input clock 0 selected.
#00
01
MCLK divider input clock 1 selected.
#01
10
MCLK divider input clock 2 selected.
#10
11
MCLK divider input clock 3 selected.
#11
MOE
MCLK Output Enable
30
1
read-write
0
MCLK signal pin is configured as an input that bypasses the MCLK divider.
#0
1
MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
#1
DUF
Divider Update Flag
31
1
read-only
0
MCLK divider ratio is not being updated currently.
#0
1
MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
#1
MDR
SAI MCLK Divide Register
0x104
32
read-write
0
0xFFFFFFFF
DIVIDE
MCLK Divide
0
12
read-write
FRACT
MCLK Fraction
12
8
read-write
CRC
Cyclic Redundancy Check
CRC_
0x40032000
0
0xC
registers
DATA
CRC Data register
CRC
0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
LL
CRC Low Lower Byte
0
8
read-write
LU
CRC Low Upper Byte
8
8
read-write
HL
CRC High Lower Byte
16
8
read-write
HU
CRC High Upper Byte
24
8
read-write
DATAL
CRC_DATAL register.
CRC
0
16
read-write
0xFFFF
0xFFFF
DATAL
DATAL stores the lower 16 bits of the 16/32 bit CRC
0
16
read-write
DATALL
CRC_DATALL register.
CRC
0
8
read-write
0xFF
0xFF
DATALL
CRCLL stores the first 8 bits of the 32 bit DATA
0
8
read-write
DATALU
CRC_DATALU register.
0x1
8
read-write
0xFF
0xFF
DATALU
DATALL stores the second 8 bits of the 32 bit CRC
0
8
read-write
DATAH
CRC_DATAH register.
CRC
0x2
16
read-write
0xFFFF
0xFFFF
DATAH
DATAH stores the high 16 bits of the 16/32 bit CRC
0
16
read-write
DATAHL
CRC_DATAHL register.
CRC
0x2
8
read-write
0xFF
0xFF
DATAHL
DATAHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
DATAHU
CRC_DATAHU register.
0x3
8
read-write
0xFF
0xFF
DATAHU
DATAHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
GPOLY
CRC Polynomial register
CRC
0x4
32
read-write
0x1021
0xFFFFFFFF
LOW
Low Polynominal Half-word
0
16
read-write
HIGH
High Polynominal Half-word
16
16
read-write
GPOLYL
CRC_GPOLYL register.
CRC
0x4
16
read-write
0xFFFF
0xFFFF
GPOLYL
POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYLL
CRC_GPOLYLL register.
CRC
0x4
8
read-write
0xFF
0xFF
GPOLYLL
POLYLL stores the first 8 bits of the 32 bit CRC
0
8
read-write
GPOLYLU
CRC_GPOLYLU register.
0x5
8
read-write
0xFF
0xFF
GPOLYLU
POLYLL stores the second 8 bits of the 32 bit CRC
0
8
read-write
GPOLYH
CRC_GPOLYH register.
CRC
0x6
16
read-write
0xFFFF
0xFFFF
GPOLYH
POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYHL
CRC_GPOLYHL register.
CRC
0x6
8
read-write
0xFF
0xFF
GPOLYHL
POLYHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
GPOLYHU
CRC_GPOLYHU register.
0x7
8
read-write
0xFF
0xFF
GPOLYHU
POLYHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
CTRL
CRC Control register
0x8
32
read-write
0
0xFFFFFFFF
TCRC
Width of CRC protocol.
24
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
WAS
Write CRC Data Register As Seed
25
1
read-write
0
Writes to the CRC data register are data values.
#0
1
Writes to the CRC data register are seed values.
#1
FXOR
Complement Read Of CRC Data Register
26
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of the CRC Data register.
#1
TOTR
Type Of Transpose For Read
28
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOT
Type Of Transpose For Writes
30
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
CTRLHU
CRC_CTRLHU register.
0xB
8
read-write
0
0xFF
TCRC
no description available
0
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
WAS
no description available
1
1
read-write
0
Writes to CRC data register are data values.
#0
1
Writes to CRC data reguster are seed values.
#1
FXOR
no description available
2
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of CRC data register.
#1
TOTR
no description available
4
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOT
no description available
6
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
USBDCD
USB Device Charger Detection module
USBDCD_
0x40035000
0
0x1C
registers
USBDCD
54
CONTROL
Control register
0
32
read-write
0x10000
0xFFFFFFFF
IACK
Interrupt Acknowledge
0
1
write-only
0
Do not clear the interrupt.
#0
1
Clear the IF bit (interrupt flag).
#1
IF
Interrupt Flag
8
1
read-only
0
No interrupt is pending.
#0
1
An interrupt is pending.
#1
IE
Interrupt Enable
16
1
read-write
0
Disable interrupts to the system.
#0
1
Enable interrupts to the system.
#1
BC12
BC1.2 compatibility. This bit cannot be changed after start detection.
17
1
read-write
0
Compatible with BC1.1 (default)
#0
1
Compatible with BC1.2
#1
START
Start Change Detection Sequence
24
1
write-only
0
Do not start the sequence. Writes of this value have no effect.
#0
1
Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
#1
SR
Software Reset
25
1
write-only
0
Do not perform a software reset.
#0
1
Perform a software reset.
#1
CLOCK
Clock register
0x4
32
read-write
0xC1
0xFFFFFFFF
CLOCK_UNIT
Unit of Measurement Encoding for Clock Speed
0
1
read-write
0
kHz Speed (between 1 kHz and 1023 kHz)
#0
1
MHz Speed (between 1 MHz and 1023 MHz)
#1
CLOCK_SPEED
Numerical Value of Clock Speed in Binary
2
10
read-write
STATUS
Status register
0x8
32
read-only
0
0xFFFFFFFF
SEQ_RES
Charger Detection Sequence Results
16
2
read-only
00
No results to report.
#00
01
Attached to a standard host. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
#01
10
Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a charging host or a dedicated charger. The charger type detection has not completed. 1: Attached to a charging host. The charger type detection has completed.
#10
11
Attached to a dedicated charger.
#11
SEQ_STAT
Charger Detection Sequence Status
18
2
read-only
00
The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
#00
01
Data pin contact detection is complete.
#01
10
Charging port detection is complete.
#10
11
Charger type detection is complete.
#11
ERR
Error Flag
20
1
read-only
0
No sequence errors.
#0
1
Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
#1
TO
Timeout Flag
21
1
read-only
0
The detection sequence has not been running for over 1 s.
#0
1
It has been over 1 s since the data pin contact was detected and debounced.
#1
ACTIVE
Active Status Indicator
22
1
read-only
0
The sequence is not running.
#0
1
The sequence is running.
#1
TIMER0
TIMER0 register
0x10
32
read-write
0x100000
0xFFFFFFFF
TUNITCON
Unit Connection Timer Elapse (in ms)
0
12
read-only
TSEQ_INIT
Sequence Initiation Time
16
10
read-write
TIMER1
TIMER1 register
0x14
32
read-write
0xA0028
0xFFFFFFFF
TVDPSRC_ON
Time Period Comparator Enabled
0
10
read-write
TDCD_DBNC
Time Period to Debounce D+ Signal
16
10
read-write
TIMER2_BC11
TIMER2_BC11 register
USBDCD
0x18
32
read-write
0x280001
0xFFFFFFFF
CHECK_DM
Time Before Check of D- Line
0
4
read-write
TVDPSRC_CON
Time Period Before Enabling D+ Pullup
16
10
read-write
TIMER2_BC12
TIMER2_BC12 register
USBDCD
0x18
32
read-write
0x10028
0xFFFFFFFF
TVDMSRC_ON
Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid values are 0-40ms.
0
10
read-write
TWAIT_AFTER_PRD
Sets the amount of time (in ms) that the module waits after primary detection before start to secondary detection
16
10
read-write
PDB0
Programmable Delay Block
PDB0_
0x40036000
0
0x1A0
registers
PDB0
52
SC
Status and Control register
0
32
read-write
0
0xFFFFFFFF
LDOK
Load OK
0
1
read-write
CONT
Continuous Mode Enable
1
1
read-write
0
PDB operation in One-Shot mode
#0
1
PDB operation in Continuous mode
#1
MULT
Multiplication Factor Select for Prescaler
2
2
read-write
00
Multiplication factor is 1.
#00
01
Multiplication factor is 10.
#01
10
Multiplication factor is 20.
#10
11
Multiplication factor is 40.
#11
PDBIE
PDB Interrupt Enable
5
1
read-write
0
PDB interrupt disabled.
#0
1
PDB interrupt enabled.
#1
PDBIF
PDB Interrupt Flag
6
1
read-write
PDBEN
PDB Enable
7
1
read-write
0
PDB disabled. Counter is off.
#0
1
PDB enabled.
#1
TRGSEL
Trigger Input Source Select
8
4
read-write
0000
Trigger-In 0 is selected.
#0000
0001
Trigger-In 1 is selected.
#0001
0010
Trigger-In 2 is selected.
#0010
0011
Trigger-In 3 is selected.
#0011
0100
Trigger-In 4 is selected.
#0100
0101
Trigger-In 5 is selected.
#0101
0110
Trigger-In 6 is selected.
#0110
0111
Trigger-In 7 is selected.
#0111
1000
Trigger-In 8 is selected.
#1000
1001
Trigger-In 9 is selected.
#1001
1010
Trigger-In 10 is selected.
#1010
1011
Trigger-In 11 is selected.
#1011
1100
Trigger-In 12 is selected.
#1100
1101
Trigger-In 13 is selected.
#1101
1110
Trigger-In 14 is selected.
#1110
1111
Software trigger is selected.
#1111
PRESCALER
Prescaler Divider Select
12
3
read-write
000
Counting uses the peripheral clock divided by multiplication factor selected by MULT.
#000
001
Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
#001
010
Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
#010
011
Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
#011
100
Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
#100
101
Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
#101
110
Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
#110
111
Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
#111
DMAEN
DMA Enable
15
1
read-write
0
DMA disabled.
#0
1
DMA enabled.
#1
SWTRIG
Software Trigger
16
1
write-only
PDBEIE
PDB Sequence Error Interrupt Enable
17
1
read-write
0
PDB sequence error interrupt disabled.
#0
1
PDB sequence error interrupt enabled.
#1
LDMOD
Load Mode Select
18
2
read-write
00
The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
#00
01
The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
#01
10
The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
#10
11
The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
#11
MOD
Modulus register
0x4
32
read-write
0xFFFF
0xFFFFFFFF
MOD
PDB Modulus
0
16
read-write
CNT
Counter register
0x8
32
read-only
0
0xFFFFFFFF
CNT
PDB Counter
0
16
read-only
IDLY
Interrupt Delay register
0xC
32
read-write
0xFFFF
0xFFFFFFFF
IDLY
PDB Interrupt Delay
0
16
read-write
2
0x28
0,1
CH%sC1
Channel n Control register 1
0x10
32
read-write
0
0xFFFFFFFF
EN
PDB Channel Pre-Trigger Enable
0
8
read-write
0
PDB channel's corresponding pre-trigger disabled.
#0
1
PDB channel's corresponding pre-trigger enabled.
#1
TOS
PDB Channel Pre-Trigger Output Select
8
8
read-write
0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#0
1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
#1
BB
PDB Channel Pre-Trigger Back-to-Back Operation Enable
16
8
read-write
0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
#0
1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
#1
2
0x28
0,1
CH%sS
Channel n Status register
0x14
32
read-write
0
0xFFFFFFFF
ERR
PDB Channel Sequence Error Flags
0
8
read-write
0
Sequence error not detected on PDB channel's corresponding pre-trigger.
#0
1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
#1
CF
PDB Channel Flags
16
8
read-write
2
0x28
0,1
CH%sDLY0
Channel n Delay 0 register
0x18
32
read-write
0
0xFFFFFFFF
DLY
PDB Channel Delay
0
16
read-write
2
0x28
0,1
CH%sDLY1
Channel n Delay 1 register
0x1C
32
read-write
0
0xFFFFFFFF
DLY
PDB Channel Delay
0
16
read-write
2
0x8
0,1
DACINTC%s
DAC Interval Trigger n Control register
0x150
32
read-write
0
0xFFFFFFFF
TOE
DAC Interval Trigger Enable
0
1
read-write
0
DAC interval trigger disabled.
#0
1
DAC interval trigger enabled.
#1
EXT
DAC External Trigger Input Enable
1
1
read-write
0
DAC external trigger input disabled. DAC interval counter is reset and counting starts when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#0
1
DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
#1
2
0x8
0,1
DACINT%s
DAC Interval n register
0x154
32
read-write
0
0xFFFFFFFF
INT
DAC Interval
0
16
read-write
POEN
Pulse-Out n Enable register
0x190
32
read-write
0
0xFFFFFFFF
POEN
PDB Pulse-Out Enable
0
8
read-write
0
PDB Pulse-Out disabled
#0
1
PDB Pulse-Out enabled
#1
3
0x4
0,1,2
PO%sDLY
Pulse-Out n Delay register
0x194
32
read-write
0
0xFFFFFFFF
DLY2
PDB Pulse-Out Delay 2
0
16
read-write
DLY1
PDB Pulse-Out Delay 1
16
16
read-write
PIT
Periodic Interrupt Timer
PIT_
0x40037000
0
0x140
registers
PIT0
48
PIT1
49
PIT2
50
PIT3
51
MCR
PIT Module Control Register
0
32
read-write
0x6
0xFFFFFFFF
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
4
0x10
0,1,2,3
LDVAL%s
Timer Load Value Register
0x100
32
read-write
0
0xFFFFFFFF
TSV
Timer Start Value
0
32
read-write
4
0x10
0,1,2,3
CVAL%s
Current Timer Value Register
0x104
32
read-only
0
0xFFFFFFFF
TVL
Current Timer Value
0
32
read-only
4
0x10
0,1,2,3
TCTRL%s
Timer Control Register
0x108
32
read-write
0
0xFFFFFFFF
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
4
0x10
0,1,2,3
TFLG%s
Timer Flag Register
0x10C
32
read-write
0
0xFFFFFFFF
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
FTM0
FlexTimer Module
FTM
FTM0_
0x40038000
0
0x9C
registers
FTM0
42
SC
Status And Control
0
32
read-write
0
0xFFFFFFFF
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
CNT
Counter
0x4
32
read-write
0
0xFFFFFFFF
COUNT
Counter Value
0
16
read-write
MOD
Modulo
0x8
32
read-write
0
0xFFFFFFFF
MOD
Modulo Value
0
16
read-write
8
0x8
0,1,2,3,4,5,6,7
C%sSC
Channel (n) Status And Control
0xC
32
read-write
0
0xFFFFFFFF
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
8
0x8
0,1,2,3,4,5,6,7
C%sV
Channel (n) Value
0x10
32
read-write
0
0xFFFFFFFF
VAL
Channel Value
0
16
read-write
CNTIN
Counter Initial Value
0x4C
32
read-write
0
0xFFFFFFFF
INIT
Initial Value Of The FTM Counter
0
16
read-write
STATUS
Capture And Compare Status
0x50
32
read-write
0
0xFFFFFFFF
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
MODE
Features Mode Selection
0x54
32
read-write
0x4
0xFFFFFFFF
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
SYNC
Synchronization
0x58
32
read-write
0
0xFFFFFFFF
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
0
0xFFFFFFFF
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
OUTMASK
Output Mask
0x60
32
read-write
0
0xFFFFFFFF
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
COMBINE
Function For Linked Channels
0x64
32
read-write
0
0xFFFFFFFF
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
0
0xFFFFFFFF
DTVAL
Deadtime Value
0
6
read-write
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
EXTTRIG
FTM External Trigger
0x6C
32
read-write
0
0xFFFFFFFF
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
POL
Channels Polarity
0x70
32
read-write
0
0xFFFFFFFF
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
FMS
Fault Mode Status
0x74
32
read-write
0
0xFFFFFFFF
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
0
0xFFFFFFFF
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
0
0xFFFFFFFF
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
QDCTRL
Quadrature Decoder Control And Status
0x80
32
read-write
0
0xFFFFFFFF
QUADEN
Quadrature Decoder Mode Enable
0
1
read-write
0
Quadrature Decoder mode is disabled.
#0
1
Quadrature Decoder mode is enabled.
#1
TOFDIR
Timer Overflow Direction In Quadrature Decoder Mode
1
1
read-only
0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#0
1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
#1
QUADIR
FTM Counter Direction In Quadrature Decoder Mode
2
1
read-only
0
Counting direction is decreasing (FTM counter decrement).
#0
1
Counting direction is increasing (FTM counter increment).
#1
QUADMODE
Quadrature Decoder Mode
3
1
read-write
0
Phase A and phase B encoding mode.
#0
1
Count and direction encoding mode.
#1
PHBPOL
Phase B Input Polarity
4
1
read-write
0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHAPOL
Phase A Input Polarity
5
1
read-write
0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHBFLTREN
Phase B Input Filter Enable
6
1
read-write
0
Phase B input filter is disabled.
#0
1
Phase B input filter is enabled.
#1
PHAFLTREN
Phase A Input Filter Enable
7
1
read-write
0
Phase A input filter is disabled.
#0
1
Phase A input filter is enabled.
#1
CONF
Configuration
0x84
32
read-write
0
0xFFFFFFFF
NUMTOF
TOF Frequency
0
5
read-write
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
0
0xFFFFFFFF
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
0
0xFFFFFFFF
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
SWRSTCNT
FTM counter synchronization is activated by the software trigger.
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SWOM
Output mask synchronization is activated by the software trigger.
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWINVC
Inverting control synchronization is activated by the software trigger.
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWSOC
Software output control synchronization is activated by the software trigger.
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
HWRSTCNT
FTM counter synchronization is activated by a hardware trigger.
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
HWOM
Output mask synchronization is activated by a hardware trigger.
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWINVC
Inverting control synchronization is activated by a hardware trigger.
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWSOC
Software output control synchronization is activated by a hardware trigger.
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
0
0xFFFFFFFF
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
SWOCTRL
FTM Software Output Control
0x94
32
read-write
0
0xFFFFFFFF
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
PWMLOAD
FTM PWM Load
0x98
32
read-write
0
0xFFFFFFFF
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
FTM1
FlexTimer Module
FTM
FTM1_
0x40039000
0
0x9C
registers
FTM1
43
SC
Status And Control
0
32
read-write
0
0xFFFFFFFF
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
CNT
Counter
0x4
32
read-write
0
0xFFFFFFFF
COUNT
Counter Value
0
16
read-write
MOD
Modulo
0x8
32
read-write
0
0xFFFFFFFF
MOD
Modulo Value
0
16
read-write
2
0x8
0,1
C%sSC
Channel (n) Status And Control
0xC
32
read-write
0
0xFFFFFFFF
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
2
0x8
0,1
C%sV
Channel (n) Value
0x10
32
read-write
0
0xFFFFFFFF
VAL
Channel Value
0
16
read-write
CNTIN
Counter Initial Value
0x4C
32
read-write
0
0xFFFFFFFF
INIT
Initial Value Of The FTM Counter
0
16
read-write
STATUS
Capture And Compare Status
0x50
32
read-write
0
0xFFFFFFFF
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
MODE
Features Mode Selection
0x54
32
read-write
0x4
0xFFFFFFFF
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
SYNC
Synchronization
0x58
32
read-write
0
0xFFFFFFFF
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
0
0xFFFFFFFF
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
OUTMASK
Output Mask
0x60
32
read-write
0
0xFFFFFFFF
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
COMBINE
Function For Linked Channels
0x64
32
read-write
0
0xFFFFFFFF
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
0
0xFFFFFFFF
DTVAL
Deadtime Value
0
6
read-write
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
EXTTRIG
FTM External Trigger
0x6C
32
read-write
0
0xFFFFFFFF
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
POL
Channels Polarity
0x70
32
read-write
0
0xFFFFFFFF
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
FMS
Fault Mode Status
0x74
32
read-write
0
0xFFFFFFFF
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
0
0xFFFFFFFF
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
0
0xFFFFFFFF
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
QDCTRL
Quadrature Decoder Control And Status
0x80
32
read-write
0
0xFFFFFFFF
QUADEN
Quadrature Decoder Mode Enable
0
1
read-write
0
Quadrature Decoder mode is disabled.
#0
1
Quadrature Decoder mode is enabled.
#1
TOFDIR
Timer Overflow Direction In Quadrature Decoder Mode
1
1
read-only
0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#0
1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
#1
QUADIR
FTM Counter Direction In Quadrature Decoder Mode
2
1
read-only
0
Counting direction is decreasing (FTM counter decrement).
#0
1
Counting direction is increasing (FTM counter increment).
#1
QUADMODE
Quadrature Decoder Mode
3
1
read-write
0
Phase A and phase B encoding mode.
#0
1
Count and direction encoding mode.
#1
PHBPOL
Phase B Input Polarity
4
1
read-write
0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHAPOL
Phase A Input Polarity
5
1
read-write
0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHBFLTREN
Phase B Input Filter Enable
6
1
read-write
0
Phase B input filter is disabled.
#0
1
Phase B input filter is enabled.
#1
PHAFLTREN
Phase A Input Filter Enable
7
1
read-write
0
Phase A input filter is disabled.
#0
1
Phase A input filter is enabled.
#1
CONF
Configuration
0x84
32
read-write
0
0xFFFFFFFF
NUMTOF
TOF Frequency
0
5
read-write
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
0
0xFFFFFFFF
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
0
0xFFFFFFFF
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
SWRSTCNT
FTM counter synchronization is activated by the software trigger.
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SWOM
Output mask synchronization is activated by the software trigger.
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWINVC
Inverting control synchronization is activated by the software trigger.
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWSOC
Software output control synchronization is activated by the software trigger.
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
HWRSTCNT
FTM counter synchronization is activated by a hardware trigger.
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
HWOM
Output mask synchronization is activated by a hardware trigger.
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWINVC
Inverting control synchronization is activated by a hardware trigger.
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWSOC
Software output control synchronization is activated by a hardware trigger.
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
0
0xFFFFFFFF
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
SWOCTRL
FTM Software Output Control
0x94
32
read-write
0
0xFFFFFFFF
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
PWMLOAD
FTM PWM Load
0x98
32
read-write
0
0xFFFFFFFF
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
FTM2
FlexTimer Module
FTM
FTM2_
0x4003A000
0
0x9C
registers
FTM2
44
SC
Status And Control
0
32
read-write
0
0xFFFFFFFF
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
CNT
Counter
0x4
32
read-write
0
0xFFFFFFFF
COUNT
Counter Value
0
16
read-write
MOD
Modulo
0x8
32
read-write
0
0xFFFFFFFF
MOD
Modulo Value
0
16
read-write
2
0x8
0,1
C%sSC
Channel (n) Status And Control
0xC
32
read-write
0
0xFFFFFFFF
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
2
0x8
0,1
C%sV
Channel (n) Value
0x10
32
read-write
0
0xFFFFFFFF
VAL
Channel Value
0
16
read-write
CNTIN
Counter Initial Value
0x4C
32
read-write
0
0xFFFFFFFF
INIT
Initial Value Of The FTM Counter
0
16
read-write
STATUS
Capture And Compare Status
0x50
32
read-write
0
0xFFFFFFFF
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
MODE
Features Mode Selection
0x54
32
read-write
0x4
0xFFFFFFFF
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
SYNC
Synchronization
0x58
32
read-write
0
0xFFFFFFFF
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
0
0xFFFFFFFF
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
OUTMASK
Output Mask
0x60
32
read-write
0
0xFFFFFFFF
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
COMBINE
Function For Linked Channels
0x64
32
read-write
0
0xFFFFFFFF
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
0
0xFFFFFFFF
DTVAL
Deadtime Value
0
6
read-write
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
EXTTRIG
FTM External Trigger
0x6C
32
read-write
0
0xFFFFFFFF
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
POL
Channels Polarity
0x70
32
read-write
0
0xFFFFFFFF
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
FMS
Fault Mode Status
0x74
32
read-write
0
0xFFFFFFFF
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
0
0xFFFFFFFF
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
0
0xFFFFFFFF
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
QDCTRL
Quadrature Decoder Control And Status
0x80
32
read-write
0
0xFFFFFFFF
QUADEN
Quadrature Decoder Mode Enable
0
1
read-write
0
Quadrature Decoder mode is disabled.
#0
1
Quadrature Decoder mode is enabled.
#1
TOFDIR
Timer Overflow Direction In Quadrature Decoder Mode
1
1
read-only
0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#0
1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
#1
QUADIR
FTM Counter Direction In Quadrature Decoder Mode
2
1
read-only
0
Counting direction is decreasing (FTM counter decrement).
#0
1
Counting direction is increasing (FTM counter increment).
#1
QUADMODE
Quadrature Decoder Mode
3
1
read-write
0
Phase A and phase B encoding mode.
#0
1
Count and direction encoding mode.
#1
PHBPOL
Phase B Input Polarity
4
1
read-write
0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHAPOL
Phase A Input Polarity
5
1
read-write
0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHBFLTREN
Phase B Input Filter Enable
6
1
read-write
0
Phase B input filter is disabled.
#0
1
Phase B input filter is enabled.
#1
PHAFLTREN
Phase A Input Filter Enable
7
1
read-write
0
Phase A input filter is disabled.
#0
1
Phase A input filter is enabled.
#1
CONF
Configuration
0x84
32
read-write
0
0xFFFFFFFF
NUMTOF
TOF Frequency
0
5
read-write
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
0
0xFFFFFFFF
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
0
0xFFFFFFFF
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
SWRSTCNT
FTM counter synchronization is activated by the software trigger.
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SWOM
Output mask synchronization is activated by the software trigger.
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWINVC
Inverting control synchronization is activated by the software trigger.
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWSOC
Software output control synchronization is activated by the software trigger.
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
HWRSTCNT
FTM counter synchronization is activated by a hardware trigger.
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
HWOM
Output mask synchronization is activated by a hardware trigger.
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWINVC
Inverting control synchronization is activated by a hardware trigger.
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWSOC
Software output control synchronization is activated by a hardware trigger.
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
0
0xFFFFFFFF
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
SWOCTRL
FTM Software Output Control
0x94
32
read-write
0
0xFFFFFFFF
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
PWMLOAD
FTM PWM Load
0x98
32
read-write
0
0xFFFFFFFF
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
FTM3
FlexTimer Module
FTM
FTM3_
0x400B9000
0
0x9C
registers
FTM3
71
SC
Status And Control
0
32
read-write
0
0xFFFFFFFF
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
CNT
Counter
0x4
32
read-write
0
0xFFFFFFFF
COUNT
Counter Value
0
16
read-write
MOD
Modulo
0x8
32
read-write
0
0xFFFFFFFF
MOD
Modulo Value
0
16
read-write
8
0x8
0,1,2,3,4,5,6,7
C%sSC
Channel (n) Status And Control
0xC
32
read-write
0
0xFFFFFFFF
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
8
0x8
0,1,2,3,4,5,6,7
C%sV
Channel (n) Value
0x10
32
read-write
0
0xFFFFFFFF
VAL
Channel Value
0
16
read-write
CNTIN
Counter Initial Value
0x4C
32
read-write
0
0xFFFFFFFF
INIT
Initial Value Of The FTM Counter
0
16
read-write
STATUS
Capture And Compare Status
0x50
32
read-write
0
0xFFFFFFFF
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
MODE
Features Mode Selection
0x54
32
read-write
0x4
0xFFFFFFFF
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
SYNC
Synchronization
0x58
32
read-write
0
0xFFFFFFFF
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
0
0xFFFFFFFF
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
OUTMASK
Output Mask
0x60
32
read-write
0
0xFFFFFFFF
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
COMBINE
Function For Linked Channels
0x64
32
read-write
0
0xFFFFFFFF
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
0
0xFFFFFFFF
DTVAL
Deadtime Value
0
6
read-write
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
EXTTRIG
FTM External Trigger
0x6C
32
read-write
0
0xFFFFFFFF
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
POL
Channels Polarity
0x70
32
read-write
0
0xFFFFFFFF
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
FMS
Fault Mode Status
0x74
32
read-write
0
0xFFFFFFFF
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
0
0xFFFFFFFF
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
0
0xFFFFFFFF
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
QDCTRL
Quadrature Decoder Control And Status
0x80
32
read-write
0
0xFFFFFFFF
QUADEN
Quadrature Decoder Mode Enable
0
1
read-write
0
Quadrature Decoder mode is disabled.
#0
1
Quadrature Decoder mode is enabled.
#1
TOFDIR
Timer Overflow Direction In Quadrature Decoder Mode
1
1
read-only
0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#0
1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
#1
QUADIR
FTM Counter Direction In Quadrature Decoder Mode
2
1
read-only
0
Counting direction is decreasing (FTM counter decrement).
#0
1
Counting direction is increasing (FTM counter increment).
#1
QUADMODE
Quadrature Decoder Mode
3
1
read-write
0
Phase A and phase B encoding mode.
#0
1
Count and direction encoding mode.
#1
PHBPOL
Phase B Input Polarity
4
1
read-write
0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHAPOL
Phase A Input Polarity
5
1
read-write
0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#0
1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
#1
PHBFLTREN
Phase B Input Filter Enable
6
1
read-write
0
Phase B input filter is disabled.
#0
1
Phase B input filter is enabled.
#1
PHAFLTREN
Phase A Input Filter Enable
7
1
read-write
0
Phase A input filter is disabled.
#0
1
Phase A input filter is enabled.
#1
CONF
Configuration
0x84
32
read-write
0
0xFFFFFFFF
NUMTOF
TOF Frequency
0
5
read-write
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
0
0xFFFFFFFF
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
0
0xFFFFFFFF
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
SWRSTCNT
FTM counter synchronization is activated by the software trigger.
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SWOM
Output mask synchronization is activated by the software trigger.
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWINVC
Inverting control synchronization is activated by the software trigger.
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWSOC
Software output control synchronization is activated by the software trigger.
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
HWRSTCNT
FTM counter synchronization is activated by a hardware trigger.
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
HWOM
Output mask synchronization is activated by a hardware trigger.
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWINVC
Inverting control synchronization is activated by a hardware trigger.
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWSOC
Software output control synchronization is activated by a hardware trigger.
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
0
0xFFFFFFFF
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
SWOCTRL
FTM Software Output Control
0x94
32
read-write
0
0xFFFFFFFF
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
PWMLOAD
FTM PWM Load
0x98
32
read-write
0
0xFFFFFFFF
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
ADC0
Analog-to-Digital Converter
ADC
ADC0_
0x4003B000
0
0x70
registers
ADC0
39
2
0x4
A,B
SC1%s
ADC Status and Control Registers 1
0
32
read-write
0x1F
0xFFFFFFFF
ADCH
Input channel select
0
5
read-write
00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00000
00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00001
00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00010
00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00011
00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00100
00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00101
00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00110
00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#00111
01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01000
01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01001
01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01010
01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01011
01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01100
01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01101
01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01110
01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#01111
10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10000
10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10001
10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10010
10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10011
10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10100
10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10101
10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10110
10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#10111
11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11010
11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11011
11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
DIFF
Differential Mode Enable
5
1
read-write
0
Single-ended conversions and input channels are selected.
#0
1
Differential conversions and input channels are selected.
#1
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
CFG1
ADC Configuration Register 1
0x8
32
read-write
0
0xFFFFFFFF
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
Alternate clock 2 (ALTCLK2)
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
MODE
Conversion mode selection
2
2
read-write
00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
#00
01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
#01
10
When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
#10
11
When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
#11
ADLSMP
Sample Time Configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
ADIV
Clock Divide Select
5
2
read-write
00
The divide ratio is 1 and the clock rate is input clock.
#00
01
The divide ratio is 2 and the clock rate is (input clock)/2.
#01
10
The divide ratio is 4 and the clock rate is (input clock)/4.
#10
11
The divide ratio is 8 and the clock rate is (input clock)/8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
Normal power configuration.
#0
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
#1
CFG2
ADC Configuration Register 2
0xC
32
read-write
0
0xFFFFFFFF
ADLSTS
Long Sample Time Select
0
2
read-write
00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#00
01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#01
10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#10
11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
#11
ADHSC
High-Speed Configuration
2
1
read-write
0
Normal conversion sequence selected.
#0
1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
#1
ADACKEN
Asynchronous Clock Output Enable
3
1
read-write
0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#0
1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
#1
MUXSEL
ADC Mux Select
4
1
read-write
0
ADxxa channels are selected.
#0
1
ADxxb channels are selected.
#1
2
0x4
A,B
R%s
ADC Data Result Register
0x10
32
read-only
0
0xFFFFFFFF
D
Data result
0
16
read-only
2
0x4
1,2
CV%s
Compare Value Registers
0x18
32
read-write
0
0xFFFFFFFF
CV
Compare Value.
0
16
read-write
SC2
Status and Control Register 2
0x20
32
read-write
0
0xFFFFFFFF
REFSEL
Voltage Reference Selection
0
2
read-write
00
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#00
01
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
#01
DMAEN
DMA Enable
2
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
#1
ACREN
Compare Function Range Enable
3
1
read-write
0
Range function disabled. Only CV1 is compared.
#0
1
Range function enabled. Both CV1 and CV2 are compared.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#0
1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
#1
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
SC3
Status and Control Register 3
0x24
32
read-write
0
0xFFFFFFFF
AVGS
Hardware Average Select
0
2
read-write
00
4 samples averaged.
#00
01
8 samples averaged.
#01
10
16 samples averaged.
#10
11
32 samples averaged.
#11
AVGE
Hardware Average Enable
2
1
read-write
0
Hardware average function disabled.
#0
1
Hardware average function enabled.
#1
ADCO
Continuous Conversion Enable
3
1
read-write
0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#0
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1
CALF
Calibration Failed Flag
6
1
read-write
0
Calibration completed normally.
#0
1
Calibration failed. ADC accuracy specifications are not guaranteed.
#1
CAL
Calibration
7
1
read-write
OFS
ADC Offset Correction Register
0x28
32
read-write
0x4
0xFFFFFFFF
OFS
Offset Error Correction Value
0
16
read-write
PG
ADC Plus-Side Gain Register
0x2C
32
read-write
0x8200
0xFFFFFFFF
PG
Plus-Side Gain
0
16
read-write
MG
ADC Minus-Side Gain Register
0x30
32
read-write
0x8200
0xFFFFFFFF
MG
Minus-Side Gain
0
16
read-write
CLPD
ADC Plus-Side General Calibration Value Register
0x34
32
read-write
0xA
0xFFFFFFFF
CLPD
Calibration Value
0
6
read-write
CLPS
ADC Plus-Side General Calibration Value Register
0x38
32
read-write
0x20
0xFFFFFFFF
CLPS
Calibration Value
0
6
read-write
CLP4
ADC Plus-Side General Calibration Value Register
0x3C
32
read-write
0x200
0xFFFFFFFF
CLP4
Calibration Value
0
10
read-write
CLP3
ADC Plus-Side General Calibration Value Register
0x40
32
read-write
0x100
0xFFFFFFFF
CLP3
Calibration Value
0
9
read-write
CLP2
ADC Plus-Side General Calibration Value Register
0x44
32
read-write
0x80
0xFFFFFFFF
CLP2
Calibration Value
0
8
read-write
CLP1
ADC Plus-Side General Calibration Value Register
0x48
32
read-write
0x40
0xFFFFFFFF
CLP1
Calibration Value
0
7
read-write
CLP0
ADC Plus-Side General Calibration Value Register
0x4C
32
read-write
0x20
0xFFFFFFFF
CLP0
Calibration Value
0
6
read-write
CLMD
ADC Minus-Side General Calibration Value Register
0x54
32
read-write
0xA
0xFFFFFFFF
CLMD
Calibration Value
0
6
read-write
CLMS
ADC Minus-Side General Calibration Value Register
0x58
32
read-write
0x20
0xFFFFFFFF
CLMS
Calibration Value
0
6
read-write
CLM4
ADC Minus-Side General Calibration Value Register
0x5C
32
read-write
0x200
0xFFFFFFFF
CLM4
Calibration Value
0
10
read-write
CLM3
ADC Minus-Side General Calibration Value Register
0x60
32
read-write
0x100
0xFFFFFFFF
CLM3
Calibration Value
0
9
read-write
CLM2
ADC Minus-Side General Calibration Value Register
0x64
32
read-write
0x80
0xFFFFFFFF
CLM2
Calibration Value
0
8
read-write
CLM1
ADC Minus-Side General Calibration Value Register
0x68
32
read-write
0x40
0xFFFFFFFF
CLM1
Calibration Value
0
7
read-write
CLM0
ADC Minus-Side General Calibration Value Register
0x6C
32
read-write
0x20
0xFFFFFFFF
CLM0
Calibration Value
0
6
read-write
ADC1
Analog-to-Digital Converter
ADC
ADC1_
0x400BB000
0
0x70
registers
ADC1
73
2
0x4
A,B
SC1%s
ADC Status and Control Registers 1
0
32
read-write
0x1F
0xFFFFFFFF
ADCH
Input channel select
0
5
read-write
00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00000
00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00001
00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00010
00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00011
00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00100
00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00101
00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00110
00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#00111
01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01000
01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01001
01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01010
01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01011
01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01100
01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01101
01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01110
01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#01111
10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10000
10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10001
10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10010
10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10011
10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10100
10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10101
10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10110
10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#10111
11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11010
11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11011
11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
DIFF
Differential Mode Enable
5
1
read-write
0
Single-ended conversions and input channels are selected.
#0
1
Differential conversions and input channels are selected.
#1
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
CFG1
ADC Configuration Register 1
0x8
32
read-write
0
0xFFFFFFFF
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
Alternate clock 2 (ALTCLK2)
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
MODE
Conversion mode selection
2
2
read-write
00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
#00
01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
#01
10
When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
#10
11
When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
#11
ADLSMP
Sample Time Configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
ADIV
Clock Divide Select
5
2
read-write
00
The divide ratio is 1 and the clock rate is input clock.
#00
01
The divide ratio is 2 and the clock rate is (input clock)/2.
#01
10
The divide ratio is 4 and the clock rate is (input clock)/4.
#10
11
The divide ratio is 8 and the clock rate is (input clock)/8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
Normal power configuration.
#0
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
#1
CFG2
ADC Configuration Register 2
0xC
32
read-write
0
0xFFFFFFFF
ADLSTS
Long Sample Time Select
0
2
read-write
00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#00
01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#01
10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#10
11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
#11
ADHSC
High-Speed Configuration
2
1
read-write
0
Normal conversion sequence selected.
#0
1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
#1
ADACKEN
Asynchronous Clock Output Enable
3
1
read-write
0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#0
1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
#1
MUXSEL
ADC Mux Select
4
1
read-write
0
ADxxa channels are selected.
#0
1
ADxxb channels are selected.
#1
2
0x4
A,B
R%s
ADC Data Result Register
0x10
32
read-only
0
0xFFFFFFFF
D
Data result
0
16
read-only
2
0x4
1,2
CV%s
Compare Value Registers
0x18
32
read-write
0
0xFFFFFFFF
CV
Compare Value.
0
16
read-write
SC2
Status and Control Register 2
0x20
32
read-write
0
0xFFFFFFFF
REFSEL
Voltage Reference Selection
0
2
read-write
00
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#00
01
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
#01
DMAEN
DMA Enable
2
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
#1
ACREN
Compare Function Range Enable
3
1
read-write
0
Range function disabled. Only CV1 is compared.
#0
1
Range function enabled. Both CV1 and CV2 are compared.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#0
1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
#1
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
SC3
Status and Control Register 3
0x24
32
read-write
0
0xFFFFFFFF
AVGS
Hardware Average Select
0
2
read-write
00
4 samples averaged.
#00
01
8 samples averaged.
#01
10
16 samples averaged.
#10
11
32 samples averaged.
#11
AVGE
Hardware Average Enable
2
1
read-write
0
Hardware average function disabled.
#0
1
Hardware average function enabled.
#1
ADCO
Continuous Conversion Enable
3
1
read-write
0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#0
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1
CALF
Calibration Failed Flag
6
1
read-write
0
Calibration completed normally.
#0
1
Calibration failed. ADC accuracy specifications are not guaranteed.
#1
CAL
Calibration
7
1
read-write
OFS
ADC Offset Correction Register
0x28
32
read-write
0x4
0xFFFFFFFF
OFS
Offset Error Correction Value
0
16
read-write
PG
ADC Plus-Side Gain Register
0x2C
32
read-write
0x8200
0xFFFFFFFF
PG
Plus-Side Gain
0
16
read-write
MG
ADC Minus-Side Gain Register
0x30
32
read-write
0x8200
0xFFFFFFFF
MG
Minus-Side Gain
0
16
read-write
CLPD
ADC Plus-Side General Calibration Value Register
0x34
32
read-write
0xA
0xFFFFFFFF
CLPD
Calibration Value
0
6
read-write
CLPS
ADC Plus-Side General Calibration Value Register
0x38
32
read-write
0x20
0xFFFFFFFF
CLPS
Calibration Value
0
6
read-write
CLP4
ADC Plus-Side General Calibration Value Register
0x3C
32
read-write
0x200
0xFFFFFFFF
CLP4
Calibration Value
0
10
read-write
CLP3
ADC Plus-Side General Calibration Value Register
0x40
32
read-write
0x100
0xFFFFFFFF
CLP3
Calibration Value
0
9
read-write
CLP2
ADC Plus-Side General Calibration Value Register
0x44
32
read-write
0x80
0xFFFFFFFF
CLP2
Calibration Value
0
8
read-write
CLP1
ADC Plus-Side General Calibration Value Register
0x48
32
read-write
0x40
0xFFFFFFFF
CLP1
Calibration Value
0
7
read-write
CLP0
ADC Plus-Side General Calibration Value Register
0x4C
32
read-write
0x20
0xFFFFFFFF
CLP0
Calibration Value
0
6
read-write
CLMD
ADC Minus-Side General Calibration Value Register
0x54
32
read-write
0xA
0xFFFFFFFF
CLMD
Calibration Value
0
6
read-write
CLMS
ADC Minus-Side General Calibration Value Register
0x58
32
read-write
0x20
0xFFFFFFFF
CLMS
Calibration Value
0
6
read-write
CLM4
ADC Minus-Side General Calibration Value Register
0x5C
32
read-write
0x200
0xFFFFFFFF
CLM4
Calibration Value
0
10
read-write
CLM3
ADC Minus-Side General Calibration Value Register
0x60
32
read-write
0x100
0xFFFFFFFF
CLM3
Calibration Value
0
9
read-write
CLM2
ADC Minus-Side General Calibration Value Register
0x64
32
read-write
0x80
0xFFFFFFFF
CLM2
Calibration Value
0
8
read-write
CLM1
ADC Minus-Side General Calibration Value Register
0x68
32
read-write
0x40
0xFFFFFFFF
CLM1
Calibration Value
0
7
read-write
CLM0
ADC Minus-Side General Calibration Value Register
0x6C
32
read-write
0x20
0xFFFFFFFF
CLM0
Calibration Value
0
6
read-write
RTC
Secure Real Time Clock
RTC_
0x4003D000
0
0x808
registers
RTC
46
RTC_Seconds
47
TSR
RTC Time Seconds Register
0
32
read-write
0
0xFFFFFFFF
TSR
Time Seconds Register
0
32
read-write
TPR
RTC Time Prescaler Register
0x4
32
read-write
0
0xFFFFFFFF
TPR
Time Prescaler Register
0
16
read-write
TAR
RTC Time Alarm Register
0x8
32
read-write
0
0xFFFFFFFF
TAR
Time Alarm Register
0
32
read-write
TCR
RTC Time Compensation Register
0xC
32
read-write
0
0xFFFFFFFF
TCR
Time Compensation Register
0
8
read-write
10000000
Time Prescaler Register overflows every 32896 clock cycles.
#10000000
11111111
Time Prescaler Register overflows every 32769 clock cycles.
#11111111
0
Time Prescaler Register overflows every 32768 clock cycles.
#0
1
Time Prescaler Register overflows every 32767 clock cycles.
#1
1111111
Time Prescaler Register overflows every 32641 clock cycles.
#1111111
CIR
Compensation Interval Register
8
8
read-write
TCV
Time Compensation Value
16
8
read-only
CIC
Compensation Interval Counter
24
8
read-only
CR
RTC Control Register
0x10
32
read-write
0
0xFFFFFFFF
SWR
Software Reset
0
1
read-write
0
No effect.
#0
1
Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
#1
WPE
Wakeup Pin Enable
1
1
read-write
0
Wakeup pin is disabled.
#0
1
Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
#1
SUP
Supervisor Access
2
1
read-write
0
Non-supervisor mode write accesses are not supported and generate a bus error.
#0
1
Non-supervisor mode write accesses are supported.
#1
UM
Update Mode
3
1
read-write
0
Registers cannot be written when locked.
#0
1
Registers can be written when locked under limited conditions.
#1
WPS
Wakeup Pin Select
4
1
read-write
0
Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
#0
1
Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
#1
OSCE
Oscillator Enable
8
1
read-write
0
32.768 kHz oscillator is disabled.
#0
1
32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
#1
CLKO
Clock Output
9
1
read-write
0
The 32 kHz clock is output to other peripherals.
#0
1
The 32 kHz clock is not output to other peripherals.
#1
SC16P
Oscillator 16pF Load Configure
10
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC8P
Oscillator 8pF Load Configure
11
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC4P
Oscillator 4pF Load Configure
12
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC2P
Oscillator 2pF Load Configure
13
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SR
RTC Status Register
0x14
32
read-write
0x1
0xFFFFFFFF
TIF
Time Invalid Flag
0
1
read-only
0
Time is valid.
#0
1
Time is invalid and time counter is read as zero.
#1
TOF
Time Overflow Flag
1
1
read-only
0
Time overflow has not occurred.
#0
1
Time overflow has occurred and time counter is read as zero.
#1
TAF
Time Alarm Flag
2
1
read-only
0
Time alarm has not occurred.
#0
1
Time alarm has occurred.
#1
TCE
Time Counter Enable
4
1
read-write
0
Time counter is disabled.
#0
1
Time counter is enabled.
#1
LR
RTC Lock Register
0x18
32
read-write
0xFF
0xFFFFFFFF
TCL
Time Compensation Lock
3
1
read-write
0
Time Compensation Register is locked and writes are ignored.
#0
1
Time Compensation Register is not locked and writes complete as normal.
#1
CRL
Control Register Lock
4
1
read-write
0
Control Register is locked and writes are ignored.
#0
1
Control Register is not locked and writes complete as normal.
#1
SRL
Status Register Lock
5
1
read-write
0
Status Register is locked and writes are ignored.
#0
1
Status Register is not locked and writes complete as normal.
#1
LRL
Lock Register Lock
6
1
read-write
0
Lock Register is locked and writes are ignored.
#0
1
Lock Register is not locked and writes complete as normal.
#1
IER
RTC Interrupt Enable Register
0x1C
32
read-write
0x7
0xFFFFFFFF
TIIE
Time Invalid Interrupt Enable
0
1
read-write
0
Time invalid flag does not generate an interrupt.
#0
1
Time invalid flag does generate an interrupt.
#1
TOIE
Time Overflow Interrupt Enable
1
1
read-write
0
Time overflow flag does not generate an interrupt.
#0
1
Time overflow flag does generate an interrupt.
#1
TAIE
Time Alarm Interrupt Enable
2
1
read-write
0
Time alarm flag does not generate an interrupt.
#0
1
Time alarm flag does generate an interrupt.
#1
TSIE
Time Seconds Interrupt Enable
4
1
read-write
0
Seconds interrupt is disabled.
#0
1
Seconds interrupt is enabled.
#1
WPON
Wakeup Pin On
7
1
read-write
0
No effect.
#0
1
If the wakeup pin is enabled, then the wakeup pin will assert.
#1
WAR
RTC Write Access Register
0x800
32
read-write
0xFF
0xFFFFFFFF
TSRW
Time Seconds Register Write
0
1
read-write
0
Writes to the Time Seconds Register are ignored.
#0
1
Writes to the Time Seconds Register complete as normal.
#1
TPRW
Time Prescaler Register Write
1
1
read-write
0
Writes to the Time Prescaler Register are ignored.
#0
1
Writes to the Time Prescaler Register complete as normal.
#1
TARW
Time Alarm Register Write
2
1
read-write
0
Writes to the Time Alarm Register are ignored.
#0
1
Writes to the Time Alarm Register complete as normal.
#1
TCRW
Time Compensation Register Write
3
1
read-write
0
Writes to the Time Compensation Register are ignored.
#0
1
Writes to the Time Compensation Register complete as normal.
#1
CRW
Control Register Write
4
1
read-write
0
Writes to the Control Register are ignored.
#0
1
Writes to the Control Register complete as normal.
#1
SRW
Status Register Write
5
1
read-write
0
Writes to the Status Register are ignored.
#0
1
Writes to the Status Register complete as normal.
#1
LRW
Lock Register Write
6
1
read-write
0
Writes to the Lock Register are ignored.
#0
1
Writes to the Lock Register complete as normal.
#1
IERW
Interrupt Enable Register Write
7
1
read-write
0
Writes to the Interupt Enable Register are ignored.
#0
1
Writes to the Interrupt Enable Register complete as normal.
#1
RAR
RTC Read Access Register
0x804
32
read-write
0xFF
0xFFFFFFFF
TSRR
Time Seconds Register Read
0
1
read-write
0
Reads to the Time Seconds Register are ignored.
#0
1
Reads to the Time Seconds Register complete as normal.
#1
TPRR
Time Prescaler Register Read
1
1
read-write
0
Reads to the Time Pprescaler Register are ignored.
#0
1
Reads to the Time Prescaler Register complete as normal.
#1
TARR
Time Alarm Register Read
2
1
read-write
0
Reads to the Time Alarm Register are ignored.
#0
1
Reads to the Time Alarm Register complete as normal.
#1
TCRR
Time Compensation Register Read
3
1
read-write
0
Reads to the Time Compensation Register are ignored.
#0
1
Reads to the Time Compensation Register complete as normal.
#1
CRR
Control Register Read
4
1
read-write
0
Reads to the Control Register are ignored.
#0
1
Reads to the Control Register complete as normal.
#1
SRR
Status Register Read
5
1
read-write
0
Reads to the Status Register are ignored.
#0
1
Reads to the Status Register complete as normal.
#1
LRR
Lock Register Read
6
1
read-write
0
Reads to the Lock Register are ignored.
#0
1
Reads to the Lock Register complete as normal.
#1
IERR
Interrupt Enable Register Read
7
1
read-write
0
Reads to the Interrupt Enable Register are ignored.
#0
1
Reads to the Interrupt Enable Register complete as normal.
#1
RFVBAT
VBAT register file
RFVBAT_
0x4003E000
0
0x20
registers
8
0x4
0,1,2,3,4,5,6,7
REG%s
VBAT register file register
0
32
read-write
0
0xFFFFFFFF
LL
Low lower byte
0
8
read-write
LH
Low higher byte
8
8
read-write
HL
High lower byte
16
8
read-write
HH
High higher byte
24
8
read-write
LPTMR0
Low Power Timer
LPTMR0_
0x40040000
0
0x10
registers
LPTMR0
58
CSR
Low Power Timer Control Status Register
0
32
read-write
0
0xFFFFFFFF
TEN
Timer Enable
0
1
read-write
0
LPTMR is disabled and internal logic is reset.
#0
1
LPTMR is enabled.
#1
TMS
Timer Mode Select
1
1
read-write
0
Time Counter mode.
#0
1
Pulse Counter mode.
#1
TFC
Timer Free-Running Counter
2
1
read-write
0
CNR is reset whenever TCF is set.
#0
1
CNR is reset on overflow.
#1
TPP
Timer Pin Polarity
3
1
read-write
0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
#0
1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
#1
TPS
Timer Pin Select
4
2
read-write
00
Pulse counter input 0 is selected.
#00
01
Pulse counter input 1 is selected.
#01
10
Pulse counter input 2 is selected.
#10
11
Pulse counter input 3 is selected.
#11
TIE
Timer Interrupt Enable
6
1
read-write
0
Timer interrupt disabled.
#0
1
Timer interrupt enabled.
#1
TCF
Timer Compare Flag
7
1
read-write
0
The value of CNR is not equal to CMR and increments.
#0
1
The value of CNR is equal to CMR and increments.
#1
PSR
Low Power Timer Prescale Register
0x4
32
read-write
0
0xFFFFFFFF
PCS
Prescaler Clock Select
0
2
read-write
00
Prescaler/glitch filter clock 0 selected.
#00
01
Prescaler/glitch filter clock 1 selected.
#01
10
Prescaler/glitch filter clock 2 selected.
#10
11
Prescaler/glitch filter clock 3 selected.
#11
PBYP
Prescaler Bypass
2
1
read-write
0
Prescaler/glitch filter is enabled.
#0
1
Prescaler/glitch filter is bypassed.
#1
PRESCALE
Prescale Value
3
4
read-write
0000
Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
#0000
0001
Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
#0001
0010
Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
#0010
0011
Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
#0011
0100
Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
#0100
0101
Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
#0101
0110
Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
#0110
0111
Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
#0111
1000
Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
#1000
1001
Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
#1001
1010
Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
#1010
1011
Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
#1011
1100
Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
#1100
1101
Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
#1101
1110
Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
#1110
1111
Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
#1111
CMR
Low Power Timer Compare Register
0x8
32
read-write
0
0xFFFFFFFF
COMPARE
Compare Value
0
16
read-write
CNR
Low Power Timer Counter Register
0xC
32
read-write
0
0xFFFFFFFF
COUNTER
Counter Value
0
16
read-write
RFSYS
System register file
RFSYS_
0x40041000
0
0x20
registers
8
0x4
0,1,2,3,4,5,6,7
REG%s
Register file register
0
32
read-write
0
0xFFFFFFFF
LL
Low lower byte
0
8
read-write
LH
Low higher byte
8
8
read-write
HL
High lower byte
16
8
read-write
HH
High higher byte
24
8
read-write
SIM
System Integration Module
SIM_
0x40047000
0
0x1064
registers
SOPT1
System Options Register 1
0
32
read-write
0x80000000
0xFFFF0FC0
RAMSIZE
RAM size
12
4
read-only
0001
8 KB
#0001
0011
16 KB
#0011
0100
24 KB
#0100
0101
32 KB
#0101
0110
48 KB
#0110
0111
64 KB
#0111
1000
96 KB
#1000
1001
128 KB
#1001
1011
256 KB
#1011
OSC32KSEL
32K oscillator clock select
18
2
read-write
00
System oscillator (OSC32KCLK)
#00
10
RTC 32.768kHz oscillator
#10
11
LPO 1 kHz
#11
USBVSTBY
USB voltage regulator in standby mode during VLPR and VLPW modes
29
1
read-write
0
USB voltage regulator not in standby during VLPR and VLPW modes.
#0
1
USB voltage regulator in standby during VLPR and VLPW modes.
#1
USBSSTBY
USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
30
1
read-write
0
USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
#0
1
USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
#1
USBREGEN
USB voltage regulator enable
31
1
read-write
0
USB voltage regulator is disabled.
#0
1
USB voltage regulator is enabled.
#1
SOPT1CFG
SOPT1 Configuration Register
0x4
32
read-write
0
0xFFFFFFFF
URWE
USB voltage regulator enable write enable
24
1
read-write
0
SOPT1 USBREGEN cannot be written.
#0
1
SOPT1 USBREGEN can be written.
#1
UVSWE
USB voltage regulator VLP standby write enable
25
1
read-write
0
SOPT1 USBVSTBY cannot be written.
#0
1
SOPT1 USBVSTBY can be written.
#1
USSWE
USB voltage regulator stop standby write enable
26
1
read-write
0
SOPT1 USBSSTBY cannot be written.
#0
1
SOPT1 USBSSTBY can be written.
#1
SOPT2
System Options Register 2
0x1004
32
read-write
0x1000
0xFFFFFFFF
RTCCLKOUTSEL
RTC clock out select
4
1
read-write
0
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
#0
1
RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
#1
CLKOUTSEL
CLKOUT select
5
3
read-write
000
FlexBus CLKOUT
#000
010
Flash clock
#010
011
LPO clock (1 kHz)
#011
100
MCGIRCLK
#100
101
RTC 32.768kHz clock
#101
110
OSCERCLK0
#110
111
IRC 48 MHz clock
#111
FBSL
FlexBus security level
8
2
read-write
00
All off-chip accesses (instruction and data) via the FlexBus are disallowed.
#00
01
All off-chip accesses (instruction and data) via the FlexBus are disallowed.
#01
10
Off-chip instruction accesses are disallowed. Data accesses are allowed.
#10
11
Off-chip instruction accesses and data accesses are allowed.
#11
PTD7PAD
PTD7 pad drive strength
11
1
read-write
0
Single-pad drive strength for PTD7.
#0
1
Double pad drive strength for PTD7.
#1
TRACECLKSEL
Debug trace clock select
12
1
read-write
0
MCGOUTCLK
#0
1
Core/system clock
#1
PLLFLLSEL
PLL/FLL clock select
16
2
read-write
00
MCGFLLCLK clock
#00
01
MCGPLLCLK clock
#01
11
IRC48 MHz clock
#11
USBSRC
USB clock source select
18
1
read-write
0
External bypass clock (USB_CLKIN).
#0
1
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
#1
RMIISRC
RMII clock source select
19
1
read-write
0
EXTAL clock
#0
1
External bypass clock (ENET_1588_CLKIN).
#1
TIMESRC
IEEE 1588 timestamp clock source select
20
2
read-write
00
Core/system clock.
#00
01
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
#01
10
OSCERCLK clock
#10
11
External bypass clock (ENET_1588_CLKIN).
#11
SDHCSRC
SDHC clock source select
28
2
read-write
00
Core/system clock.
#00
01
MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
#01
10
OSCERCLK clock
#10
11
External bypass clock (SDHC0_CLKIN)
#11
SOPT4
System Options Register 4
0x100C
32
read-write
0
0xFFFFFFFF
FTM0FLT0
FTM0 Fault 0 Select
0
1
read-write
0
FTM0_FLT0 pin
#0
1
CMP0 out
#1
FTM0FLT1
FTM0 Fault 1 Select
1
1
read-write
0
FTM0_FLT1 pin
#0
1
CMP1 out
#1
FTM0FLT2
FTM0 Fault 2 Select
2
1
read-write
0
FTM0_FLT2 pin
#0
1
CMP2 out
#1
FTM1FLT0
FTM1 Fault 0 Select
4
1
read-write
0
FTM1_FLT0 pin
#0
1
CMP0 out
#1
FTM2FLT0
FTM2 Fault 0 Select
8
1
read-write
0
FTM2_FLT0 pin
#0
1
CMP0 out
#1
FTM3FLT0
FTM3 Fault 0 Select
12
1
read-write
0
FTM3_FLT0 pin
#0
1
CMP0 out
#1
FTM1CH0SRC
FTM1 channel 0 input capture source select
18
2
read-write
00
FTM1_CH0 signal
#00
01
CMP0 output
#01
10
CMP1 output
#10
11
USB start of frame pulse
#11
FTM2CH0SRC
FTM2 channel 0 input capture source select
20
2
read-write
00
FTM2_CH0 signal
#00
01
CMP0 output
#01
10
CMP1 output
#10
FTM0CLKSEL
FlexTimer 0 External Clock Pin Select
24
1
read-write
0
FTM_CLK0 pin
#0
1
FTM_CLK1 pin
#1
FTM1CLKSEL
FTM1 External Clock Pin Select
25
1
read-write
0
FTM_CLK0 pin
#0
1
FTM_CLK1 pin
#1
FTM2CLKSEL
FlexTimer 2 External Clock Pin Select
26
1
read-write
0
FTM2 external clock driven by FTM_CLK0 pin.
#0
1
FTM2 external clock driven by FTM_CLK1 pin.
#1
FTM3CLKSEL
FlexTimer 3 External Clock Pin Select
27
1
read-write
0
FTM3 external clock driven by FTM_CLK0 pin.
#0
1
FTM3 external clock driven by FTM_CLK1 pin.
#1
FTM0TRG0SRC
FlexTimer 0 Hardware Trigger 0 Source Select
28
1
read-write
0
HSCMP0 output drives FTM0 hardware trigger 0
#0
1
FTM1 channel match drives FTM0 hardware trigger 0
#1
FTM0TRG1SRC
FlexTimer 0 Hardware Trigger 1 Source Select
29
1
read-write
0
PDB output trigger 1 drives FTM0 hardware trigger 1
#0
1
FTM2 channel match drives FTM0 hardware trigger 1
#1
FTM3TRG0SRC
FlexTimer 3 Hardware Trigger 0 Source Select
30
1
read-write
1
FTM1 channel match drives FTM3 hardware trigger 0
#1
FTM3TRG1SRC
FlexTimer 3 Hardware Trigger 1 Source Select
31
1
read-write
1
FTM2 channel match drives FTM3 hardware trigger 1
#1
SOPT5
System Options Register 5
0x1010
32
read-write
0
0xFFFFFFFF
UART0TXSRC
UART 0 transmit data source select
0
2
read-write
00
UART0_TX pin
#00
01
UART0_TX pin modulated with FTM1 channel 0 output
#01
10
UART0_TX pin modulated with FTM2 channel 0 output
#10
UART0RXSRC
UART 0 receive data source select
2
2
read-write
00
UART0_RX pin
#00
01
CMP0
#01
10
CMP1
#10
UART1TXSRC
UART 1 transmit data source select
4
2
read-write
00
UART1_TX pin
#00
01
UART1_TX pin modulated with FTM1 channel 0 output
#01
10
UART1_TX pin modulated with FTM2 channel 0 output
#10
UART1RXSRC
UART 1 receive data source select
6
2
read-write
00
UART1_RX pin
#00
01
CMP0
#01
10
CMP1
#10
SOPT7
System Options Register 7
0x1018
32
read-write
0
0xFFFFFFFF
ADC0TRGSEL
ADC0 trigger select
0
4
read-write
0000
PDB external trigger pin input (PDB0_EXTRG)
#0000
0001
High speed comparator 0 output
#0001
0010
High speed comparator 1 output
#0010
0011
High speed comparator 2 output
#0011
0100
PIT trigger 0
#0100
0101
PIT trigger 1
#0101
0110
PIT trigger 2
#0110
0111
PIT trigger 3
#0111
1000
FTM0 trigger
#1000
1001
FTM1 trigger
#1001
1010
FTM2 trigger
#1010
1011
FTM3 trigger
#1011
1100
RTC alarm
#1100
1101
RTC seconds
#1101
1110
Low-power timer (LPTMR) trigger
#1110
ADC0PRETRGSEL
ADC0 pretrigger select
4
1
read-write
0
Pre-trigger A
#0
1
Pre-trigger B
#1
ADC0ALTTRGEN
ADC0 alternate trigger enable
7
1
read-write
0
PDB trigger selected for ADC0.
#0
1
Alternate trigger selected for ADC0.
#1
ADC1TRGSEL
ADC1 trigger select
8
4
read-write
0000
PDB external trigger pin input (PDB0_EXTRG)
#0000
0001
High speed comparator 0 output
#0001
0010
High speed comparator 1 output
#0010
0011
High speed comparator 2 output
#0011
0100
PIT trigger 0
#0100
0101
PIT trigger 1
#0101
0110
PIT trigger 2
#0110
0111
PIT trigger 3
#0111
1000
FTM0 trigger
#1000
1001
FTM1 trigger
#1001
1010
FTM2 trigger
#1010
1011
FTM3 trigger
#1011
1100
RTC alarm
#1100
1101
RTC seconds
#1101
1110
Low-power timer (LPTMR) trigger
#1110
ADC1PRETRGSEL
ADC1 pre-trigger select
12
1
read-write
0
Pre-trigger A selected for ADC1.
#0
1
Pre-trigger B selected for ADC1.
#1
ADC1ALTTRGEN
ADC1 alternate trigger enable
15
1
read-write
0
PDB trigger selected for ADC1
#0
1
Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
#1
SDID
System Device Identification Register
0x1024
32
read-only
0x380
0xF0F80
PINID
Pincount identification
0
4
read-only
0010
32-pin
#0010
0100
48-pin
#0100
0101
64-pin
#0101
0110
80-pin
#0110
0111
81-pin or 121-pin
#0111
1000
100-pin
#1000
1001
121-pin
#1001
1010
144-pin
#1010
1011
Custom pinout (WLCSP)
#1011
1100
169-pin
#1100
1110
256-pin
#1110
FAMID
Kinetis family identification
4
3
read-only
000
K1x Family (without tamper)
#000
001
K2x Family (without tamper)
#001
010
K3x Family or K1x/K6x Family (with tamper)
#010
011
K4x Family or K2x Family (with tamper)
#011
100
K6x Family (without tamper)
#100
101
K7x Family
#101
DIEID
Device Die ID
7
5
read-only
REVID
Device revision number
12
4
read-only
SERIESID
Kinetis Series ID
20
4
read-only
0000
Kinetis K series
#0000
0001
Kinetis L series
#0001
0101
Kinetis W series
#0101
0110
Kinetis V series
#0110
SUBFAMID
Kinetis Sub-Family ID
24
4
read-only
0000
Kx0 Subfamily
#0000
0001
Kx1 Subfamily (tamper detect)
#0001
0010
Kx2 Subfamily
#0010
0011
Kx3 Subfamily (tamper detect)
#0011
0100
Kx4 Subfamily
#0100
0101
Kx5 Subfamily (tamper detect)
#0101
0110
Kx6 Subfamily
#0110
FAMILYID
Kinetis Family ID
28
4
read-only
0001
K1x Family
#0001
0010
K2x Family
#0010
0011
K3x Family
#0011
0100
K4x Family
#0100
0110
K6x Family
#0110
0111
K7x Family
#0111
SCGC1
System Clock Gating Control Register 1
0x1028
32
read-write
0
0xFFFFFFFF
I2C2
I2C2 Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART4
UART4 Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART5
UART5 Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC2
System Clock Gating Control Register 2
0x102C
32
read-write
0
0xFFFFFFFF
ENET
ENET Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DAC0
DAC0 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DAC1
DAC1 Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC3
System Clock Gating Control Register 3
0x1030
32
read-write
0
0xFFFFFFFF
RNGA
RNGA Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI2
SPI2 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SDHC
SDHC Clock Gate Control
17
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTM2
FTM2 Clock Gate Control
24
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTM3
FTM3 Clock Gate Control
25
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
ADC1
ADC1 Clock Gate Control
27
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC4
System Clock Gating Control Register 4
0x1034
32
read-write
0xF0100030
0xFFFFFFFF
EWM
EWM Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CMT
CMT Clock Gate Control
2
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C0
I2C0 Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C1
I2C1 Clock Gate Control
7
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART0
UART0 Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART1
UART1 Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART2
UART2 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART3
UART3 Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
USBOTG
USB Clock Gate Control
18
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CMP
Comparator Clock Gate Control
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
VREF
VREF Clock Gate Control
20
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC5
System Clock Gating Control Register 5
0x1038
32
read-write
0x40182
0xFFFFFFFF
LPTMR
Low Power Timer Access Control
0
1
read-write
0
Access disabled
#0
1
Access enabled
#1
PORTA
Port A Clock Gate Control
9
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTB
Port B Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTC
Port C Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTD
Port D Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTE
Port E Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC6
System Clock Gating Control Register 6
0x103C
32
read-write
0x40000001
0xFFFFFFFF
FTF
Flash Memory Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX
DMA Mux Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FLEXCAN0
FlexCAN0 Clock Gate Control
4
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RNGA
RNGA Clock Gate Control
9
1
read-write
SPI0
SPI0 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI1
SPI1 Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2S
I2S Clock Gate Control
15
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CRC
CRC Clock Gate Control
18
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
USBDCD
USB DCD Clock Gate Control
21
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PDB
PDB Clock Gate Control
22
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PIT
PIT Clock Gate Control
23
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTM0
FTM0 Clock Gate Control
24
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTM1
FTM1 Clock Gate Control
25
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTM2
FTM2 Clock Gate Control
26
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
ADC0
ADC0 Clock Gate Control
27
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RTC
RTC Access Control
29
1
read-write
0
Access and interrupts disabled
#0
1
Access and interrupts enabled
#1
DAC0
DAC0 Clock Gate Control
31
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC7
System Clock Gating Control Register 7
0x1040
32
read-write
0x6
0xFFFFFFFF
FLEXBUS
FlexBus Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMA
DMA Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
MPU
MPU Clock Gate Control
2
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CLKDIV1
System Clock Divider Register 1
0x1044
32
read-write
0x10000
0xFFFFFFFF
OUTDIV4
Clock 4 output divider value
16
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
OUTDIV3
Clock 3 output divider value
20
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
OUTDIV2
Clock 2 output divider value
24
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
OUTDIV1
Clock 1 output divider value
28
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
CLKDIV2
System Clock Divider Register 2
0x1048
32
read-write
0
0xFFFFFFFF
USBFRAC
USB clock divider fraction
0
1
read-write
USBDIV
USB clock divider divisor
1
3
read-write
FCFG1
Flash Configuration Register 1
0x104C
32
read-write
0xFF0F0F00
0xFFFFFFFF
FLASHDIS
Flash Disable
0
1
read-write
0
Flash is enabled
#0
1
Flash is disabled
#1
FLASHDOZE
Flash Doze
1
1
read-write
0
Flash remains enabled during Wait mode
#0
1
Flash is disabled for the duration of Wait mode
#1
DEPART
FlexNVM partition
8
4
read-only
EESIZE
EEPROM size
16
4
read-only
0000
16 KB
#0000
0001
8 KB
#0001
0010
4 KB
#0010
0011
2 KB
#0011
0100
1 KB
#0100
0101
512 Bytes
#0101
0110
256 Bytes
#0110
0111
128 Bytes
#0111
1000
64 Bytes
#1000
1001
32 Bytes
#1001
1111
0 Bytes
#1111
PFSIZE
Program flash size
24
4
read-only
0011
32 KB of program flash memory
#0011
0101
64 KB of program flash memory
#0101
0111
128 KB of program flash memory
#0111
1001
256 KB of program flash memory
#1001
1011
512 KB of program flash memory
#1011
1101
1024 KB of program flash memory
#1101
1111
1024 KB of program flash memory
#1111
NVMSIZE
FlexNVM size
28
4
read-only
0000
0 KB of FlexNVM
#0000
0011
32 KB of FlexNVM
#0011
0101
64 KB of FlexNVM
#0101
0111
128 KB of FlexNVM
#0111
1001
256 KB of FlexNVM
#1001
1011
512 KB of FlexNVM
#1011
1111
512 KB of FlexNVM
#1111
FCFG2
Flash Configuration Register 2
0x1050
32
read-only
0x7F7F0000
0xFFFFFFFF
MAXADDR1
Max address block 1
16
7
read-only
PFLSH
Program flash only
23
1
read-only
0
Device supports FlexNVM
#0
1
Program Flash only, device does not support FlexNVM
#1
MAXADDR0
Max address block 0
24
7
read-only
UIDH
Unique Identification Register High
0x1054
32
read-only
0
0xFFFFFFFF
UID
Unique Identification
0
32
read-only
UIDMH
Unique Identification Register Mid-High
0x1058
32
read-only
0
0xFFFFFFFF
UID
Unique Identification
0
32
read-only
UIDML
Unique Identification Register Mid Low
0x105C
32
read-only
0
0xFFFFFFFF
UID
Unique Identification
0
32
read-only
UIDL
Unique Identification Register Low
0x1060
32
read-only
0
0xFFFFFFFF
UID
Unique Identification
0
32
read-only
PORTA
Pin Control and Interrupts
PORT
PORTA_
0x40049000
0
0xA4
registers
PORTA
59
PCR0
Pin Control Register n
0
32
read-write
0x742
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR1
Pin Control Register n
0x4
32
read-write
0x743
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR2
Pin Control Register n
0x8
32
read-write
0x743
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR3
Pin Control Register n
0xC
32
read-write
0x743
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR4
Pin Control Register n
0x10
32
read-write
0x743
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR5
Pin Control Register n
0x14
32
read-write
0x41
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR6
Pin Control Register n
0x18
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR8
Pin Control Register n
0x20
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR9
Pin Control Register n
0x24
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR10
Pin Control Register n
0x28
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR12
Pin Control Register n
0x30
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR13
Pin Control Register n
0x34
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR14
Pin Control Register n
0x38
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR16
Pin Control Register n
0x40
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR17
Pin Control Register n
0x44
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR18
Pin Control Register n
0x48
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR20
Pin Control Register n
0x50
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR21
Pin Control Register n
0x54
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR22
Pin Control Register n
0x58
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR24
Pin Control Register n
0x60
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR25
Pin Control Register n
0x64
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR26
Pin Control Register n
0x68
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR28
Pin Control Register n
0x70
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR29
Pin Control Register n
0x74
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR30
Pin Control Register n
0x78
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCHR
Global Pin Control High Register
0x84
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
0
0xFFFFFFFF
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PORTB
Pin Control and Interrupts
PORT
PORTB_
0x4004A000
0
0xA4
registers
PORTB
60
PCR0
Pin Control Register n
0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR1
Pin Control Register n
0x4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR2
Pin Control Register n
0x8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR3
Pin Control Register n
0xC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR4
Pin Control Register n
0x10
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR5
Pin Control Register n
0x14
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR6
Pin Control Register n
0x18
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR8
Pin Control Register n
0x20
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR9
Pin Control Register n
0x24
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR10
Pin Control Register n
0x28
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR12
Pin Control Register n
0x30
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR13
Pin Control Register n
0x34
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR14
Pin Control Register n
0x38
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR16
Pin Control Register n
0x40
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR17
Pin Control Register n
0x44
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR18
Pin Control Register n
0x48
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR20
Pin Control Register n
0x50
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR21
Pin Control Register n
0x54
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR22
Pin Control Register n
0x58
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR24
Pin Control Register n
0x60
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR25
Pin Control Register n
0x64
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR26
Pin Control Register n
0x68
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR28
Pin Control Register n
0x70
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR29
Pin Control Register n
0x74
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR30
Pin Control Register n
0x78
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCHR
Global Pin Control High Register
0x84
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
0
0xFFFFFFFF
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PORTC
Pin Control and Interrupts
PORT
PORTC_
0x4004B000
0
0xA4
registers
PORTC
61
PCR0
Pin Control Register n
0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR1
Pin Control Register n
0x4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR2
Pin Control Register n
0x8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR3
Pin Control Register n
0xC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR4
Pin Control Register n
0x10
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR5
Pin Control Register n
0x14
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR6
Pin Control Register n
0x18
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR8
Pin Control Register n
0x20
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR9
Pin Control Register n
0x24
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR10
Pin Control Register n
0x28
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR12
Pin Control Register n
0x30
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR13
Pin Control Register n
0x34
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR14
Pin Control Register n
0x38
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR16
Pin Control Register n
0x40
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR17
Pin Control Register n
0x44
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR18
Pin Control Register n
0x48
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR20
Pin Control Register n
0x50
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR21
Pin Control Register n
0x54
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR22
Pin Control Register n
0x58
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR24
Pin Control Register n
0x60
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR25
Pin Control Register n
0x64
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR26
Pin Control Register n
0x68
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR28
Pin Control Register n
0x70
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR29
Pin Control Register n
0x74
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR30
Pin Control Register n
0x78
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCHR
Global Pin Control High Register
0x84
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
0
0xFFFFFFFF
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PORTD
Pin Control and Interrupts
PORT
PORTD_
0x4004C000
0
0xCC
registers
PORTD
62
PCR0
Pin Control Register n
0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR1
Pin Control Register n
0x4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR2
Pin Control Register n
0x8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR3
Pin Control Register n
0xC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR4
Pin Control Register n
0x10
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR5
Pin Control Register n
0x14
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR6
Pin Control Register n
0x18
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR8
Pin Control Register n
0x20
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR9
Pin Control Register n
0x24
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR10
Pin Control Register n
0x28
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR12
Pin Control Register n
0x30
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR13
Pin Control Register n
0x34
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR14
Pin Control Register n
0x38
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR16
Pin Control Register n
0x40
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR17
Pin Control Register n
0x44
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR18
Pin Control Register n
0x48
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR20
Pin Control Register n
0x50
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR21
Pin Control Register n
0x54
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR22
Pin Control Register n
0x58
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR24
Pin Control Register n
0x60
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR25
Pin Control Register n
0x64
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR26
Pin Control Register n
0x68
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR28
Pin Control Register n
0x70
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR29
Pin Control Register n
0x74
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR30
Pin Control Register n
0x78
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCHR
Global Pin Control High Register
0x84
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
0
0xFFFFFFFF
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
DFER
Digital Filter Enable Register
0xC0
32
read-write
0
0xFFFFFFFF
DFE
Digital Filter Enable
0
32
read-write
0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#0
1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
DFCR
Digital Filter Clock Register
0xC4
32
read-write
0
0xFFFFFFFF
CS
Clock Source
0
1
read-write
0
Digital filters are clocked by the bus clock.
#0
1
Digital filters are clocked by the 1 kHz LPO clock.
#1
DFWR
Digital Filter Width Register
0xC8
32
read-write
0
0xFFFFFFFF
FILT
Filter Length
0
5
read-write
PORTE
Pin Control and Interrupts
PORT
PORTE_
0x4004D000
0
0xA4
registers
PORTE
63
PCR0
Pin Control Register n
0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR1
Pin Control Register n
0x4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR2
Pin Control Register n
0x8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR3
Pin Control Register n
0xC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR4
Pin Control Register n
0x10
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR5
Pin Control Register n
0x14
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR6
Pin Control Register n
0x18
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR8
Pin Control Register n
0x20
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR9
Pin Control Register n
0x24
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR10
Pin Control Register n
0x28
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR12
Pin Control Register n
0x30
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR13
Pin Control Register n
0x34
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR14
Pin Control Register n
0x38
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR16
Pin Control Register n
0x40
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR17
Pin Control Register n
0x44
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR18
Pin Control Register n
0x48
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR20
Pin Control Register n
0x50
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR21
Pin Control Register n
0x54
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR22
Pin Control Register n
0x58
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR24
Pin Control Register n
0x60
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR25
Pin Control Register n
0x64
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR26
Pin Control Register n
0x68
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR28
Pin Control Register n
0x70
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-write
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR29
Pin Control Register n
0x74
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR30
Pin Control Register n
0x78
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
ODE
Open Drain Enable
5
1
read-only
0
Open drain output is disabled on the corresponding pin.
#0
1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
#1
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic 0.
#1000
1001
Interrupt on rising-edge.
#1001
1010
Interrupt on falling-edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCHR
Global Pin Control High Register
0x84
32
write-only
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
0
0xFFFFFFFF
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
WDOG
Generation 2008 Watchdog Timer
WDOG_
0x40052000
0
0x18
registers
WDOG_EWM
22
STCTRLH
Watchdog Status and Control Register High
0
16
read-write
0x1D3
0xFFFF
WDOGEN
Enables or disables the WDOG's operation
0
1
read-write
0
WDOG is disabled.
#0
1
WDOG is enabled.
#1
CLKSRC
Selects clock source for the WDOG timer and other internal timing operations.
1
1
read-write
0
WDOG clock sourced from LPO .
#0
1
WDOG clock sourced from alternate clock source.
#1
IRQRSTEN
Used to enable the debug breadcrumbs feature
2
1
read-write
0
WDOG time-out generates reset only.
#0
1
WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
#1
WINEN
Enables Windowing mode.
3
1
read-write
0
Windowing mode is disabled.
#0
1
Windowing mode is enabled.
#1
ALLOWUPDATE
Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence
4
1
read-write
0
No further updates allowed to WDOG write-once registers.
#0
1
WDOG write-once registers can be unlocked for updating.
#1
DBGEN
Enables or disables WDOG in Debug mode.
5
1
read-write
0
WDOG is disabled in CPU Debug mode.
#0
1
WDOG is enabled in CPU Debug mode.
#1
STOPEN
Enables or disables WDOG in Stop mode.
6
1
read-write
0
WDOG is disabled in CPU Stop mode.
#0
1
WDOG is enabled in CPU Stop mode.
#1
WAITEN
Enables or disables WDOG in Wait mode.
7
1
read-write
0
WDOG is disabled in CPU Wait mode.
#0
1
WDOG is enabled in CPU Wait mode.
#1
TESTWDOG
Puts the watchdog in the functional test mode
10
1
read-write
TESTSEL
Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer.
11
1
read-write
0
Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
#0
1
Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
#1
BYTESEL
This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode.
12
2
read-write
00
Byte 0 selected
#00
01
Byte 1 selected
#01
10
Byte 2 selected
#10
11
Byte 3 selected
#11
DISTESTWDOG
Allows the WDOG's functional test mode to be disabled permanently
14
1
read-write
0
WDOG functional test mode is not disabled.
#0
1
WDOG functional test mode is disabled permanently until reset.
#1
STCTRLL
Watchdog Status and Control Register Low
0x2
16
read-write
0x1
0xFFFF
INTFLG
Interrupt flag
15
1
read-write
TOVALH
Watchdog Time-out Value Register High
0x4
16
read-write
0x4C
0xFFFF
TOVALHIGH
Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer
0
16
read-write
TOVALL
Watchdog Time-out Value Register Low
0x6
16
read-write
0x4B4C
0xFFFF
TOVALLOW
Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer
0
16
read-write
WINH
Watchdog Window Register High
0x8
16
read-write
0
0xFFFF
WINHIGH
Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog
0
16
read-write
WINL
Watchdog Window Register Low
0xA
16
read-write
0x10
0xFFFF
WINLOW
Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog
0
16
read-write
REFRESH
Watchdog Refresh register
0xC
16
read-write
0xB480
0xFFFF
WDOGREFRESH
Watchdog refresh register
0
16
read-write
UNLOCK
Watchdog Unlock register
0xE
16
read-write
0xD928
0xFFFF
WDOGUNLOCK
Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again
0
16
read-write
TMROUTH
Watchdog Timer Output Register High
0x10
16
read-write
0
0xFFFF
TIMEROUTHIGH
Shows the value of the upper 16 bits of the watchdog timer.
0
16
read-write
TMROUTL
Watchdog Timer Output Register Low
0x12
16
read-write
0
0xFFFF
TIMEROUTLOW
Shows the value of the lower 16 bits of the watchdog timer.
0
16
read-write
RSTCNT
Watchdog Reset Count register
0x14
16
read-write
0
0xFFFF
RSTCNT
Counts the number of times the watchdog resets the system
0
16
read-write
PRESC
Watchdog Prescaler register
0x16
16
read-write
0x400
0xFFFF
PRESCVAL
3-bit prescaler for the watchdog clock source
8
3
read-write
EWM
External Watchdog Monitor
EWM_
0x40061000
0
0x4
registers
WDOG_EWM
22
CTRL
Control Register
0
8
read-write
0
0xFF
EWMEN
EWM enable.
0
1
read-write
ASSIN
EWM_in's Assertion State Select.
1
1
read-write
INEN
Input Enable.
2
1
read-write
INTEN
Interrupt Enable.
3
1
read-write
SERV
Service Register
0x1
8
write-only
0
0xFF
SERVICE
The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C
0
8
write-only
CMPL
Compare Low Register
0x2
8
read-write
0
0xFF
COMPAREL
To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required
0
8
read-write
CMPH
Compare High Register
0x3
8
read-write
0xFF
0xFF
COMPAREH
To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required
0
8
read-write
CMT
Carrier Modulator Transmitter
CMT_
0x40062000
0
0xC
registers
CMT
45
CGH1
CMT Carrier Generator High Data Register 1
0
8
read-write
0
0
PH
Primary Carrier High Time Data Value
0
8
read-write
CGL1
CMT Carrier Generator Low Data Register 1
0x1
8
read-write
0
0
PL
Primary Carrier Low Time Data Value
0
8
read-write
CGH2
CMT Carrier Generator High Data Register 2
0x2
8
read-write
0
0
SH
Secondary Carrier High Time Data Value
0
8
read-write
CGL2
CMT Carrier Generator Low Data Register 2
0x3
8
read-write
0
0
SL
Secondary Carrier Low Time Data Value
0
8
read-write
OC
CMT Output Control Register
0x4
8
read-write
0
0xFF
IROPEN
IRO Pin Enable
5
1
read-write
0
The IRO signal is disabled.
#0
1
The IRO signal is enabled as output.
#1
CMTPOL
CMT Output Polarity
6
1
read-write
0
The IRO signal is active-low.
#0
1
The IRO signal is active-high.
#1
IROL
IRO Latch Control
7
1
read-write
MSC
CMT Modulator Status and Control Register
0x5
8
read-write
0
0xFF
MCGEN
Modulator and Carrier Generator Enable
0
1
read-write
0
Modulator and carrier generator disabled
#0
1
Modulator and carrier generator enabled
#1
EOCIE
End of Cycle Interrupt Enable
1
1
read-write
0
CPU interrupt is disabled.
#0
1
CPU interrupt is enabled.
#1
FSK
FSK Mode Select
2
1
read-write
0
The CMT operates in Time or Baseband mode.
#0
1
The CMT operates in FSK mode.
#1
BASE
Baseband Enable
3
1
read-write
0
Baseband mode is disabled.
#0
1
Baseband mode is enabled.
#1
EXSPC
Extended Space Enable
4
1
read-write
0
Extended space is disabled.
#0
1
Extended space is enabled.
#1
CMTDIV
CMT Clock Divide Prescaler
5
2
read-write
00
IF * 1
#00
01
IF * 2
#01
10
IF * 4
#10
11
IF * 8
#11
EOCF
End Of Cycle Status Flag
7
1
read-only
0
End of modulation cycle has not occured since the flag last cleared.
#0
1
End of modulator cycle has occurred.
#1
CMD1
CMT Modulator Data Register Mark High
0x6
8
read-write
0
0
MB
Controls the upper mark periods of the modulator for all modes.
0
8
read-write
CMD2
CMT Modulator Data Register Mark Low
0x7
8
read-write
0
0
MB
Controls the lower mark periods of the modulator for all modes.
0
8
read-write
CMD3
CMT Modulator Data Register Space High
0x8
8
read-write
0
0
SB
Controls the upper space periods of the modulator for all modes.
0
8
read-write
CMD4
CMT Modulator Data Register Space Low
0x9
8
read-write
0
0
SB
Controls the lower space periods of the modulator for all modes.
0
8
read-write
PPS
CMT Primary Prescaler Register
0xA
8
read-write
0
0xFF
PPSDIV
Primary Prescaler Divider
0
4
read-write
0000
Bus clock * 1
#0000
0001
Bus clock * 2
#0001
0010
Bus clock * 3
#0010
0011
Bus clock * 4
#0011
0100
Bus clock * 5
#0100
0101
Bus clock * 6
#0101
0110
Bus clock * 7
#0110
0111
Bus clock * 8
#0111
1000
Bus clock * 9
#1000
1001
Bus clock * 10
#1001
1010
Bus clock * 11
#1010
1011
Bus clock * 12
#1011
1100
Bus clock * 13
#1100
1101
Bus clock * 14
#1101
1110
Bus clock * 15
#1110
1111
Bus clock * 16
#1111
DMA
CMT Direct Memory Access Register
0xB
8
read-write
0
0xFF
DMA
DMA Enable
0
1
read-write
0
DMA transfer request and done are disabled.
#0
1
DMA transfer request and done are enabled.
#1
MCG
Multipurpose Clock Generator module
MCG_
0x40064000
0
0xE
registers
C1
MCG Control 1 Register
0
8
read-write
0x4
0xFF
IREFSTEN
Internal Reference Stop Enable
0
1
read-write
0
Internal reference clock is disabled in Stop mode.
#0
1
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
#1
IRCLKEN
Internal Reference Clock Enable
1
1
read-write
0
MCGIRCLK inactive.
#0
1
MCGIRCLK active.
#1
IREFS
Internal Reference Select
2
1
read-write
0
External reference clock is selected.
#0
1
The slow internal reference clock is selected.
#1
FRDIV
FLL External Reference Divider
3
3
read-write
000
If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
#000
001
If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
#001
010
If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
#010
011
If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
#011
100
If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
#100
101
If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
#101
110
If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
#110
111
If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
#111
CLKS
Clock Source Select
6
2
read-write
00
Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Encoding 3 - Reserved.
#11
C2
MCG Control 2 Register
0x1
8
read-write
0x80
0xFF
IRCS
Internal Reference Clock Select
0
1
read-write
0
Slow internal reference clock selected.
#0
1
Fast internal reference clock selected.
#1
LP
Low Power Select
1
1
read-write
0
FLL or PLL is not disabled in bypass modes.
#0
1
FLL or PLL is disabled in bypass modes (lower power)
#1
EREFS
External Reference Select
2
1
read-write
0
External reference clock requested.
#0
1
Oscillator requested.
#1
HGO
High Gain Oscillator Select
3
1
read-write
0
Configure crystal oscillator for low-power operation.
#0
1
Configure crystal oscillator for high-gain operation.
#1
RANGE
Frequency Range Select
4
2
read-write
00
Encoding 0 - Low frequency range selected for the crystal oscillator .
#00
01
Encoding 1 - High frequency range selected for the crystal oscillator .
#01
1X
Encoding 2 - Very high frequency range selected for the crystal oscillator .
#1x
FCFTRIM
Fast Internal Reference Clock Fine Trim
6
1
read-write
LOCRE0
Loss of Clock Reset Enable
7
1
read-write
0
Interrupt request is generated on a loss of OSC0 external reference clock.
#0
1
Generate a reset request on a loss of OSC0 external reference clock.
#1
C3
MCG Control 3 Register
0x2
8
read-write
0
0
SCTRIM
Slow Internal Reference Clock Trim Setting
0
8
read-write
C4
MCG Control 4 Register
0x3
8
read-write
0
0xE0
SCFTRIM
Slow Internal Reference Clock Fine Trim
0
1
read-write
FCTRIM
Fast Internal Reference Clock Trim Setting
1
4
read-write
DRST_DRS
DCO Range Select
5
2
read-write
00
Encoding 0 - Low range (reset default).
#00
01
Encoding 1 - Mid range.
#01
10
Encoding 2 - Mid-high range.
#10
11
Encoding 3 - High range.
#11
DMX32
DCO Maximum Frequency with 32.768 kHz Reference
7
1
read-write
0
DCO has a default range of 25%.
#0
1
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
#1
C5
MCG Control 5 Register
0x4
8
read-write
0
0xFF
PRDIV0
PLL External Reference Divider
0
5
read-write
0
Divide Factor is 1
#00000
1
Divide Factor is 2
#00001
2
Divide Factor is 3
#00010
3
Divide Factor is 4
#00011
4
Divide Factor is 5
#00100
5
Divide Factor is 6
#00101
6
Divide Factor is 7
#00110
7
Divide Factor is 8
#00111
8
Divide Factor is 9
#01000
9
Divide Factor is 10
#01001
10
Divide Factor is 11
#01010
11
Divide Factor is 12
#01011
12
Divide Factor is 13
#01100
13
Divide Factor is 14
#01101
14
Divide Factor is 15
#01110
15
Divide Factor is 16
#01111
16
Divide Factor is 17
#10000
17
Divide Factor is 18
#10001
18
Divide Factor is 19
#10010
19
Divide Factor is 20
#10011
20
Divide Factor is 21
#10100
21
Divide Factor is 22
#10101
22
Divide Factor is 23
#10110
23
Divide Factor is 24
#10111
24
Divide Factor is 25
#11000
25
Divide Factor is 26
#11001
26
Divide Factor is 27
#11010
27
Divide Factor is 28
#11011
28
Divide Factor is 29
#11100
29
Divide Factor is 30
#11101
30
Divide Factor is 31
#11110
31
Divide Factor is 32
#11111
PLLSTEN0
PLL Stop Enable
5
1
read-write
0
MCGPLLCLK is disabled in any of the Stop modes.
#0
1
MCGPLLCLK is enabled if system is in Normal Stop mode.
#1
PLLCLKEN0
PLL Clock Enable
6
1
read-write
0
MCGPLLCLK is inactive.
#0
1
MCGPLLCLK is active.
#1
C6
MCG Control 6 Register
0x5
8
read-write
0
0xFF
VDIV0
VCO 0 Divider
0
5
read-write
0
Multiply Factor is 24
#00000
1
Multiply Factor is 25
#00001
2
Multiply Factor is 26
#00010
3
Multiply Factor is 27
#00011
4
Multiply Factor is 28
#00100
5
Multiply Factor is 29
#00101
6
Multiply Factor is 30
#00110
7
Multiply Factor is 31
#00111
8
Multiply Factor is 32
#01000
9
Multiply Factor is 33
#01001
10
Multiply Factor is 34
#01010
11
Multiply Factor is 35
#01011
12
Multiply Factor is 36
#01100
13
Multiply Factor is 37
#01101
14
Multiply Factor is 38
#01110
15
Multiply Factor is 39
#01111
16
Multiply Factor is 40
#10000
17
Multiply Factor is 41
#10001
18
Multiply Factor is 42
#10010
19
Multiply Factor is 43
#10011
20
Multiply Factor is 44
#10100
21
Multiply Factor is 45
#10101
22
Multiply Factor is 46
#10110
23
Multiply Factor is 47
#10111
24
Multiply Factor is 48
#11000
25
Multiply Factor is 49
#11001
26
Multiply Factor is 50
#11010
27
Multiply Factor is 51
#11011
28
Multiply Factor is 52
#11100
29
Multiply Factor is 53
#11101
30
Multiply Factor is 54
#11110
31
Multiply Factor is 55
#11111
CME0
Clock Monitor Enable
5
1
read-write
0
External clock monitor is disabled for OSC0.
#0
1
External clock monitor is enabled for OSC0.
#1
PLLS
PLL Select
6
1
read-write
0
FLL is selected.
#0
1
PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).
#1
LOLIE0
Loss of Lock Interrrupt Enable
7
1
read-write
0
No interrupt request is generated on loss of lock.
#0
1
Generate an interrupt request on loss of lock.
#1
S
MCG Status Register
0x6
8
read-write
0x10
0xFF
IRCST
Internal Reference Clock Status
0
1
read-only
0
Source of internal reference clock is the slow clock (32 kHz IRC).
#0
1
Source of internal reference clock is the fast clock (4 MHz IRC).
#1
OSCINIT0
OSC Initialization
1
1
read-only
CLKST
Clock Mode Status
2
2
read-only
00
Encoding 0 - Output of the FLL is selected (reset default).
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Encoding 3 - Output of the PLL is selected.
#11
IREFST
Internal Reference Status
4
1
read-only
0
Source of FLL reference clock is the external reference clock.
#0
1
Source of FLL reference clock is the internal reference clock.
#1
PLLST
PLL Select Status
5
1
read-only
0
Source of PLLS clock is FLL clock.
#0
1
Source of PLLS clock is PLL output clock.
#1
LOCK0
Lock Status
6
1
read-only
0
PLL is currently unlocked.
#0
1
PLL is currently locked.
#1
LOLS0
Loss of Lock Status
7
1
read-write
0
PLL has not lost lock since LOLS 0 was last cleared.
#0
1
PLL has lost lock since LOLS 0 was last cleared.
#1
SC
MCG Status and Control Register
0x8
8
read-write
0x2
0xFF
LOCS0
OSC0 Loss of Clock Status
0
1
read-write
0
Loss of OSC0 has not occurred.
#0
1
Loss of OSC0 has occurred.
#1
FCRDIV
Fast Clock Internal Reference Divider
1
3
read-write
000
Divide Factor is 1
#000
001
Divide Factor is 2.
#001
010
Divide Factor is 4.
#010
011
Divide Factor is 8.
#011
100
Divide Factor is 16
#100
101
Divide Factor is 32
#101
110
Divide Factor is 64
#110
111
Divide Factor is 128.
#111
FLTPRSRV
FLL Filter Preserve Enable
4
1
read-write
0
FLL filter and FLL frequency will reset on changes to currect clock mode.
#0
1
Fll filter and FLL frequency retain their previous values during new clock mode change.
#1
ATMF
Automatic Trim Machine Fail Flag
5
1
read-write
0
Automatic Trim Machine completed normally.
#0
1
Automatic Trim Machine failed.
#1
ATMS
Automatic Trim Machine Select
6
1
read-write
0
32 kHz Internal Reference Clock selected.
#0
1
4 MHz Internal Reference Clock selected.
#1
ATME
Automatic Trim Machine Enable
7
1
read-write
0
Auto Trim Machine disabled.
#0
1
Auto Trim Machine enabled.
#1
ATCVH
MCG Auto Trim Compare Value High Register
0xA
8
read-write
0
0xFF
ATCVH
ATM Compare Value High
0
8
read-write
ATCVL
MCG Auto Trim Compare Value Low Register
0xB
8
read-write
0
0xFF
ATCVL
ATM Compare Value Low
0
8
read-write
C7
MCG Control 7 Register
0xC
8
read-write
0
0xFF
OSCSEL
MCG OSC Clock Select
0
2
read-write
00
Selects Oscillator (OSCCLK0).
#00
01
Selects 32 kHz RTC Oscillator.
#01
10
Selects Oscillator (OSCCLK1).
#10
C8
MCG Control 8 Register
0xD
8
read-write
0x80
0xFF
LOCS1
RTC Loss of Clock Status
0
1
read-write
0
Loss of RTC has not occur.
#0
1
Loss of RTC has occur
#1
CME1
Clock Monitor Enable1
5
1
read-write
0
External clock monitor is disabled for RTC clock.
#0
1
External clock monitor is enabled for RTC clock.
#1
LOLRE
PLL Loss of Lock Reset Enable
6
1
read-write
0
Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
#0
1
Generate a reset request on a PLL loss of lock indication.
#1
LOCRE1
Loss of Clock Reset Enable
7
1
read-write
0
Interrupt request is generated on a loss of RTC external reference clock.
#0
1
Generate a reset request on a loss of RTC external reference clock
#1
OSC
Oscillator
OSC_
0x40065000
0
0x1
registers
CR
OSC Control Register
0
8
read-write
0
0xFF
SC16P
Oscillator 16 pF Capacitor Load Configure
0
1
read-write
0
Disable the selection.
#0
1
Add 16 pF capacitor to the oscillator load.
#1
SC8P
Oscillator 8 pF Capacitor Load Configure
1
1
read-write
0
Disable the selection.
#0
1
Add 8 pF capacitor to the oscillator load.
#1
SC4P
Oscillator 4 pF Capacitor Load Configure
2
1
read-write
0
Disable the selection.
#0
1
Add 4 pF capacitor to the oscillator load.
#1
SC2P
Oscillator 2 pF Capacitor Load Configure
3
1
read-write
0
Disable the selection.
#0
1
Add 2 pF capacitor to the oscillator load.
#1
EREFSTEN
External Reference Stop Enable
5
1
read-write
0
External reference clock is disabled in Stop mode.
#0
1
External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
#1
ERCLKEN
External Reference Enable
7
1
read-write
0
External reference clock is inactive.
#0
1
External reference clock is enabled.
#1
I2C0
Inter-Integrated Circuit
I2C
I2C0_
0x40066000
0
0xC
registers
I2C0
24
A1
I2C Address Register 1
0
8
read-write
0
0xFF
AD
Address
1
7
read-write
F
I2C Frequency Divider register
0x1
8
read-write
0
0xFF
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
C1
I2C Control Register 1
0x2
8
read-write
0
0xFF
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
RSTA
Repeat START
2
1
write-only
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
S
I2C Status register
0x3
8
read-write
0x80
0xFF
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
D
I2C Data I/O register
0x4
8
read-write
0
0xFF
DATA
Data
0
8
read-write
C2
I2C Control Register 2
0x5
8
read-write
0
0xFF
AD
Slave Address
0
3
read-write
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
FLT
I2C Programmable Input Glitch Filter register
0x6
8
read-write
0
0xFF
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0000
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
RA
I2C Range Address register
0x7
8
read-write
0
0xFF
RAD
Range Slave Address
1
7
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
0
0xFF
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
A2
I2C Address Register 2
0x9
8
read-write
0xC2
0xFF
SAD
SMBus Address
1
7
read-write
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
0
0xFF
SSLT
Most significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
0
0xFF
SSLT
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
I2C1
Inter-Integrated Circuit
I2C
I2C1_
0x40067000
0
0xC
registers
I2C1
25
A1
I2C Address Register 1
0
8
read-write
0
0xFF
AD
Address
1
7
read-write
F
I2C Frequency Divider register
0x1
8
read-write
0
0xFF
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
C1
I2C Control Register 1
0x2
8
read-write
0
0xFF
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
RSTA
Repeat START
2
1
write-only
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
S
I2C Status register
0x3
8
read-write
0x80
0xFF
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
D
I2C Data I/O register
0x4
8
read-write
0
0xFF
DATA
Data
0
8
read-write
C2
I2C Control Register 2
0x5
8
read-write
0
0xFF
AD
Slave Address
0
3
read-write
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
FLT
I2C Programmable Input Glitch Filter register
0x6
8
read-write
0
0xFF
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0000
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
RA
I2C Range Address register
0x7
8
read-write
0
0xFF
RAD
Range Slave Address
1
7
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
0
0xFF
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
A2
I2C Address Register 2
0x9
8
read-write
0xC2
0xFF
SAD
SMBus Address
1
7
read-write
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
0
0xFF
SSLT
Most significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
0
0xFF
SSLT
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
I2C2
Inter-Integrated Circuit
I2C
I2C2_
0x400E6000
0
0xC
registers
I2C2
74
A1
I2C Address Register 1
0
8
read-write
0
0xFF
AD
Address
1
7
read-write
F
I2C Frequency Divider register
0x1
8
read-write
0
0xFF
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
C1
I2C Control Register 1
0x2
8
read-write
0
0xFF
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
RSTA
Repeat START
2
1
write-only
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
S
I2C Status register
0x3
8
read-write
0x80
0xFF
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
D
I2C Data I/O register
0x4
8
read-write
0
0xFF
DATA
Data
0
8
read-write
C2
I2C Control Register 2
0x5
8
read-write
0
0xFF
AD
Slave Address
0
3
read-write
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
FLT
I2C Programmable Input Glitch Filter register
0x6
8
read-write
0
0xFF
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0000
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
RA
I2C Range Address register
0x7
8
read-write
0
0xFF
RAD
Range Slave Address
1
7
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
0
0xFF
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
A2
I2C Address Register 2
0x9
8
read-write
0xC2
0xFF
SAD
SMBus Address
1
7
read-write
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
0
0xFF
SSLT
Most significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
0
0xFF
SSLT
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
8
read-write
UART0
Serial Communication Interface
UART
UART0_
0x4006A000
0
0x20
registers
UART0_LON
30
UART0_RX_TX
31
UART0_ERR
32
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
C7816
UART 7816 Control Register
0x18
8
read-write
0
0xFF
ISO_7816E
ISO-7816 Functionality Enabled
0
1
read-write
0
ISO-7816 functionality is turned off/not enabled.
#0
1
ISO-7816 functionality is turned on/enabled.
#1
TTYPE
Transfer Type
1
1
read-write
0
T = 0 per the ISO-7816 specification.
#0
1
T = 1 per the ISO-7816 specification.
#1
INIT
Detect Initial Character
2
1
read-write
0
Normal operating mode. Receiver does not seek to identify initial character.
#0
1
Receiver searches for initial character.
#1
ANACK
Generate NACK on Error
3
1
read-write
0
No NACK is automatically generated.
#0
1
A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
#1
ONACK
Generate NACK on Overflow
4
1
read-write
0
The received data does not generate a NACK when the receipt of the data results in an overflow event.
#0
1
If the receiver buffer overflows, a NACK is automatically sent on a received character.
#1
IE7816
UART 7816 Interrupt Enable Register
0x19
8
read-write
0
0xFF
RXTE
Receive Threshold Exceeded Interrupt Enable
0
1
read-write
0
The assertion of IS7816[RXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[RXT] results in the generation of an interrupt.
#1
TXTE
Transmit Threshold Exceeded Interrupt Enable
1
1
read-write
0
The assertion of IS7816[TXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[TXT] results in the generation of an interrupt.
#1
GTVE
Guard Timer Violated Interrupt Enable
2
1
read-write
0
The assertion of IS7816[GTV] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[GTV] results in the generation of an interrupt.
#1
INITDE
Initial Character Detected Interrupt Enable
4
1
read-write
0
The assertion of IS7816[INITD] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[INITD] results in the generation of an interrupt.
#1
BWTE
Block Wait Timer Interrupt Enable
5
1
read-write
0
The assertion of IS7816[BWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[BWT] results in the generation of an interrupt.
#1
CWTE
Character Wait Timer Interrupt Enable
6
1
read-write
0
The assertion of IS7816[CWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[CWT] results in the generation of an interrupt.
#1
WTE
Wait Timer Interrupt Enable
7
1
read-write
0
The assertion of IS7816[WT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[WT] results in the generation of an interrupt.
#1
IS7816
UART 7816 Interrupt Status Register
0x1A
8
read-write
0
0xFF
RXT
Receive Threshold Exceeded Interrupt
0
1
read-write
0
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
#0
1
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
#1
TXT
Transmit Threshold Exceeded Interrupt
1
1
read-write
0
The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
#0
1
The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
#1
GTV
Guard Timer Violated Interrupt
2
1
read-write
0
A guard time (GT, CGT, or BGT) has not been violated.
#0
1
A guard time (GT, CGT, or BGT) has been violated.
#1
INITD
Initial Character Detected Interrupt
4
1
read-write
0
A valid initial character has not been received.
#0
1
A valid initial character has been received.
#1
BWT
Block Wait Timer Interrupt
5
1
read-write
0
Block wait time (BWT) has not been violated.
#0
1
Block wait time (BWT) has been violated.
#1
CWT
Character Wait Timer Interrupt
6
1
read-write
0
Character wait time (CWT) has not been violated.
#0
1
Character wait time (CWT) has been violated.
#1
WT
Wait Timer Interrupt
7
1
read-write
0
Wait time (WT) has not been violated.
#0
1
Wait time (WT) has been violated.
#1
WP7816T0
UART 7816 Wait Parameter Register
UART0
0x1B
8
read-write
0xA
0xFF
WI
Wait Time Integer (C7816[TTYPE] = 0)
0
8
read-write
WP7816T1
UART 7816 Wait Parameter Register
UART0
0x1B
8
read-write
0xA
0xFF
BWI
Block Wait Time Integer(C7816[TTYPE] = 1)
0
4
read-write
CWI
Character Wait Time Integer (C7816[TTYPE] = 1)
4
4
read-write
WN7816
UART 7816 Wait N Register
0x1C
8
read-write
0
0xFF
GTN
Guard Band N
0
8
read-write
WF7816
UART 7816 Wait FD Register
0x1D
8
read-write
0x1
0xFF
GTFD
FD Multiplier
0
8
read-write
ET7816
UART 7816 Error Threshold Register
0x1E
8
read-write
0
0xFF
RXTHRESHOLD
Receive NACK Threshold
0
4
read-write
TXTHRESHOLD
Transmit NACK Threshold
4
4
read-write
0
TXT asserts on the first NACK that is received.
#0000
1
TXT asserts on the second NACK that is received.
#0001
TL7816
UART 7816 Transmit Length Register
0x1F
8
read-write
0
0xFF
TLEN
Transmit Length
0
8
read-write
UART1
Serial Communication Interface
UART
UART1_
0x4006B000
0
0x17
registers
UART1_RX_TX
33
UART1_ERR
34
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
UART2
Serial Communication Interface
UART
UART2_
0x4006C000
0
0x17
registers
UART2_RX_TX
35
UART2_ERR
36
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
UART3
Serial Communication Interface
UART
UART3_
0x4006D000
0
0x17
registers
UART3_RX_TX
37
UART3_ERR
38
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
UART4
Serial Communication Interface
UART
UART4_
0x400EA000
0
0x17
registers
UART4_RX_TX
66
UART4_ERR
67
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
UART5
Serial Communication Interface
UART
UART5_
0x400EB000
0
0x17
registers
UART5_RX_TX
68
UART5_ERR
69
BDH
UART Baud Rate Registers: High
0
8
read-write
0
0xFF
SBR
UART Baud Rate Bits
0
5
read-write
SBNS
Stop Bit Number Select
5
1
read-write
0
Data frame consists of a single stop bit.
#0
1
Data frame consists of two stop bits.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
LBKDIE
LIN Break Detect Interrupt or DMA Request Enable
7
1
read-write
0
LBKDIF interrupt and DMA transfer requests disabled.
#0
1
LBKDIF interrupt or DMA transfer requests enabled.
#1
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
0x4
0xFF
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
0
0xFF
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clock continues to run in Wait mode.
#0
1
UART clock freezes while CPU is in Wait mode.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
C2
UART Control Register 2
0x3
8
read-write
0
0xFF
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
ILIE
Idle Line Interrupt DMA Transfer Enable
4
1
read-write
0
IDLE interrupt requests disabled. and DMA transfer
#0
1
IDLE interrupt requests enabled. or DMA transfer
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
TCIE
Transmission Complete Interrupt or DMA Transfer Enable
6
1
read-write
0
TC interrupt and DMA transfer requests disabled.
#0
1
TC interrupt or DMA transfer requests enabled.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
S1
UART Status Register 1
0x4
8
read-only
0xC0
0xFF
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
0
0xFF
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character detection is disabled.
#0
1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
#1
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character detected.
#0
1
LIN break character detected.
#1
C3
UART Control Register 3
0x6
8
read-write
0
0xFF
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
T8
Transmit Bit 8
6
1
read-write
R8
Received Bit 8
7
1
read-only
D
UART Data Register
0x7
8
read-write
0
0xFF
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
0
0xFF
MA
Match Address
0
8
read-write
C4
UART Control Register 4
0xA
8
read-write
0
0xFF
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
0
0xFF
LBKDDMAS
LIN Break Detect DMA Select Bit
3
1
read-write
0
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.
#0
1
If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.
#1
ILDMAS
Idle Line DMA Select
4
1
read-write
0
If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.
#1
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TCDMAS
Transmission Complete DMA Select
6
1
read-write
0
If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
ED
UART Extended Data Register
0xC
8
read-only
0
0xFF
PARITYE
The current received dataword contained in D and C3[R8] was received with a parity error.
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
NOISY
The current received dataword contained in D and C3[R8] was received with noise.
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
MODEM
UART Modem Register
0xD
8
read-write
0
0xFF
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
IR
UART Infrared Register
0xE
8
read-write
0
0xFF
TNP
Transmitter narrow pulse
0
2
read-write
00
3/16.
#00
01
1/16.
#01
10
1/32.
#10
11
1/4.
#11
IREN
Infrared enable
2
1
read-write
0
IR disabled.
#0
1
IR enabled.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
0
0xFF
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
0
0xFF
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
0xC0
0xFF
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
0
0xFF
TXWATER
Transmit Watermark
0
8
read-write
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
0
0xFF
TXCOUNT
Transmit Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
0x1
0xFF
RXWATER
Receive Watermark
0
8
read-write
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
0
0xFF
RXCOUNT
Receive Counter
0
8
read-only
USB0
Universal Serial Bus, OTG Capable Controller
USB0_
0x40072000
0
0x15D
registers
USB0
53
PERID
Peripheral ID register
0
8
read-only
0x4
0xFF
ID
Peripheral Identification
0
6
read-only
IDCOMP
Peripheral ID Complement register
0x4
8
read-only
0xFB
0xFF
NID
Ones' complement of PERID[ID]. bits.
0
6
read-only
REV
Peripheral Revision register
0x8
8
read-only
0x33
0xFF
REV
Revision
0
8
read-only
ADDINFO
Peripheral Additional Info register
0xC
8
read-only
0x1
0xFF
IEHOST
This bit is set if host mode is enabled.
0
1
read-only
IRQNUM
Assigned Interrupt Request Number
3
5
read-only
OTGISTAT
OTG Interrupt Status register
0x10
8
read-write
0
0xFF
AVBUSCHG
This bit is set when a change in VBUS is detected on an A device.
0
1
read-write
B_SESS_CHG
This bit is set when a change in VBUS is detected on a B device.
2
1
read-write
SESSVLDCHG
This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid
3
1
read-write
LINE_STATE_CHG
This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond, and the value of the line state is different from the last time when the line state was stable
5
1
read-write
ONEMSEC
This bit is set when the 1 millisecond timer expires
6
1
read-write
IDCHG
This bit is set when a change in the ID Signal from the USB connector is sensed.
7
1
read-write
OTGICR
OTG Interrupt Control register
0x14
8
read-write
0
0xFF
AVBUSEN
A VBUS Valid Interrupt Enable
0
1
read-write
0
Disables the AVBUSCHG interrupt.
#0
1
Enables the AVBUSCHG interrupt.
#1
BSESSEN
B Session END Interrupt Enable
2
1
read-write
0
Disables the B_SESS_CHG interrupt.
#0
1
Enables the B_SESS_CHG interrupt.
#1
SESSVLDEN
Session Valid Interrupt Enable
3
1
read-write
0
Disables the SESSVLDCHG interrupt.
#0
1
Enables the SESSVLDCHG interrupt.
#1
LINESTATEEN
Line State Change Interrupt Enable
5
1
read-write
0
Disables the LINE_STAT_CHG interrupt.
#0
1
Enables the LINE_STAT_CHG interrupt.
#1
ONEMSECEN
One Millisecond Interrupt Enable
6
1
read-write
0
Diables the 1ms timer interrupt.
#0
1
Enables the 1ms timer interrupt.
#1
IDEN
ID Interrupt Enable
7
1
read-write
0
The ID interrupt is disabled
#0
1
The ID interrupt is enabled
#1
OTGSTAT
OTG Status register
0x18
8
read-write
0
0xFF
AVBUSVLD
A VBUS Valid
0
1
read-write
0
The VBUS voltage is below the A VBUS Valid threshold.
#0
1
The VBUS voltage is above the A VBUS Valid threshold.
#1
BSESSEND
B Session End
2
1
read-write
0
The VBUS voltage is above the B session end threshold.
#0
1
The VBUS voltage is below the B session end threshold.
#1
SESS_VLD
Session Valid
3
1
read-write
0
The VBUS voltage is below the B session valid threshold
#0
1
The VBUS voltage is above the B session valid threshold.
#1
LINESTATESTABLE
Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond
5
1
read-write
0
The LINE_STAT_CHG bit is not yet stable.
#0
1
The LINE_STAT_CHG bit has been debounced and is stable.
#1
ONEMSECEN
This bit is reserved for the 1ms count, but it is not useful to software.
6
1
read-write
ID
Indicates the current state of the ID pin on the USB connector
7
1
read-write
0
Indicates a Type A cable is plugged into the USB connector.
#0
1
Indicates no cable is attached or a Type B cable is plugged into the USB connector.
#1
OTGCTL
OTG Control register
0x1C
8
read-write
0
0xFF
OTGEN
On-The-Go pullup/pulldown resistor enable
2
1
read-write
0
If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
#0
1
The pull-up and pull-down controls in this register are used.
#1
DMLOW
D- Data Line pull-down resistor enable
4
1
read-write
0
D- pulldown resistor is not enabled.
#0
1
D- pulldown resistor is enabled.
#1
DPLOW
D+ Data Line pull-down resistor enable
5
1
read-write
0
D+ pulldown resistor is not enabled.
#0
1
D+ pulldown resistor is enabled.
#1
DPHIGH
D+ Data Line pullup resistor enable
7
1
read-write
0
D+ pullup resistor is not enabled
#0
1
D+ pullup resistor is enabled
#1
ISTAT
Interrupt Status register
0x80
8
read-write
0
0xFF
USBRST
This bit is set when the USB Module has decoded a valid USB reset
0
1
read-write
ERROR
This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur
1
1
read-write
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token
2
1
read-write
TOKDNE
This bit is set when the current token being processed has completed
3
1
read-write
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms
4
1
read-write
RESUME
This bit is set when a K-state is observed on the DP/DM signals for 2
5
1
read-write
ATTACH
Attach Interrupt
6
1
read-write
STALL
Stall Interrupt
7
1
read-write
INTEN
Interrupt Enable register
0x84
8
read-write
0
0xFF
USBRSTEN
USBRST Interrupt Enable
0
1
read-write
0
Disables the USBRST interrupt.
#0
1
Enables the USBRST interrupt.
#1
ERROREN
ERROR Interrupt Enable
1
1
read-write
0
Disables the ERROR interrupt.
#0
1
Enables the ERROR interrupt.
#1
SOFTOKEN
SOFTOK Interrupt Enable
2
1
read-write
0
Disbles the SOFTOK interrupt.
#0
1
Enables the SOFTOK interrupt.
#1
TOKDNEEN
TOKDNE Interrupt Enable
3
1
read-write
0
Disables the TOKDNE interrupt.
#0
1
Enables the TOKDNE interrupt.
#1
SLEEPEN
SLEEP Interrupt Enable
4
1
read-write
0
Disables the SLEEP interrupt.
#0
1
Enables the SLEEP interrupt.
#1
RESUMEEN
RESUME Interrupt Enable
5
1
read-write
0
Disables the RESUME interrupt.
#0
1
Enables the RESUME interrupt.
#1
ATTACHEN
ATTACH Interrupt Enable
6
1
read-write
0
Disables the ATTACH interrupt.
#0
1
Enables the ATTACH interrupt.
#1
STALLEN
STALL Interrupt Enable
7
1
read-write
0
Diasbles the STALL interrupt.
#0
1
Enables the STALL interrupt.
#1
ERRSTAT
Error Interrupt Status register
0x88
8
read-write
0
0xFF
PIDERR
This bit is set when the PID check field fails.
0
1
read-write
CRC5EOF
This error interrupt has two functions
1
1
read-write
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
2
1
read-write
DFN8
This bit is set if the data field received was not 8 bits in length
3
1
read-write
BTOERR
This bit is set when a bus turnaround timeout error occurs
4
1
read-write
DMAERR
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data
5
1
read-write
BTSERR
This bit is set when a bit stuff error is detected
7
1
read-write
ERREN
Error Interrupt Enable register
0x8C
8
read-write
0
0xFF
PIDERREN
PIDERR Interrupt Enable
0
1
read-write
0
Disables the PIDERR interrupt.
#0
1
Enters the PIDERR interrupt.
#1
CRC5EOFEN
CRC5/EOF Interrupt Enable
1
1
read-write
0
Disables the CRC5/EOF interrupt.
#0
1
Enables the CRC5/EOF interrupt.
#1
CRC16EN
CRC16 Interrupt Enable
2
1
read-write
0
Disables the CRC16 interrupt.
#0
1
Enables the CRC16 interrupt.
#1
DFN8EN
DFN8 Interrupt Enable
3
1
read-write
0
Disables the DFN8 interrupt.
#0
1
Enables the DFN8 interrupt.
#1
BTOERREN
BTOERR Interrupt Enable
4
1
read-write
0
Disables the BTOERR interrupt.
#0
1
Enables the BTOERR interrupt.
#1
DMAERREN
DMAERR Interrupt Enable
5
1
read-write
0
Disables the DMAERR interrupt.
#0
1
Enables the DMAERR interrupt.
#1
BTSERREN
BTSERR Interrupt Enable
7
1
read-write
0
Disables the BTSERR interrupt.
#0
1
Enables the BTSERR interrupt.
#1
STAT
Status register
0x90
8
read-only
0
0xFF
ODD
This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
2
1
read-only
TX
Transmit Indicator
3
1
read-only
0
The most recent transaction was a receive operation.
#0
1
The most recent transaction was a transmit operation.
#1
ENDP
This four-bit field encodes the endpoint address that received or transmitted the previous token
4
4
read-only
CTL
Control register
0x94
8
read-write
0
0xFF
USBENSOFEN
USB Enable
0
1
read-write
0
Disables the USB Module.
#0
1
Enables the USB Module.
#1
ODDRST
Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank
1
1
read-write
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling
2
1
read-write
HOSTMODEEN
When set to 1, this bit enables the USB Module to operate in Host mode
3
1
read-write
RESET
Setting this bit enables the USB Module to generate USB reset signaling
4
1
read-write
TXSUSPENDTOKENBUSY
In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token
5
1
read-write
SE0
Live USB Single Ended Zero signal
6
1
read-write
JSTATE
Live USB differential receiver JSTATE signal
7
1
read-write
ADDR
Address register
0x98
8
read-write
0
0xFF
ADDR
USB Address
0
7
read-write
LSEN
Low Speed Enable bit
7
1
read-write
BDTPAGE1
BDT Page register 1
0x9C
8
read-write
0
0xFF
BDTBA
Provides address bits 15 through 9 of the BDT base address.
1
7
read-write
FRMNUML
Frame Number register Low
0xA0
8
read-write
0
0xFF
FRM
This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
0
8
read-write
FRMNUMH
Frame Number register High
0xA4
8
read-write
0
0xFF
FRM
This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
0
3
read-write
TOKEN
Token register
0xA8
8
read-write
0
0xFF
TOKENENDPT
Holds the Endpoint address for the token command
0
4
read-write
TOKENPID
Contains the token type executed by the USB module.
4
4
read-write
0001
OUT Token. USB Module performs an OUT (TX) transaction.
#0001
1001
IN Token. USB Module performs an In (RX) transaction.
#1001
1101
SETUP Token. USB Module performs a SETUP (TX) transaction
#1101
SOFTHLD
SOF Threshold register
0xAC
8
read-write
0
0xFF
CNT
Represents the SOF count threshold in byte times.
0
8
read-write
BDTPAGE2
BDT Page Register 2
0xB0
8
read-write
0
0xFF
BDTBA
Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
0
8
read-write
BDTPAGE3
BDT Page Register 3
0xB4
8
read-write
0
0xFF
BDTBA
Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
0
8
read-write
16
0x4
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
ENDPT%s
Endpoint Control register
0xC0
8
read-write
0
0xFF
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPSTALL
When set this bit indicates that the endpoint is called
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers.
2
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers.
3
1
read-write
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
RETRYDIS
This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
6
1
read-write
HOSTWOHUB
This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
7
1
read-write
USBCTRL
USB Control register
0x100
8
read-write
0xC0
0xFF
PDE
Enables the weak pulldowns on the USB transceiver.
6
1
read-write
0
Weak pulldowns are disabled on D+ and D-.
#0
1
Weak pulldowns are enabled on D+ and D-.
#1
SUSP
Places the USB transceiver into the suspend state.
7
1
read-write
0
USB transceiver is not in suspend state.
#0
1
USB transceiver is in suspend state.
#1
OBSERVE
USB OTG Observe register
0x104
8
read-only
0x50
0xFF
DMPD
Provides observability of the D- Pulldown enable at the USB transceiver.
4
1
read-only
0
D- pulldown disabled.
#0
1
D- pulldown enabled.
#1
DPPD
Provides observability of the D+ Pulldown enable at the USB transceiver.
6
1
read-only
0
D+ pulldown disabled.
#0
1
D+ pulldown enabled.
#1
DPPU
Provides observability of the D+ Pullup enable at the USB transceiver.
7
1
read-only
0
D+ pullup disabled.
#0
1
D+ pullup enabled.
#1
CONTROL
USB OTG Control register
0x108
8
read-write
0
0xFF
DPPULLUPNONOTG
Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG device mode.
4
1
read-write
0
DP Pullup in non-OTG device mode is not enabled.
#0
1
DP Pullup in non-OTG device mode is enabled.
#1
USBTRC0
USB Transceiver Control register 0
0x10C
8
read-write
0
0xFF
USB_RESUME_INT
USB Asynchronous Interrupt
0
1
read-only
0
No interrupt was generated.
#0
1
Interrupt was generated because of the USB asynchronous interrupt.
#1
SYNC_DET
Synchronous USB Interrupt Detect
1
1
read-only
0
Synchronous interrupt has not been detected.
#0
1
Synchronous interrupt has been detected.
#1
USB_CLK_RECOVERY_INT
Combined USB Clock Recovery interrupt status
2
1
read-only
USBRESMEN
Asynchronous Resume Interrupt Enable
5
1
read-write
0
USB asynchronous wakeup from suspend mode disabled.
#0
1
USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
#1
USBRESET
USB Reset
7
1
write-only
0
Normal USB module operation.
#0
1
Returns the USB module to its reset state.
#1
USBFRMADJUST
Frame Adjust Register
0x114
8
read-write
0
0xFF
ADJ
Frame Adjustment
0
8
read-write
CLK_RECOVER_CTRL
USB Clock recovery control
0x140
8
read-write
0
0xFF
RESTART_IFRTRIM_EN
Restart from IFR trim value
5
1
read-write
0
Trim fine adjustment always works based on the previous updated trim fine value (default)
#0
1
Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
#1
RESET_RESUME_ROUGH_EN
Reset/resume to rough phase enable
6
1
read-write
0
Always works in tracking phase after the 1st time rough to track transition (default)
#0
1
Go back to rough stage whenever bus reset or bus resume occurs
#1
CLOCK_RECOVER_EN
Crystal-less USB enable
7
1
read-write
0
Disable clock recovery block (default)
#0
1
Enable clock recovery block
#1
CLK_RECOVER_IRC_EN
IRC48M oscillator enable register
0x144
8
read-write
0x1
0xFF
REG_EN
IRC48M regulator enable
0
1
read-write
0
IRC48M local regulator is disabled
#0
1
IRC48M local regulator is enabled (default)
#1
IRC_EN
IRC48M enable
1
1
read-write
0
Disable the IRC48M module (default)
#0
1
Enable the IRC48M module
#1
CLK_RECOVER_INT_STATUS
Clock recovery separated interrupt status
0x15C
8
read-write
0
0xFF
OVF_ERROR
Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module
4
1
read-write
0
No interrupt is reported
#0
1
Unmasked interrupt has been generated
#1
CMP0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP
CMP0_
0x40073000
0
0x6
registers
CMP0
40
CR0
CMP Control Register 0
0
8
read-write
0
0xFF
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
CR1
CMP Control Register 1
0x1
8
read-write
0
0xFF
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
#0
1
CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
#1
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
0
0xFF
FILT_PER
Filter Sample Period
0
8
read-write
SCR
CMP Status and Control Register
0x3
8
read-write
0
0xFF
COUT
Analog Comparator Output
0
1
read-only
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
DACCR
DAC Control Register
0x4
8
read-write
0
0xFF
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
V is selected as resistor ladder network supply reference V. in1 in
#0
1
V is selected as resistor ladder network supply reference V. in2 in
#1
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
MUXCR
MUX Control Register
0x5
8
read-write
0
0xFF
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSTM
Pass Through Mode Enable
7
1
read-write
0
Pass Through Mode is disabled.
#0
1
Pass Through Mode is enabled.
#1
CMP1
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP
CMP1_
0x40073008
0
0x6
registers
CMP1
41
CR0
CMP Control Register 0
0
8
read-write
0
0xFF
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
CR1
CMP Control Register 1
0x1
8
read-write
0
0xFF
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
#0
1
CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
#1
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
0
0xFF
FILT_PER
Filter Sample Period
0
8
read-write
SCR
CMP Status and Control Register
0x3
8
read-write
0
0xFF
COUT
Analog Comparator Output
0
1
read-only
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
DACCR
DAC Control Register
0x4
8
read-write
0
0xFF
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
V is selected as resistor ladder network supply reference V. in1 in
#0
1
V is selected as resistor ladder network supply reference V. in2 in
#1
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
MUXCR
MUX Control Register
0x5
8
read-write
0
0xFF
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSTM
Pass Through Mode Enable
7
1
read-write
0
Pass Through Mode is disabled.
#0
1
Pass Through Mode is enabled.
#1
CMP2
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP
CMP2_
0x40073010
0
0x6
registers
CMP2
70
CR0
CMP Control Register 0
0
8
read-write
0
0xFF
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
CR1
CMP Control Register 1
0x1
8
read-write
0
0xFF
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
#0
1
CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
#1
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
0
0xFF
FILT_PER
Filter Sample Period
0
8
read-write
SCR
CMP Status and Control Register
0x3
8
read-write
0
0xFF
COUT
Analog Comparator Output
0
1
read-only
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
DACCR
DAC Control Register
0x4
8
read-write
0
0xFF
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
V is selected as resistor ladder network supply reference V. in1 in
#0
1
V is selected as resistor ladder network supply reference V. in2 in
#1
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
MUXCR
MUX Control Register
0x5
8
read-write
0
0xFF
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSTM
Pass Through Mode Enable
7
1
read-write
0
Pass Through Mode is disabled.
#0
1
Pass Through Mode is enabled.
#1
VREF
Voltage Reference
VREF_
0x40074000
0
0x2
registers
TRM
VREF Trim Register
0
8
read-write
0
0x40
TRIM
Trim bits
0
6
read-write
000000
Min
#0
111111
Max
#111111
CHOPEN
Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
6
1
read-write
0
Chop oscillator is disabled.
#0
1
Chop oscillator is enabled.
#1
SC
VREF Status and Control Register
0x1
8
read-write
0
0xFF
MODE_LV
Buffer Mode selection
0
2
read-write
00
Bandgap on only, for stabilization and startup
#00
01
High power buffer mode enabled
#01
10
Low-power buffer mode enabled
#10
VREFST
Internal Voltage Reference stable
2
1
read-only
0
The module is disabled or not stable.
#0
1
The module is stable.
#1
ICOMPEN
Second order curvature compensation enable
5
1
read-write
0
Disabled
#0
1
Enabled
#1
REGEN
Regulator enable
6
1
read-write
0
Internal 1.75 V regulator is disabled.
#0
1
Internal 1.75 V regulator is enabled.
#1
VREFEN
Internal Voltage Reference enable
7
1
read-write
0
The module is disabled.
#0
1
The module is enabled.
#1
LLWU
Low leakage wakeup unit
LLWU_
0x4007C000
0
0xB
registers
LLWU
21
PE1
LLWU Pin Enable 1 register
0
8
read-write
0
0xFF
WUPE0
Wakeup Pin Enable For LLWU_P0
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE1
Wakeup Pin Enable For LLWU_P1
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE2
Wakeup Pin Enable For LLWU_P2
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE3
Wakeup Pin Enable For LLWU_P3
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE2
LLWU Pin Enable 2 register
0x1
8
read-write
0
0xFF
WUPE4
Wakeup Pin Enable For LLWU_P4
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE5
Wakeup Pin Enable For LLWU_P5
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE6
Wakeup Pin Enable For LLWU_P6
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE7
Wakeup Pin Enable For LLWU_P7
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE3
LLWU Pin Enable 3 register
0x2
8
read-write
0
0xFF
WUPE8
Wakeup Pin Enable For LLWU_P8
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE9
Wakeup Pin Enable For LLWU_P9
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE10
Wakeup Pin Enable For LLWU_P10
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE11
Wakeup Pin Enable For LLWU_P11
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE4
LLWU Pin Enable 4 register
0x3
8
read-write
0
0xFF
WUPE12
Wakeup Pin Enable For LLWU_P12
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE13
Wakeup Pin Enable For LLWU_P13
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE14
Wakeup Pin Enable For LLWU_P14
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE15
Wakeup Pin Enable For LLWU_P15
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
ME
LLWU Module Enable register
0x4
8
read-write
0
0xFF
WUME0
Wakeup Module Enable For Module 0
0
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME1
Wakeup Module Enable for Module 1
1
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME2
Wakeup Module Enable For Module 2
2
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME3
Wakeup Module Enable For Module 3
3
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME4
Wakeup Module Enable For Module 4
4
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME5
Wakeup Module Enable For Module 5
5
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME6
Wakeup Module Enable For Module 6
6
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME7
Wakeup Module Enable For Module 7
7
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
F1
LLWU Flag 1 register
0x5
8
read-write
0
0xFF
WUF0
Wakeup Flag For LLWU_P0
0
1
read-write
0
LLWU_P0 input was not a wakeup source
#0
1
LLWU_P0 input was a wakeup source
#1
WUF1
Wakeup Flag For LLWU_P1
1
1
read-write
0
LLWU_P1 input was not a wakeup source
#0
1
LLWU_P1 input was a wakeup source
#1
WUF2
Wakeup Flag For LLWU_P2
2
1
read-write
0
LLWU_P2 input was not a wakeup source
#0
1
LLWU_P2 input was a wakeup source
#1
WUF3
Wakeup Flag For LLWU_P3
3
1
read-write
0
LLWU_P3 input was not a wake-up source
#0
1
LLWU_P3 input was a wake-up source
#1
WUF4
Wakeup Flag For LLWU_P4
4
1
read-write
0
LLWU_P4 input was not a wakeup source
#0
1
LLWU_P4 input was a wakeup source
#1
WUF5
Wakeup Flag For LLWU_P5
5
1
read-write
0
LLWU_P5 input was not a wakeup source
#0
1
LLWU_P5 input was a wakeup source
#1
WUF6
Wakeup Flag For LLWU_P6
6
1
read-write
0
LLWU_P6 input was not a wakeup source
#0
1
LLWU_P6 input was a wakeup source
#1
WUF7
Wakeup Flag For LLWU_P7
7
1
read-write
0
LLWU_P7 input was not a wakeup source
#0
1
LLWU_P7 input was a wakeup source
#1
F2
LLWU Flag 2 register
0x6
8
read-write
0
0xFF
WUF8
Wakeup Flag For LLWU_P8
0
1
read-write
0
LLWU_P8 input was not a wakeup source
#0
1
LLWU_P8 input was a wakeup source
#1
WUF9
Wakeup Flag For LLWU_P9
1
1
read-write
0
LLWU_P9 input was not a wakeup source
#0
1
LLWU_P9 input was a wakeup source
#1
WUF10
Wakeup Flag For LLWU_P10
2
1
read-write
0
LLWU_P10 input was not a wakeup source
#0
1
LLWU_P10 input was a wakeup source
#1
WUF11
Wakeup Flag For LLWU_P11
3
1
read-write
0
LLWU_P11 input was not a wakeup source
#0
1
LLWU_P11 input was a wakeup source
#1
WUF12
Wakeup Flag For LLWU_P12
4
1
read-write
0
LLWU_P12 input was not a wakeup source
#0
1
LLWU_P12 input was a wakeup source
#1
WUF13
Wakeup Flag For LLWU_P13
5
1
read-write
0
LLWU_P13 input was not a wakeup source
#0
1
LLWU_P13 input was a wakeup source
#1
WUF14
Wakeup Flag For LLWU_P14
6
1
read-write
0
LLWU_P14 input was not a wakeup source
#0
1
LLWU_P14 input was a wakeup source
#1
WUF15
Wakeup Flag For LLWU_P15
7
1
read-write
0
LLWU_P15 input was not a wakeup source
#0
1
LLWU_P15 input was a wakeup source
#1
F3
LLWU Flag 3 register
0x7
8
read-only
0
0xFF
MWUF0
Wakeup flag For module 0
0
1
read-only
0
Module 0 input was not a wakeup source
#0
1
Module 0 input was a wakeup source
#1
MWUF1
Wakeup flag For module 1
1
1
read-only
0
Module 1 input was not a wakeup source
#0
1
Module 1 input was a wakeup source
#1
MWUF2
Wakeup flag For module 2
2
1
read-only
0
Module 2 input was not a wakeup source
#0
1
Module 2 input was a wakeup source
#1
MWUF3
Wakeup flag For module 3
3
1
read-only
0
Module 3 input was not a wakeup source
#0
1
Module 3 input was a wakeup source
#1
MWUF4
Wakeup flag For module 4
4
1
read-only
0
Module 4 input was not a wakeup source
#0
1
Module 4 input was a wakeup source
#1
MWUF5
Wakeup flag For module 5
5
1
read-only
0
Module 5 input was not a wakeup source
#0
1
Module 5 input was a wakeup source
#1
MWUF6
Wakeup flag For module 6
6
1
read-only
0
Module 6 input was not a wakeup source
#0
1
Module 6 input was a wakeup source
#1
MWUF7
Wakeup flag For module 7
7
1
read-only
0
Module 7 input was not a wakeup source
#0
1
Module 7 input was a wakeup source
#1
FILT1
LLWU Pin Filter 1 register
0x8
8
read-write
0
0xFF
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 1 was not a wakeup source
#0
1
Pin Filter 1 was a wakeup source
#1
FILT2
LLWU Pin Filter 2 register
0x9
8
read-write
0
0xFF
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 2 was not a wakeup source
#0
1
Pin Filter 2 was a wakeup source
#1
RST
LLWU Reset Enable register
0xA
8
read-write
0x2
0xFF
RSTFILT
Digital Filter On RESET Pin
0
1
read-write
0
Filter not enabled
#0
1
Filter enabled
#1
LLRSTE
Low-Leakage Mode RESET Enable
1
1
read-write
0
RESET pin not enabled as a leakage mode exit source
#0
1
RESET pin enabled as a low leakage mode exit source
#1
PMC
Power Management Controller
PMC_
0x4007D000
0
0x3
registers
LVD_LVW
20
LVDSC1
Low Voltage Detect Status And Control 1 register
0
8
read-write
0x10
0xFF
LVDV
Low-Voltage Detect Voltage Select
0
2
read-write
00
Low trip point selected (V LVD = V LVDL )
#00
01
High trip point selected (V LVD = V LVDH )
#01
LVDRE
Low-Voltage Detect Reset Enable
4
1
read-write
0
LVDF does not generate hardware resets
#0
1
Force an MCU reset when LVDF = 1
#1
LVDIE
Low-Voltage Detect Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVDF = 1
#1
LVDACK
Low-Voltage Detect Acknowledge
6
1
write-only
LVDF
Low-Voltage Detect Flag
7
1
read-only
0
Low-voltage event not detected
#0
1
Low-voltage event detected
#1
LVDSC2
Low Voltage Detect Status And Control 2 register
0x1
8
read-write
0
0xFF
LVWV
Low-Voltage Warning Voltage Select
0
2
read-write
00
Low trip point selected (VLVW = VLVW1)
#00
01
Mid 1 trip point selected (VLVW = VLVW2)
#01
10
Mid 2 trip point selected (VLVW = VLVW3)
#10
11
High trip point selected (VLVW = VLVW4)
#11
LVWIE
Low-Voltage Warning Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVWF = 1
#1
LVWACK
Low-Voltage Warning Acknowledge
6
1
write-only
LVWF
Low-Voltage Warning Flag
7
1
read-only
0
Low-voltage warning event not detected
#0
1
Low-voltage warning event detected
#1
REGSC
Regulator Status And Control register
0x2
8
read-write
0x4
0xFF
BGBE
Bandgap Buffer Enable
0
1
read-write
0
Bandgap buffer not enabled
#0
1
Bandgap buffer enabled
#1
REGONS
Regulator In Run Regulation Status
2
1
read-only
0
Regulator is in stop regulation or in transition to/from it
#0
1
Regulator is in run regulation
#1
ACKISO
Acknowledge Isolation
3
1
read-write
0
Peripherals and I/O pads are in normal run state.
#0
1
Certain peripherals and I/O pads are in an isolated and latched state.
#1
BGEN
Bandgap Enable In VLPx Operation
4
1
read-write
0
Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
#0
1
Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
#1
SMC
System Mode Controller
SMC_
0x4007E000
0
0x4
registers
PMPROT
Power Mode Protection register
0
8
read-write
0
0xFF
AVLLS
Allow Very-Low-Leakage Stop Mode
1
1
read-write
0
Any VLLSx mode is not allowed
#0
1
Any VLLSx mode is allowed
#1
ALLS
Allow Low-Leakage Stop Mode
3
1
read-write
0
LLS is not allowed
#0
1
LLS is allowed
#1
AVLP
Allow Very-Low-Power Modes
5
1
read-write
0
VLPR, VLPW, and VLPS are not allowed.
#0
1
VLPR, VLPW, and VLPS are allowed.
#1
PMCTRL
Power Mode Control register
0x1
8
read-write
0
0xFF
STOPM
Stop Mode Control
0
3
read-write
000
Normal Stop (STOP)
#000
010
Very-Low-Power Stop (VLPS)
#010
011
Low-Leakage Stop (LLS)
#011
100
Very-Low-Leakage Stop (VLLSx)
#100
110
Reseved
#110
STOPA
Stop Aborted
3
1
read-only
0
The previous stop mode entry was successsful.
#0
1
The previous stop mode entry was aborted.
#1
RUNM
Run Mode Control
5
2
read-write
00
Normal Run mode (RUN)
#00
10
Very-Low-Power Run mode (VLPR)
#10
LPWUI
Low-Power Wake Up On Interrupt
7
1
read-write
0
The system remains in a VLP mode on an interrupt
#0
1
The system exits to Normal RUN mode on an interrupt
#1
VLLSCTRL
VLLS Control register
0x2
8
read-write
0x3
0xFF
VLLSM
VLLS Mode Control
0
3
read-write
000
VLLS0
#000
001
VLLS1
#001
010
VLLS2
#010
011
VLLS3
#011
PORPO
POR Power Option
5
1
read-write
0
POR detect circuit is enabled in VLLS0.
#0
1
POR detect circuit is disabled in VLLS0.
#1
PMSTAT
Power Mode Status register
0x3
8
read-only
0x1
0xFF
PMSTAT
When debug is enabled, the PMSTAT will not update to STOP or VLPS
0
7
read-only
RCM
Reset Control Module
RCM_
0x4007F000
0
0x8
registers
SRS0
System Reset Status Register 0
0
8
read-only
0x82
0xFF
WAKEUP
Low Leakage Wakeup Reset
0
1
read-only
0
Reset not caused by LLWU module wakeup source
#0
1
Reset caused by LLWU module wakeup source
#1
LVD
Low-Voltage Detect Reset
1
1
read-only
0
Reset not caused by LVD trip or POR
#0
1
Reset caused by LVD trip or POR
#1
LOC
Loss-of-Clock Reset
2
1
read-only
0
Reset not caused by a loss of external clock.
#0
1
Reset caused by a loss of external clock.
#1
LOL
Loss-of-Lock Reset
3
1
read-only
0
Reset not caused by a loss of lock in the PLL
#0
1
Reset caused by a loss of lock in the PLL
#1
WDOG
Watchdog
5
1
read-only
0
Reset not caused by watchdog timeout
#0
1
Reset caused by watchdog timeout
#1
PIN
External Reset Pin
6
1
read-only
0
Reset not caused by external reset pin
#0
1
Reset caused by external reset pin
#1
POR
Power-On Reset
7
1
read-only
0
Reset not caused by POR
#0
1
Reset caused by POR
#1
SRS1
System Reset Status Register 1
0x1
8
read-only
0
0xFF
JTAG
JTAG Generated Reset
0
1
read-only
0
Reset not caused by JTAG
#0
1
Reset caused by JTAG
#1
LOCKUP
Core Lockup
1
1
read-only
0
Reset not caused by core LOCKUP event
#0
1
Reset caused by core LOCKUP event
#1
SW
Software
2
1
read-only
0
Reset not caused by software setting of SYSRESETREQ bit
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
MDM_AP
MDM-AP System Reset Request
3
1
read-only
0
Reset not caused by host debugger system setting of the System Reset Request bit
#0
1
Reset caused by host debugger system setting of the System Reset Request bit
#1
EZPT
EzPort Reset
4
1
read-only
0
Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
#0
1
Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
#1
SACKERR
Stop Mode Acknowledge Error Reset
5
1
read-only
0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#0
1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
#1
RPFC
Reset Pin Filter Control register
0x4
8
read-write
0
0xFF
RSTFLTSRW
Reset Pin Filter Select in Run and Wait Modes
0
2
read-write
00
All filtering disabled
#00
01
Bus clock filter enabled for normal operation
#01
10
LPO clock filter enabled for normal operation
#10
RSTFLTSS
Reset Pin Filter Select in Stop Mode
2
1
read-write
0
All filtering disabled
#0
1
LPO clock filter enabled
#1
RPFW
Reset Pin Filter Width register
0x5
8
read-write
0
0xFF
RSTFLTSEL
Reset Pin Filter Bus Clock Select
0
5
read-write
00000
Bus clock filter count is 1
#00000
00001
Bus clock filter count is 2
#00001
00010
Bus clock filter count is 3
#00010
00011
Bus clock filter count is 4
#00011
00100
Bus clock filter count is 5
#00100
00101
Bus clock filter count is 6
#00101
00110
Bus clock filter count is 7
#00110
00111
Bus clock filter count is 8
#00111
01000
Bus clock filter count is 9
#01000
01001
Bus clock filter count is 10
#01001
01010
Bus clock filter count is 11
#01010
01011
Bus clock filter count is 12
#01011
01100
Bus clock filter count is 13
#01100
01101
Bus clock filter count is 14
#01101
01110
Bus clock filter count is 15
#01110
01111
Bus clock filter count is 16
#01111
10000
Bus clock filter count is 17
#10000
10001
Bus clock filter count is 18
#10001
10010
Bus clock filter count is 19
#10010
10011
Bus clock filter count is 20
#10011
10100
Bus clock filter count is 21
#10100
10101
Bus clock filter count is 22
#10101
10110
Bus clock filter count is 23
#10110
10111
Bus clock filter count is 24
#10111
11000
Bus clock filter count is 25
#11000
11001
Bus clock filter count is 26
#11001
11010
Bus clock filter count is 27
#11010
11011
Bus clock filter count is 28
#11011
11100
Bus clock filter count is 29
#11100
11101
Bus clock filter count is 30
#11101
11110
Bus clock filter count is 31
#11110
11111
Bus clock filter count is 32
#11111
MR
Mode Register
0x7
8
read-only
0
0xFF
EZP_MS
EZP_MS_B pin state
1
1
read-only
0
Pin deasserted (logic 1)
#0
1
Pin asserted (logic 0)
#1
SDHC
Secured Digital Host Controller
SDHC_
0x400B1000
0
0x100
registers
SDHC
81
DSADDR
DMA System Address register
0
32
read-write
0
0xFFFFFFFF
DSADDR
DMA System Address
2
30
read-write
BLKATTR
Block Attributes register
0x4
32
read-write
0
0xFFFFFFFF
BLKSIZE
Transfer Block Size
0
13
read-write
0
No data transfer.
#0
1
1 Byte
#1
10
2 Bytes
#10
11
3 Bytes
#11
100
4 Bytes
#100
111111111
511 Bytes
#111111111
1000000000
512 Bytes
#1000000000
100000000000
2048 Bytes
#100000000000
1000000000000
4096 Bytes
#1000000000000
BLKCNT
Blocks Count For Current Transfer
16
16
read-write
0
Stop count.
#0
1
1 block
#1
10
2 blocks
#10
1111111111111111
65535 blocks
#1111111111111111
CMDARG
Command Argument register
0x8
32
read-write
0
0xFFFFFFFF
CMDARG
Command Argument
0
32
read-write
XFERTYP
Transfer Type register
0xC
32
read-write
0
0xFFFFFFFF
DMAEN
DMA Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
BCEN
Block Count Enable
1
1
read-write
0
Disable
#0
1
Enable
#1
AC12EN
Auto CMD12 Enable
2
1
read-write
0
Disable
#0
1
Enable
#1
DTDSEL
Data Transfer Direction Select
4
1
read-write
0
Write host to card.
#0
1
Read card to host.
#1
MSBSEL
Multi/Single Block Select
5
1
read-write
0
Single block.
#0
1
Multiple blocks.
#1
RSPTYP
Response Type Select
16
2
read-write
00
No response.
#00
01
Response length 136.
#01
10
Response length 48.
#10
11
Response length 48, check busy after response.
#11
CCCEN
Command CRC Check Enable
19
1
read-write
0
Disable
#0
1
Enable
#1
CICEN
Command Index Check Enable
20
1
read-write
0
Disable
#0
1
Enable
#1
DPSEL
Data Present Select
21
1
read-write
0
No data present.
#0
1
Data present.
#1
CMDTYP
Command Type
22
2
read-write
00
Normal other commands.
#00
01
Suspend CMD52 for writing bus suspend in CCCR.
#01
10
Resume CMD52 for writing function select in CCCR.
#10
11
Abort CMD12, CMD52 for writing I/O abort in CCCR.
#11
CMDINX
Command Index
24
6
read-write
CMDRSP0
Command Response 0
0x10
32
read-only
0
0xFFFFFFFF
CMDRSP0
Command Response 0
0
32
read-only
CMDRSP1
Command Response 1
0x14
32
read-only
0
0xFFFFFFFF
CMDRSP1
Command Response 1
0
32
read-only
CMDRSP2
Command Response 2
0x18
32
read-only
0
0xFFFFFFFF
CMDRSP2
Command Response 2
0
32
read-only
CMDRSP3
Command Response 3
0x1C
32
read-only
0
0xFFFFFFFF
CMDRSP3
Command Response 3
0
32
read-only
DATPORT
Buffer Data Port register
0x20
32
read-write
0
0xFFFFFFFF
DATCONT
Data Content
0
32
read-write
PRSSTAT
Present State register
0x24
32
read-only
0
0xFFFFFFFF
CIHB
Command Inhibit (CMD)
0
1
read-only
0
Can issue command using only CMD line.
#0
1
Cannot issue command.
#1
CDIHB
Command Inhibit (DAT)
1
1
read-only
0
Can issue command which uses the DAT line.
#0
1
Cannot issue command which uses the DAT line.
#1
DLA
Data Line Active
2
1
read-only
0
DAT line inactive.
#0
1
DAT line active.
#1
SDSTB
SD Clock Stable
3
1
read-only
0
Clock is changing frequency and not stable.
#0
1
Clock is stable.
#1
IPGOFF
Bus Clock Gated Off Internally
4
1
read-only
0
Bus clock is active.
#0
1
Bus clock is gated off.
#1
HCKOFF
System Clock Gated Off Internally
5
1
read-only
0
System clock is active.
#0
1
System clock is gated off.
#1
PEROFF
SDHC clock Gated Off Internally
6
1
read-only
0
SDHC clock is active.
#0
1
SDHC clock is gated off.
#1
SDOFF
SD Clock Gated Off Internally
7
1
read-only
0
SD clock is active.
#0
1
SD clock is gated off.
#1
WTA
Write Transfer Active
8
1
read-only
0
No valid data.
#0
1
Transferring data.
#1
RTA
Read Transfer Active
9
1
read-only
0
No valid data.
#0
1
Transferring data.
#1
BWEN
Buffer Write Enable
10
1
read-only
0
Write disable, the buffer can hold valid data less than the write watermark level.
#0
1
Write enable, the buffer can hold valid data greater than the write watermark level.
#1
BREN
Buffer Read Enable
11
1
read-only
0
Read disable, valid data less than the watermark level exist in the buffer.
#0
1
Read enable, valid data greater than the watermark level exist in the buffer.
#1
CINS
Card Inserted
16
1
read-only
0
Power on reset or no card.
#0
1
Card inserted.
#1
CLSL
CMD Line Signal Level
23
1
read-only
DLSL
DAT Line Signal Level
24
8
read-only
PROCTL
Protocol Control register
0x28
32
read-write
0x20
0xFFFFFFFF
LCTL
LED Control
0
1
read-write
0
LED off.
#0
1
LED on.
#1
DTW
Data Transfer Width
1
2
read-write
00
1-bit mode
#00
01
4-bit mode
#01
10
8-bit mode
#10
D3CD
DAT3 As Card Detection Pin
3
1
read-write
0
DAT3 does not monitor card Insertion.
#0
1
DAT3 as card detection pin.
#1
EMODE
Endian Mode
4
2
read-write
00
Big endian mode
#00
01
Half word big endian mode
#01
10
Little endian mode
#10
CDTL
Card Detect Test Level
6
1
read-write
0
Card detect test level is 0, no card inserted.
#0
1
Card detect test level is 1, card inserted.
#1
CDSS
Card Detect Signal Selection
7
1
read-write
0
Card detection level is selected for normal purpose.
#0
1
Card detection test level is selected for test purpose.
#1
DMAS
DMA Select
8
2
read-write
00
No DMA or simple DMA is selected.
#00
01
ADMA1 is selected.
#01
10
ADMA2 is selected.
#10
SABGREQ
Stop At Block Gap Request
16
1
read-write
0
Transfer
#0
1
Stop
#1
CREQ
Continue Request
17
1
read-write
0
No effect.
#0
1
Restart
#1
RWCTL
Read Wait Control
18
1
read-write
0
Disable read wait control, and stop SD clock at block gap when SABGREQ is set.
#0
1
Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.
#1
IABG
Interrupt At Block Gap
19
1
read-write
0
Disabled
#0
1
Enabled
#1
WECINT
Wakeup Event Enable On Card Interrupt
24
1
read-write
0
Disabled
#0
1
Enabled
#1
WECINS
Wakeup Event Enable On SD Card Insertion
25
1
read-write
0
Disabled
#0
1
Enabled
#1
WECRM
Wakeup Event Enable On SD Card Removal
26
1
read-write
0
Disabled
#0
1
Enabled
#1
SYSCTL
System Control register
0x2C
32
read-write
0x8008
0xFFFFFFFF
IPGEN
IPG Clock Enable
0
1
read-write
0
Bus clock will be internally gated off.
#0
1
Bus clock will not be automatically gated off.
#1
HCKEN
System Clock Enable
1
1
read-write
0
System clock will be internally gated off.
#0
1
System clock will not be automatically gated off.
#1
PEREN
Peripheral Clock Enable
2
1
read-write
0
SDHC clock will be internally gated off.
#0
1
SDHC clock will not be automatically gated off.
#1
SDCLKEN
SD Clock Enable
3
1
read-write
DVS
Divisor
4
4
read-write
0
Divisor by 1.
#0000
1
Divisor by 2.
#0001
1110
Divisor by 15.
#1110
1111
Divisor by 16.
#1111
SDCLKFS
SDCLK Frequency Select
8
8
read-write
1
Base clock divided by 2.
#1
10
Base clock divided by 4.
#10
100
Base clock divided by 8.
#100
1000
Base clock divided by 16.
#1000
10000
Base clock divided by 32.
#10000
100000
Base clock divided by 64.
#100000
1000000
Base clock divided by 128.
#1000000
10000000
Base clock divided by 256.
#10000000
DTOCV
Data Timeout Counter Value
16
4
read-write
0000
SDCLK x 2 13
#0000
0001
SDCLK x 2 14
#0001
1110
SDCLK x 2 27
#1110
RSTA
Software Reset For ALL
24
1
write-only
0
No reset.
#0
1
Reset.
#1
RSTC
Software Reset For CMD Line
25
1
write-only
0
No reset.
#0
1
Reset.
#1
RSTD
Software Reset For DAT Line
26
1
write-only
0
No reset.
#0
1
Reset.
#1
INITA
Initialization Active
27
1
read-write
IRQSTAT
Interrupt Status register
0x30
32
read-write
0
0xFFFFFFFF
CC
Command Complete
0
1
read-write
0
Command not complete.
#0
1
Command complete.
#1
TC
Transfer Complete
1
1
read-write
0
Transfer not complete.
#0
1
Transfer complete.
#1
BGE
Block Gap Event
2
1
read-write
0
No block gap event.
#0
1
Transaction stopped at block gap.
#1
DINT
DMA Interrupt
3
1
read-write
0
No DMA Interrupt.
#0
1
DMA Interrupt is generated.
#1
BWR
Buffer Write Ready
4
1
read-write
0
Not ready to write buffer.
#0
1
Ready to write buffer.
#1
BRR
Buffer Read Ready
5
1
read-write
0
Not ready to read buffer.
#0
1
Ready to read buffer.
#1
CINS
Card Insertion
6
1
read-write
0
Card state unstable or removed.
#0
1
Card inserted.
#1
CRM
Card Removal
7
1
read-write
0
Card state unstable or inserted.
#0
1
Card removed.
#1
CINT
Card Interrupt
8
1
read-write
0
No Card Interrupt.
#0
1
Generate Card Interrupt.
#1
CTOE
Command Timeout Error
16
1
read-write
0
No error.
#0
1
Time out.
#1
CCE
Command CRC Error
17
1
read-write
0
No error.
#0
1
CRC Error generated.
#1
CEBE
Command End Bit Error
18
1
read-write
0
No error.
#0
1
End Bit Error generated.
#1
CIE
Command Index Error
19
1
read-write
0
No error.
#0
1
Error.
#1
DTOE
Data Timeout Error
20
1
read-write
0
No error.
#0
1
Time out.
#1
DCE
Data CRC Error
21
1
read-write
0
No error.
#0
1
Error.
#1
DEBE
Data End Bit Error
22
1
read-write
0
No error.
#0
1
Error.
#1
AC12E
Auto CMD12 Error
24
1
read-write
0
No error.
#0
1
Error.
#1
DMAE
DMA Error
28
1
read-write
0
No error.
#0
1
Error.
#1
IRQSTATEN
Interrupt Status Enable register
0x34
32
read-write
0x117F013F
0xFFFFFFFF
CCSEN
Command Complete Status Enable
0
1
read-write
0
Masked
#0
1
Enabled
#1
TCSEN
Transfer Complete Status Enable
1
1
read-write
0
Masked
#0
1
Enabled
#1
BGESEN
Block Gap Event Status Enable
2
1
read-write
0
Masked
#0
1
Enabled
#1
DINTSEN
DMA Interrupt Status Enable
3
1
read-write
0
Masked
#0
1
Enabled
#1
BWRSEN
Buffer Write Ready Status Enable
4
1
read-write
0
Masked
#0
1
Enabled
#1
BRRSEN
Buffer Read Ready Status Enable
5
1
read-write
0
Masked
#0
1
Enabled
#1
CINSEN
Card Insertion Status Enable
6
1
read-write
0
Masked
#0
1
Enabled
#1
CRMSEN
Card Removal Status Enable
7
1
read-write
0
Masked
#0
1
Enabled
#1
CINTSEN
Card Interrupt Status Enable
8
1
read-write
0
Masked
#0
1
Enabled
#1
CTOESEN
Command Timeout Error Status Enable
16
1
read-write
0
Masked
#0
1
Enabled
#1
CCESEN
Command CRC Error Status Enable
17
1
read-write
0
Masked
#0
1
Enabled
#1
CEBESEN
Command End Bit Error Status Enable
18
1
read-write
0
Masked
#0
1
Enabled
#1
CIESEN
Command Index Error Status Enable
19
1
read-write
0
Masked
#0
1
Enabled
#1
DTOESEN
Data Timeout Error Status Enable
20
1
read-write
0
Masked
#0
1
Enabled
#1
DCESEN
Data CRC Error Status Enable
21
1
read-write
0
Masked
#0
1
Enabled
#1
DEBESEN
Data End Bit Error Status Enable
22
1
read-write
0
Masked
#0
1
Enabled
#1
AC12ESEN
Auto CMD12 Error Status Enable
24
1
read-write
0
Masked
#0
1
Enabled
#1
DMAESEN
DMA Error Status Enable
28
1
read-write
0
Masked
#0
1
Enabled
#1
IRQSIGEN
Interrupt Signal Enable register
0x38
32
read-write
0
0xFFFFFFFF
CCIEN
Command Complete Interrupt Enable
0
1
read-write
0
Masked
#0
1
Enabled
#1
TCIEN
Transfer Complete Interrupt Enable
1
1
read-write
0
Masked
#0
1
Enabled
#1
BGEIEN
Block Gap Event Interrupt Enable
2
1
read-write
0
Masked
#0
1
Enabled
#1
DINTIEN
DMA Interrupt Enable
3
1
read-write
0
Masked
#0
1
Enabled
#1
BWRIEN
Buffer Write Ready Interrupt Enable
4
1
read-write
0
Masked
#0
1
Enabled
#1
BRRIEN
Buffer Read Ready Interrupt Enable
5
1
read-write
0
Masked
#0
1
Enabled
#1
CINSIEN
Card Insertion Interrupt Enable
6
1
read-write
0
Masked
#0
1
Enabled
#1
CRMIEN
Card Removal Interrupt Enable
7
1
read-write
0
Masked
#0
1
Enabled
#1
CINTIEN
Card Interrupt Enable
8
1
read-write
0
Masked
#0
1
Enabled
#1
CTOEIEN
Command Timeout Error Interrupt Enable
16
1
read-write
0
Masked
#0
1
Enabled
#1
CCEIEN
Command CRC Error Interrupt Enable
17
1
read-write
0
Masked
#0
1
Enabled
#1
CEBEIEN
Command End Bit Error Interrupt Enable
18
1
read-write
0
Masked
#0
1
Enabled
#1
CIEIEN
Command Index Error Interrupt Enable
19
1
read-write
0
Masked
#0
1
Enabled
#1
DTOEIEN
Data Timeout Error Interrupt Enable
20
1
read-write
0
Masked
#0
1
Enabled
#1
DCEIEN
Data CRC Error Interrupt Enable
21
1
read-write
0
Masked
#0
1
Enabled
#1
DEBEIEN
Data End Bit Error Interrupt Enable
22
1
read-write
0
Masked
#0
1
Enabled
#1
AC12EIEN
Auto CMD12 Error Interrupt Enable
24
1
read-write
0
Masked
#0
1
Enabled
#1
DMAEIEN
DMA Error Interrupt Enable
28
1
read-write
0
Masked
#0
1
Enabled
#1
AC12ERR
Auto CMD12 Error Status Register
0x3C
32
read-only
0
0xFFFFFFFF
AC12NE
Auto CMD12 Not Executed
0
1
read-only
0
Executed.
#0
1
Not executed.
#1
AC12TOE
Auto CMD12 Timeout Error
1
1
read-only
0
No error.
#0
1
Time out.
#1
AC12EBE
Auto CMD12 End Bit Error
2
1
read-only
0
No error.
#0
1
End bit error generated.
#1
AC12CE
Auto CMD12 CRC Error
3
1
read-only
0
No CRC error.
#0
1
CRC error met in Auto CMD12 response.
#1
AC12IE
Auto CMD12 Index Error
4
1
read-only
0
No error.
#0
1
Error, the CMD index in response is not CMD12.
#1
CNIBAC12E
Command Not Issued By Auto CMD12 Error
7
1
read-only
0
No error.
#0
1
Not issued.
#1
HTCAPBLT
Host Controller Capabilities
0x40
32
read-only
0x7F30000
0xFFFFFFFF
MBL
Max Block Length
16
3
read-only
000
512 bytes
#000
001
1024 bytes
#001
010
2048 bytes
#010
011
4096 bytes
#011
ADMAS
ADMA Support
20
1
read-only
0
Advanced DMA not supported.
#0
1
Advanced DMA supported.
#1
HSS
High Speed Support
21
1
read-only
0
High speed not supported.
#0
1
High speed supported.
#1
DMAS
DMA Support
22
1
read-only
0
DMA not supported.
#0
1
DMA supported.
#1
SRS
Suspend/Resume Support
23
1
read-only
0
Not supported.
#0
1
Supported.
#1
VS33
Voltage Support 3.3 V
24
1
read-only
0
3.3 V not supported.
#0
1
3.3 V supported.
#1
WML
Watermark Level Register
0x44
32
read-write
0x100010
0xFFFFFFFF
RDWML
Read Watermark Level
0
8
read-write
WRWML
Write Watermark Level
16
8
read-write
FEVT
Force Event register
0x50
32
write-only
0
0xFFFFFFFF
AC12NE
Force Event Auto Command 12 Not Executed
0
1
write-only
AC12TOE
Force Event Auto Command 12 Time Out Error
1
1
write-only
AC12CE
Force Event Auto Command 12 CRC Error
2
1
write-only
AC12EBE
Force Event Auto Command 12 End Bit Error
3
1
write-only
AC12IE
Force Event Auto Command 12 Index Error
4
1
write-only
CNIBAC12E
Force Event Command Not Executed By Auto Command 12 Error
7
1
write-only
CTOE
Force Event Command Time Out Error
16
1
write-only
CCE
Force Event Command CRC Error
17
1
write-only
CEBE
Force Event Command End Bit Error
18
1
write-only
CIE
Force Event Command Index Error
19
1
write-only
DTOE
Force Event Data Time Out Error
20
1
write-only
DCE
Force Event Data CRC Error
21
1
write-only
DEBE
Force Event Data End Bit Error
22
1
write-only
AC12E
Force Event Auto Command 12 Error
24
1
write-only
DMAE
Force Event DMA Error
28
1
write-only
CINT
Force Event Card Interrupt
31
1
write-only
ADMAES
ADMA Error Status register
0x54
32
read-only
0
0xFFFFFFFF
ADMAES
ADMA Error State (When ADMA Error Is Occurred.)
0
2
read-only
ADMALME
ADMA Length Mismatch Error
2
1
read-only
0
No error.
#0
1
Error.
#1
ADMADCE
ADMA Descriptor Error
3
1
read-only
0
No error.
#0
1
Error.
#1
ADSADDR
ADMA System Addressregister
0x58
32
read-write
0
0xFFFFFFFF
ADSADDR
ADMA System Address
2
30
read-write
VENDOR
Vendor Specific register
0xC0
32
read-write
0x1
0xFFFFFFFF
EXTDMAEN
External DMA Request Enable
0
1
read-write
0
In any scenario, SDHC does not send out the external DMA request.
#0
1
When internal DMA is not active, the external DMA request will be sent out.
#1
EXBLKNU
Exact Block Number Block Read Enable For SDIO CMD53
1
1
read-write
0
None exact block read.
#0
1
Exact block read for SDIO CMD53.
#1
INTSTVAL
Internal State Value
16
8
read-only
MMCBOOT
MMC Boot register
0xC4
32
read-write
0
0xFFFFFFFF
DTOCVACK
Boot ACK Time Out Counter Value
0
4
read-write
0000
SDCLK x 2^8
#0000
0001
SDCLK x 2^9
#0001
0010
SDCLK x 2^10
#0010
0011
SDCLK x 2^11
#0011
0100
SDCLK x 2^12
#0100
0101
SDCLK x 2^13
#0101
0110
SDCLK x 2^14
#0110
0111
SDCLK x 2^15
#0111
1110
SDCLK x 2^22
#1110
BOOTACK
Boot Ack Mode Select
4
1
read-write
0
No ack.
#0
1
Ack.
#1
BOOTMODE
Boot Mode Select
5
1
read-write
0
Normal boot.
#0
1
Alternative boot.
#1
BOOTEN
Boot Mode Enable
6
1
read-write
0
Fast boot disable.
#0
1
Fast boot enable.
#1
AUTOSABGEN
When boot, enable auto stop at block gap function
7
1
read-write
BOOTBLKCNT
Defines the stop at block gap value of automatic mode
16
16
read-write
HOSTVER
Host Controller Version
0xFC
32
read-only
0x1201
0xFFFFFFFF
SVN
Specification Version Number
0
8
read-only
1
SD host specification version 2.0, supports test event register and ADMA.
#1
VVN
Vendor Version Number
8
8
read-only
0
Freescale SDHC version 1.0
#0
10000
Freescale SDHC version 2.0
#10000
10001
Freescale SDHC version 2.1
#10001
10010
Freescale SDHC version 2.2
#10010
ENET
Ethernet MAC-NET Core
ENET_
0x400C0000
0x4
0x624
registers
ENET_1588_Timer
82
ENET_Transmit
83
ENET_Receive
84
ENET_Error
85
EIR
Interrupt Event Register
0x4
32
read-write
0
0xFFFFFFFF
TS_TIMER
Timestamp Timer
15
1
read-write
TS_AVAIL
Transmit Timestamp Available
16
1
read-write
WAKEUP
Node Wakeup Request Indication
17
1
read-write
PLR
Payload Receive Error
18
1
read-write
UN
Transmit FIFO Underrun
19
1
read-write
RL
Collision Retry Limit
20
1
read-write
LC
Late Collision
21
1
read-write
EBERR
Ethernet Bus Error
22
1
read-write
MII
MII Interrupt.
23
1
read-write
RXB
Receive Buffer Interrupt
24
1
read-write
RXF
Receive Frame Interrupt
25
1
read-write
TXB
Transmit Buffer Interrupt
26
1
read-write
TXF
Transmit Frame Interrupt
27
1
read-write
GRA
Graceful Stop Complete
28
1
read-write
BABT
Babbling Transmit Error
29
1
read-write
BABR
Babbling Receive Error
30
1
read-write
EIMR
Interrupt Mask Register
0x8
32
read-write
0
0xFFFFFFFF
TS_TIMER
TS_TIMER Interrupt Mask
15
1
read-write
TS_AVAIL
TS_AVAIL Interrupt Mask
16
1
read-write
WAKEUP
WAKEUP Interrupt Mask
17
1
read-write
PLR
PLR Interrupt Mask
18
1
read-write
UN
UN Interrupt Mask
19
1
read-write
RL
RL Interrupt Mask
20
1
read-write
LC
LC Interrupt Mask
21
1
read-write
EBERR
EBERR Interrupt Mask
22
1
read-write
MII
MII Interrupt Mask
23
1
read-write
RXB
RXB Interrupt Mask
24
1
read-write
RXF
RXF Interrupt Mask
25
1
read-write
TXB
TXB Interrupt Mask
26
1
read-write
0
The corresponding interrupt source is masked.
#0
1
The corresponding interrupt source is not masked.
#1
TXF
TXF Interrupt Mask
27
1
read-write
0
The corresponding interrupt source is masked.
#0
1
The corresponding interrupt source is not masked.
#1
GRA
GRA Interrupt Mask
28
1
read-write
0
The corresponding interrupt source is masked.
#0
1
The corresponding interrupt source is not masked.
#1
BABT
BABT Interrupt Mask
29
1
read-write
0
The corresponding interrupt source is masked.
#0
1
The corresponding interrupt source is not masked.
#1
BABR
BABR Interrupt Mask
30
1
read-write
0
The corresponding interrupt source is masked.
#0
1
The corresponding interrupt source is not masked.
#1
RDAR
Receive Descriptor Active Register
0x10
32
read-write
0
0xFFFFFFFF
RDAR
Receive Descriptor Active
24
1
read-write
TDAR
Transmit Descriptor Active Register
0x14
32
read-write
0
0xFFFFFFFF
TDAR
Transmit Descriptor Active
24
1
read-write
ECR
Ethernet Control Register
0x24
32
read-write
0xF0000000
0xFFFFFFFF
RESET
Ethernet MAC Reset
0
1
read-write
ETHEREN
Ethernet Enable
1
1
read-write
0
Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
#0
1
MAC is enabled, and reception and transmission are possible.
#1
MAGICEN
Magic Packet Detection Enable
2
1
read-write
0
Magic detection logic disabled.
#0
1
The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#1
SLEEP
Sleep Mode Enable
3
1
read-write
0
Normal operating mode.
#0
1
Sleep mode.
#1
EN1588
EN1588 Enable
4
1
read-write
0
Legacy FEC buffer descriptors and functions enabled.
#0
1
Enhanced frame time-stamping functions enabled.
#1
DBGEN
Debug Enable
6
1
read-write
0
MAC continues operation in debug mode.
#0
1
MAC enters hardware freeze mode when the processor is in debug mode.
#1
STOPEN
STOPEN Signal Control
7
1
read-write
DBSWP
Descriptor Byte Swapping Enable
8
1
read-write
0
The buffer descriptor bytes are not swapped to support big-endian devices.
#0
1
The buffer descriptor bytes are swapped to support little-endian devices.
#1
MMFR
MII Management Frame Register
0x40
32
read-write
0
0xFFFFFFFF
DATA
Management Frame Data
0
16
read-write
TA
Turn Around
16
2
read-write
RA
Register Address
18
5
read-write
PA
PHY Address
23
5
read-write
OP
Operation Code
28
2
read-write
00
Write frame operation, but not MII compliant.
#00
01
Write frame operation for a valid MII management frame.
#01
10
Read frame operation for a valid MII management frame.
#10
11
Read frame operation, but not MII compliant.
#11
ST
Start Of Frame Delimiter
30
2
read-write
MSCR
MII Speed Control Register
0x44
32
read-write
0
0xFFFFFFFF
MII_SPEED
MII Speed
1
6
read-write
DIS_PRE
Disable Preamble
7
1
read-write
0
Preamble enabled.
#0
1
Preamble (32 ones) is not prepended to the MII management frame.
#1
HOLDTIME
Hold time On MDIO Output
8
3
read-write
000
1 internal module clock cycle
#000
001
2 internal module clock cycles
#001
010
3 internal module clock cycles
#010
111
8 internal module clock cycles
#111
MIBC
MIB Control Register
0x64
32
read-write
0xC0000000
0xFFFFFFFF
MIB_CLEAR
MIB Clear
29
1
read-write
MIB_IDLE
MIB Idle
30
1
read-only
MIB_DIS
Disable MIB Logic
31
1
read-write
RCR
Receive Control Register
0x84
32
read-write
0x5EE0001
0xFFFFFFFF
LOOP
Internal Loopback
0
1
read-write
0
Loopback disabled.
#0
1
Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#1
DRT
Disable Receive On Transmit
1
1
read-write
0
Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode.
#0
1
Disable reception of frames while transmitting. Normally used for half-duplex mode.
#1
MII_MODE
Media Independent Interface Mode
2
1
read-write
1
MII or RMII mode, as indicated by the RMII_MODE field.
#1
PROM
Promiscuous Mode
3
1
read-write
0
Disabled.
#0
1
Enabled.
#1
BC_REJ
Broadcast Frame Reject
4
1
read-write
FCE
Flow Control Enable
5
1
read-write
RMII_MODE
RMII Mode Enable
8
1
read-write
0
MAC configured for MII mode.
#0
1
MAC configured for RMII operation.
#1
RMII_10T
Enables 10-Mbps mode of the RMII .
9
1
read-write
0
100 Mbps operation.
#0
1
10 Mbps operation.
#1
PADEN
Enable Frame Padding Remove On Receive
12
1
read-write
0
No padding is removed on receive by the MAC.
#0
1
Padding is removed from received frames.
#1
PAUFWD
Terminate/Forward Pause Frames
13
1
read-write
0
Pause frames are terminated and discarded in the MAC.
#0
1
Pause frames are forwarded to the user application.
#1
CRCFWD
Terminate/Forward Received CRC
14
1
read-write
0
The CRC field of received frames is transmitted to the user application.
#0
1
The CRC field is stripped from the frame.
#1
CFEN
MAC Control Frame Enable
15
1
read-write
0
MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
#0
1
MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#1
MAX_FL
Maximum Frame Length
16
14
read-write
NLC
Payload Length Check Disable
30
1
read-write
0
The payload length check is disabled.
#0
1
The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#1
GRS
Graceful Receive Stopped
31
1
read-only
TCR
Transmit Control Register
0xC4
32
read-write
0
0xFFFFFFFF
GTS
Graceful Transmit Stop
0
1
read-write
FDEN
Full-Duplex Enable
2
1
read-write
TFC_PAUSE
Transmit Frame Control Pause
3
1
read-write
0
No PAUSE frame transmitted.
#0
1
The MAC stops transmission of data frames after the current transmission is complete.
#1
RFC_PAUSE
Receive Frame Control Pause
4
1
read-only
ADDSEL
Source MAC Address Select On Transmit
5
3
read-write
000
Node MAC address programmed on PADDR1/2 registers.
#000
ADDINS
Set MAC Address On Transmit
8
1
read-write
0
The source MAC address is not modified by the MAC.
#0
1
The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#1
CRCFWD
Forward Frame From Application With CRC
9
1
read-write
0
TxBD[TC] controls whether the frame has a CRC from the application.
#0
1
The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#1
PALR
Physical Address Lower Register
0xE4
32
read-write
0
0xFFFFFFFF
PADDR1
Pause Address
0
32
read-write
PAUR
Physical Address Upper Register
0xE8
32
read-write
0x8808
0xFFFFFFFF
TYPE
Type Field In PAUSE Frames
0
16
read-only
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames
16
16
read-write
OPD
Opcode/Pause Duration Register
0xEC
32
read-write
0x10000
0xFFFFFFFF
PAUSE_DUR
Pause Duration
0
16
read-write
OPCODE
Opcode Field In PAUSE Frames
16
16
read-only
IAUR
Descriptor Individual Upper Address Register
0x118
32
read-write
0
0xFFFFFFFF
IADDR1
Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address
0
32
read-write
IALR
Descriptor Individual Lower Address Register
0x11C
32
read-write
0
0xFFFFFFFF
IADDR2
Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address
0
32
read-write
GAUR
Descriptor Group Upper Address Register
0x120
32
read-write
0
0xFFFFFFFF
GADDR1
Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address
0
32
read-write
GALR
Descriptor Group Lower Address Register
0x124
32
read-write
0
0xFFFFFFFF
GADDR2
Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address
0
32
read-write
TFWR
Transmit FIFO Watermark Register
0x144
32
read-write
0
0xFFFFFFFF
TFWR
Transmit FIFO Write
0
6
read-write
000000
64 bytes written.
#0
000001
64 bytes written.
#1
000010
128 bytes written.
#10
000011
192 bytes written.
#11
111110
3968 bytes written.
#111110
111111
4032 bytes written.
#111111
STRFWD
Store And Forward Enable
8
1
read-write
0
Reset. The transmission start threshold is programmed in TFWR[TFWR].
#0
1
Enabled.
#1
RDSR
Receive Descriptor Ring Start Register
0x180
32
read-write
0
0xFFFFFFFF
R_DES_START
Pointer to the beginning of the receive buffer descriptor queue.
3
29
read-write
TDSR
Transmit Buffer Descriptor Ring Start Register
0x184
32
read-write
0
0xFFFFFFFF
X_DES_START
Pointer to the beginning of the transmit buffer descriptor queue.
3
29
read-write
MRBR
Maximum Receive Buffer Size Register
0x188
32
read-write
0
0xFFFFFFFF
R_BUF_SIZE
Receive buffer size in bytes.
4
10
read-write
RSFL
Receive FIFO Section Full Threshold
0x190
32
read-write
0
0xFFFFFFFF
RX_SECTION_FULL
Value Of Receive FIFO Section Full Threshold
0
8
read-write
RSEM
Receive FIFO Section Empty Threshold
0x194
32
read-write
0
0xFFFFFFFF
RX_SECTION_EMPTY
Value Of The Receive FIFO Section Empty Threshold
0
8
read-write
STAT_SECTION_EMPTY
RX Status FIFO Section Empty Threshold
16
5
read-write
RAEM
Receive FIFO Almost Empty Threshold
0x198
32
read-write
0x4
0xFFFFFFFF
RX_ALMOST_EMPTY
Value Of The Receive FIFO Almost Empty Threshold
0
8
read-write
RAFL
Receive FIFO Almost Full Threshold
0x19C
32
read-write
0x4
0xFFFFFFFF
RX_ALMOST_FULL
Value Of The Receive FIFO Almost Full Threshold
0
8
read-write
TSEM
Transmit FIFO Section Empty Threshold
0x1A0
32
read-write
0
0xFFFFFFFF
TX_SECTION_EMPTY
Value Of The Transmit FIFO Section Empty Threshold
0
8
read-write
TAEM
Transmit FIFO Almost Empty Threshold
0x1A4
32
read-write
0x4
0xFFFFFFFF
TX_ALMOST_EMPTY
Value of Transmit FIFO Almost Empty Threshold
0
8
read-write
TAFL
Transmit FIFO Almost Full Threshold
0x1A8
32
read-write
0x8
0xFFFFFFFF
TX_ALMOST_FULL
Value Of The Transmit FIFO Almost Full Threshold
0
8
read-write
TIPG
Transmit Inter-Packet Gap
0x1AC
32
read-write
0xC
0xFFFFFFFF
IPG
Transmit Inter-Packet Gap
0
5
read-write
FTRL
Frame Truncation Length
0x1B0
32
read-write
0x7FF
0xFFFFFFFF
TRUNC_FL
Frame Truncation Length
0
14
read-write
TACC
Transmit Accelerator Function Configuration
0x1C0
32
read-write
0
0xFFFFFFFF
SHIFT16
TX FIFO Shift-16
0
1
read-write
0
Disabled.
#0
1
Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#1
IPCHK
Enables insertion of IP header checksum.
3
1
read-write
0
Checksum is not inserted.
#0
1
If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#1
PROCHK
Enables insertion of protocol checksum.
4
1
read-write
0
Checksum not inserted.
#0
1
If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#1
RACC
Receive Accelerator Function Configuration
0x1C4
32
read-write
0
0xFFFFFFFF
PADREM
Enable Padding Removal For Short IP Frames
0
1
read-write
0
Padding not removed.
#0
1
Any bytes following the IP payload section of the frame are removed from the frame.
#1
IPDIS
Enable Discard Of Frames With Wrong IPv4 Header Checksum
1
1
read-write
0
Frames with wrong IPv4 header checksum are not discarded.
#0
1
If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#1
PRODIS
Enable Discard Of Frames With Wrong Protocol Checksum
2
1
read-write
0
Frames with wrong checksum are not discarded.
#0
1
If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#1
LINEDIS
Enable Discard Of Frames With MAC Layer Errors
6
1
read-write
0
Frames with errors are not discarded.
#0
1
Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#1
SHIFT16
RX FIFO Shift-16
7
1
read-write
0
Disabled.
#0
1
Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#1
RMON_T_PACKETS
Tx Packet Count Statistic Register
0x204
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_BC_PKT
Tx Broadcast Packets Statistic Register
0x208
32
read-only
0
0xFFFFFFFF
TXPKTS
Broadcast packets
0
16
read-only
RMON_T_MC_PKT
Tx Multicast Packets Statistic Register
0x20C
32
read-only
0
0xFFFFFFFF
TXPKTS
Multicast packets
0
16
read-only
RMON_T_CRC_ALIGN
Tx Packets with CRC/Align Error Statistic Register
0x210
32
read-only
0
0xFFFFFFFF
TXPKTS
Packets with CRC/align error
0
16
read-only
RMON_T_UNDERSIZE
Tx Packets Less Than Bytes and Good CRC Statistic Register
0x214
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_OVERSIZE
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
0x218
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_FRAG
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
0x21C
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_JAB
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
0x220
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_COL
Tx Collision Count Statistic Register
0x224
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P64
Tx 64-Byte Packets Statistic Register
0x228
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P65TO127
Tx 65- to 127-byte Packets Statistic Register
0x22C
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P128TO255
Tx 128- to 255-byte Packets Statistic Register
0x230
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P256TO511
Tx 256- to 511-byte Packets Statistic Register
0x234
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P512TO1023
Tx 512- to 1023-byte Packets Statistic Register
0x238
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P1024TO2047
Tx 1024- to 2047-byte Packets Statistic Register
0x23C
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_P_GTE2048
Tx Packets Greater Than 2048 Bytes Statistic Register
0x240
32
read-only
0
0xFFFFFFFF
TXPKTS
Packet count
0
16
read-only
RMON_T_OCTETS
Tx Octets Statistic Register
0x244
32
read-only
0
0xFFFFFFFF
TXOCTS
Octet count
0
32
read-only
IEEE_T_FRAME_OK
Frames Transmitted OK Statistic Register
0x24C
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_1COL
Frames Transmitted with Single Collision Statistic Register
0x250
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_MCOL
Frames Transmitted with Multiple Collisions Statistic Register
0x254
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_DEF
Frames Transmitted after Deferral Delay Statistic Register
0x258
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_LCOL
Frames Transmitted with Late Collision Statistic Register
0x25C
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_EXCOL
Frames Transmitted with Excessive Collisions Statistic Register
0x260
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_MACERR
Frames Transmitted with Tx FIFO Underrun Statistic Register
0x264
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_CSERR
Frames Transmitted with Carrier Sense Error Statistic Register
0x268
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_FDXFC
Flow Control Pause Frames Transmitted Statistic Register
0x270
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_T_OCTETS_OK
Octet Count for Frames Transmitted w/o Error Statistic Register
0x274
32
read-only
0
0xFFFFFFFF
COUNT
Octet count
0
32
read-only
RMON_R_PACKETS
Rx Packet Count Statistic Register
0x284
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_BC_PKT
Rx Broadcast Packets Statistic Register
0x288
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_MC_PKT
Rx Multicast Packets Statistic Register
0x28C
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_CRC_ALIGN
Rx Packets with CRC/Align Error Statistic Register
0x290
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_UNDERSIZE
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
0x294
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_OVERSIZE
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
0x298
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_FRAG
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
0x29C
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_JAB
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
0x2A0
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P64
Rx 64-Byte Packets Statistic Register
0x2A8
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P65TO127
Rx 65- to 127-Byte Packets Statistic Register
0x2AC
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P128TO255
Rx 128- to 255-Byte Packets Statistic Register
0x2B0
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P256TO511
Rx 256- to 511-Byte Packets Statistic Register
0x2B4
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P512TO1023
Rx 512- to 1023-Byte Packets Statistic Register
0x2B8
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P1024TO2047
Rx 1024- to 2047-Byte Packets Statistic Register
0x2BC
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_P_GTE2048
Rx Packets Greater than 2048 Bytes Statistic Register
0x2C0
32
read-only
0
0xFFFFFFFF
COUNT
Packet count
0
16
read-only
RMON_R_OCTETS
Rx Octets Statistic Register
0x2C4
32
read-only
0
0xFFFFFFFF
COUNT
Octet count
0
32
read-only
IEEE_R_DROP
Frames not Counted Correctly Statistic Register
0x2C8
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_R_FRAME_OK
Frames Received OK Statistic Register
0x2CC
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_R_CRC
Frames Received with CRC Error Statistic Register
0x2D0
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_R_ALIGN
Frames Received with Alignment Error Statistic Register
0x2D4
32
read-only
0
0xFFFFFFFF
COUNT
Frame count
0
16
read-only
IEEE_R_MACERR
Receive FIFO Overflow Count Statistic Register
0x2D8
32
read-only
0
0xFFFFFFFF
COUNT
Count
0
16
read-only
IEEE_R_FDXFC
Flow Control Pause Frames Received Statistic Register
0x2DC
32
read-only
0
0xFFFFFFFF
COUNT
Pause frame count
0
16
read-only
IEEE_R_OCTETS_OK
Octet Count for Frames Received without Error Statistic Register
0x2E0
32
read-only
0
0xFFFFFFFF
COUNT
Octet count
0
32
read-only
ATCR
Adjustable Timer Control Register
0x400
32
read-write
0
0xFFFFFFFF
EN
Enable Timer
0
1
read-write
0
The timer stops at the current value.
#0
1
The timer starts incrementing.
#1
OFFEN
Enable One-Shot Offset Event
2
1
read-write
0
Disable.
#0
1
The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#1
OFFRST
Reset Timer On Offset Event
3
1
read-write
0
The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
#0
1
If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#1
PEREN
Enable Periodical Event
4
1
read-write
0
Disable.
#0
1
A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#1
PINPER
Enables event signal output assertion on period event
7
1
read-write
0
Disable.
#0
1
Enable.
#1
RESTART
Reset Timer
9
1
read-write
CAPTURE
Capture Timer Value
11
1
read-write
0
No effect.
#0
1
The current time is captured and can be read from the ATVR register.
#1
SLAVE
Enable Timer Slave Mode
13
1
read-write
0
The timer is active and all configuration fields in this register are relevant.
#0
1
The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#1
ATVR
Timer Value Register
0x404
32
read-write
0
0xFFFFFFFF
ATIME
A write sets the timer
0
32
read-write
ATOFF
Timer Offset Register
0x408
32
read-write
0
0xFFFFFFFF
OFFSET
Offset value for one-shot event generation
0
32
read-write
ATPER
Timer Period Register
0x40C
32
read-write
0x3B9ACA00
0xFFFFFFFF
PERIOD
Value for generating periodic events
0
32
read-write
ATCOR
Timer Correction Register
0x410
32
read-write
0
0xFFFFFFFF
COR
Correction Counter Wrap-Around Value
0
31
read-write
ATINC
Time-Stamping Clock Period Register
0x414
32
read-write
0
0xFFFFFFFF
INC
Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
0
7
read-write
INC_CORR
Correction Increment Value
8
7
read-write
ATSTMP
Timestamp of Last Transmitted Frame
0x418
32
read-only
0
0xFFFFFFFF
TIMESTAMP
Timestamp of the last frame transmitted by the core that had TxBD[TS] set
0
32
read-only
TGSR
Timer Global Status Register
0x604
32
read-write
0
0xFFFFFFFF
TF0
Copy Of Timer Flag For Channel 0
0
1
read-write
0
Timer Flag for Channel 0 is clear
#0
1
Timer Flag for Channel 0 is set
#1
TF1
Copy Of Timer Flag For Channel 1
1
1
read-write
0
Timer Flag for Channel 1 is clear
#0
1
Timer Flag for Channel 1 is set
#1
TF2
Copy Of Timer Flag For Channel 2
2
1
read-write
0
Timer Flag for Channel 2 is clear
#0
1
Timer Flag for Channel 2 is set
#1
TF3
Copy Of Timer Flag For Channel 3
3
1
read-write
0
Timer Flag for Channel 3 is clear
#0
1
Timer Flag for Channel 3 is set
#1
4
0x8
0,1,2,3
TCSR%s
Timer Control Status Register
0x608
32
read-write
0
0xFFFFFFFF
TDRE
Timer DMA Request Enable
0
1
read-write
0
DMA request is disabled
#0
1
DMA request is enabled
#1
TMODE
Timer Mode
2
4
read-write
0000
Timer Channel is disabled.
#0000
0001
Timer Channel is configured for Input Capture on rising edge
#0001
0010
Timer Channel is configured for Input Capture on falling edge
#0010
0011
Timer Channel is configured for Input Capture on both edges
#0011
0100
Timer Channel is configured for Output Compare - software only
#0100
0101
Timer Channel is configured for Output Compare - toggle output on compare
#0101
0110
Timer Channel is configured for Output Compare - clear output on compare
#0110
0111
Timer Channel is configured for Output Compare - set output on compare
#0111
1010
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow
#1010
10x1
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow
#10x1
1110
Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle
#1110
1111
Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle
#1111
TIE
Timer Interrupt Enable
6
1
read-write
0
Interrupt is disabled
#0
1
Interrupt is enabled
#1
TF
Timer Flag
7
1
read-write
0
Input Capture or Output Compare has not occurred
#0
1
Input Capture or Output Compare has occurred
#1
4
0x8
0,1,2,3
TCCR%s
Timer Compare Capture Register
0x60C
32
read-write
0
0xFFFFFFFF
TCC
Timer Capture Compare
0
32
read-write
DAC0
12-Bit Digital-to-Analog Converter
DAC
DAC0_
0x400CC000
0
0x24
registers
DAC0
56
16
0x2
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
DAT%sL
DAC Data Low Register
0
8
read-write
0
0xFF
DATA0
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer
0
8
read-write
16
0x2
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
DAT%sH
DAC Data High Register
0x1
8
read-write
0
0xFF
DATA1
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula
0
4
read-write
SR
DAC Status Register
0x20
8
read-write
0x2
0xFF
DACBFRPBF
DAC Buffer Read Pointer Bottom Position Flag
0
1
read-write
0
The DAC buffer read pointer is not equal to C2[DACBFUP].
#0
1
The DAC buffer read pointer is equal to C2[DACBFUP].
#1
DACBFRPTF
DAC Buffer Read Pointer Top Position Flag
1
1
read-write
0
The DAC buffer read pointer is not zero.
#0
1
The DAC buffer read pointer is zero.
#1
DACBFWMF
DAC Buffer Watermark Flag
2
1
read-write
0
The DAC buffer read pointer has not reached the watermark level.
#0
1
The DAC buffer read pointer has reached the watermark level.
#1
C0
DAC Control Register
0x21
8
read-write
0
0xFF
DACBBIEN
DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0
1
read-write
0
The DAC buffer read pointer bottom flag interrupt is disabled.
#0
1
The DAC buffer read pointer bottom flag interrupt is enabled.
#1
DACBTIEN
DAC Buffer Read Pointer Top Flag Interrupt Enable
1
1
read-write
0
The DAC buffer read pointer top flag interrupt is disabled.
#0
1
The DAC buffer read pointer top flag interrupt is enabled.
#1
DACBWIEN
DAC Buffer Watermark Interrupt Enable
2
1
read-write
0
The DAC buffer watermark interrupt is disabled.
#0
1
The DAC buffer watermark interrupt is enabled.
#1
LPEN
DAC Low Power Control
3
1
read-write
0
High-Power mode
#0
1
Low-Power mode
#1
DACSWTRG
DAC Software Trigger
4
1
write-only
0
The DAC soft trigger is not valid.
#0
1
The DAC soft trigger is valid.
#1
DACTRGSEL
DAC Trigger Select
5
1
read-write
0
The DAC hardware trigger is selected.
#0
1
The DAC software trigger is selected.
#1
DACRFS
DAC Reference Select
6
1
read-write
0
The DAC selects DACREF_1 as the reference voltage.
#0
1
The DAC selects DACREF_2 as the reference voltage.
#1
DACEN
DAC Enable
7
1
read-write
0
The DAC system is disabled.
#0
1
The DAC system is enabled.
#1
C1
DAC Control Register 1
0x22
8
read-write
0
0xFF
DACBFEN
DAC Buffer Enable
0
1
read-write
0
Buffer read pointer is disabled. The converted data is always the first word of the buffer.
#0
1
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
#1
DACBFMD
DAC Buffer Work Mode Select
1
2
read-write
00
Normal mode
#00
01
Swing mode
#01
10
One-Time Scan mode
#10
DACBFWM
DAC Buffer Watermark Select
3
2
read-write
00
1 word
#00
01
2 words
#01
10
3 words
#10
11
4 words
#11
DMAEN
DMA Enable Select
7
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
#1
C2
DAC Control Register 2
0x23
8
read-write
0xF
0xFF
DACBFUP
DAC Buffer Upper Limit
0
4
read-write
DACBFRP
DAC Buffer Read Pointer
4
4
read-write
DAC1
12-Bit Digital-to-Analog Converter
DAC
DAC1_
0x400CD000
0
0x24
registers
DAC1
72
16
0x2
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
DAT%sL
DAC Data Low Register
0
8
read-write
0
0xFF
DATA0
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer
0
8
read-write
16
0x2
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
DAT%sH
DAC Data High Register
0x1
8
read-write
0
0xFF
DATA1
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula
0
4
read-write
SR
DAC Status Register
0x20
8
read-write
0x2
0xFF
DACBFRPBF
DAC Buffer Read Pointer Bottom Position Flag
0
1
read-write
0
The DAC buffer read pointer is not equal to C2[DACBFUP].
#0
1
The DAC buffer read pointer is equal to C2[DACBFUP].
#1
DACBFRPTF
DAC Buffer Read Pointer Top Position Flag
1
1
read-write
0
The DAC buffer read pointer is not zero.
#0
1
The DAC buffer read pointer is zero.
#1
DACBFWMF
DAC Buffer Watermark Flag
2
1
read-write
0
The DAC buffer read pointer has not reached the watermark level.
#0
1
The DAC buffer read pointer has reached the watermark level.
#1
C0
DAC Control Register
0x21
8
read-write
0
0xFF
DACBBIEN
DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0
1
read-write
0
The DAC buffer read pointer bottom flag interrupt is disabled.
#0
1
The DAC buffer read pointer bottom flag interrupt is enabled.
#1
DACBTIEN
DAC Buffer Read Pointer Top Flag Interrupt Enable
1
1
read-write
0
The DAC buffer read pointer top flag interrupt is disabled.
#0
1
The DAC buffer read pointer top flag interrupt is enabled.
#1
DACBWIEN
DAC Buffer Watermark Interrupt Enable
2
1
read-write
0
The DAC buffer watermark interrupt is disabled.
#0
1
The DAC buffer watermark interrupt is enabled.
#1
LPEN
DAC Low Power Control
3
1
read-write
0
High-Power mode
#0
1
Low-Power mode
#1
DACSWTRG
DAC Software Trigger
4
1
write-only
0
The DAC soft trigger is not valid.
#0
1
The DAC soft trigger is valid.
#1
DACTRGSEL
DAC Trigger Select
5
1
read-write
0
The DAC hardware trigger is selected.
#0
1
The DAC software trigger is selected.
#1
DACRFS
DAC Reference Select
6
1
read-write
0
The DAC selects DACREF_1 as the reference voltage.
#0
1
The DAC selects DACREF_2 as the reference voltage.
#1
DACEN
DAC Enable
7
1
read-write
0
The DAC system is disabled.
#0
1
The DAC system is enabled.
#1
C1
DAC Control Register 1
0x22
8
read-write
0
0xFF
DACBFEN
DAC Buffer Enable
0
1
read-write
0
Buffer read pointer is disabled. The converted data is always the first word of the buffer.
#0
1
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
#1
DACBFMD
DAC Buffer Work Mode Select
1
2
read-write
00
Normal mode
#00
01
Swing mode
#01
10
One-Time Scan mode
#10
DACBFWM
DAC Buffer Watermark Select
3
2
read-write
00
1 word
#00
01
2 words
#01
10
3 words
#10
11
4 words
#11
DMAEN
DMA Enable Select
7
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
#1
C2
DAC Control Register 2
0x23
8
read-write
0xF
0xFF
DACBFUP
DAC Buffer Upper Limit
0
4
read-write
DACBFRP
DAC Buffer Read Pointer
4
4
read-write
GPIOA
General Purpose Input/Output
GPIO
GPIOA_
0x400FF000
0
0x18
registers
PORTA
59
PDOR
Port Data Output Register
0
32
read-write
0
0xFFFFFFFF
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
0
0xFFFFFFFF
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
0
0xFFFFFFFF
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
0
0xFFFFFFFF
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PDIR
Port Data Input Register
0x10
32
read-only
0
0xFFFFFFFF
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
0
0xFFFFFFFF
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOB
General Purpose Input/Output
GPIO
GPIOB_
0x400FF040
0
0x18
registers
PORTB
60
PDOR
Port Data Output Register
0
32
read-write
0
0xFFFFFFFF
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
0
0xFFFFFFFF
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
0
0xFFFFFFFF
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
0
0xFFFFFFFF
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PDIR
Port Data Input Register
0x10
32
read-only
0
0xFFFFFFFF
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
0
0xFFFFFFFF
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOC
General Purpose Input/Output
GPIO
GPIOC_
0x400FF080
0
0x18
registers
PORTC
61
PDOR
Port Data Output Register
0
32
read-write
0
0xFFFFFFFF
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
0
0xFFFFFFFF
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
0
0xFFFFFFFF
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
0
0xFFFFFFFF
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PDIR
Port Data Input Register
0x10
32
read-only
0
0xFFFFFFFF
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
0
0xFFFFFFFF
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOD
General Purpose Input/Output
GPIO
GPIOD_
0x400FF0C0
0
0x18
registers
PORTD
62
PDOR
Port Data Output Register
0
32
read-write
0
0xFFFFFFFF
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
0
0xFFFFFFFF
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
0
0xFFFFFFFF
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
0
0xFFFFFFFF
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PDIR
Port Data Input Register
0x10
32
read-only
0
0xFFFFFFFF
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
0
0xFFFFFFFF
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOE
General Purpose Input/Output
GPIO
GPIOE_
0x400FF100
0
0x18
registers
PORTE
63
PDOR
Port Data Output Register
0
32
read-write
0
0xFFFFFFFF
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
0
0xFFFFFFFF
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
0
0xFFFFFFFF
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
0
0xFFFFFFFF
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PDIR
Port Data Input Register
0x10
32
read-only
0
0xFFFFFFFF
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
0
0xFFFFFFFF
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
SystemControl
System Control Block
SCB_
0xE000E000
0x8
0xF38
registers
ACTLR
Auxiliary Control Register,
0x8
32
read-write
0
0xFFFFFFFF
DISMCYCINT
Disables interruption of multi-cycle instructions.
0
1
read-write
DISDEFWBUF
Disables write buffer use during default memory map accesses.
1
1
read-write
DISFOLD
Disables folding of IT instructions.
2
1
read-write
CPUID
CPUID Base Register
0xD00
32
read-only
0x410FC240
0xFFFFFFFF
REVISION
Indicates patch release: 0x0 = Patch 0
0
4
read-only
PARTNO
Indicates part number
4
12
read-only
VARIANT
Indicates processor revision: 0x2 = Revision 2
20
4
read-only
IMPLEMENTER
Implementer code
24
8
read-only
ICSR
Interrupt Control and State Register
0xD04
32
read-write
0
0xFFFFFFFF
VECTACTIVE
Active exception number
0
9
read-only
RETTOBASE
no description available
11
1
read-only
0
there are preempted active exceptions to execute
#0
1
there are no active exceptions, or the currently-executing exception is the only active exception
#1
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
read-only
ISRPENDING
no description available
22
1
read-only
ISRPREEMPT
no description available
23
1
read-only
0
Will not service
#0
1
Will service a pending exception
#1
PENDSTCLR
no description available
25
1
write-only
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
no description available
26
1
read-write
0
write: no effect; read: SysTick exception is not pending
#0
1
write: changes SysTick exception state to pending; read: SysTick exception is pending
#1
PENDSVCLR
no description available
27
1
write-only
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
no description available
28
1
read-write
0
write: no effect; read: PendSV exception is not pending
#0
1
write: changes PendSV exception state to pending; read: PendSV exception is pending
#1
NMIPENDSET
no description available
31
1
read-write
0
write: no effect; read: NMI exception is not pending
#0
1
write: changes NMI exception state to pending; read: NMI exception is pending
#1
VTOR
Vector Table Offset Register
0xD08
32
read-write
0
0xFFFFFFFF
TBLOFF
Vector table base offset
7
25
read-write
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
0xFA050000
0xFFFFFFFF
VECTRESET
no description available
0
1
write-only
VECTCLRACTIVE
no description available
1
1
write-only
SYSRESETREQ
no description available
2
1
write-only
0
no system reset request
#0
1
asserts a signal to the outer system that requests a reset
#1
PRIGROUP
Interrupt priority grouping field. This field determines the split of group priority from subpriority.
8
3
read-write
ENDIANNESS
no description available
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
VECTKEY
Register key
16
16
read-write
SCR
System Control Register
0xD10
32
read-write
0
0xFFFFFFFF
SLEEPONEXIT
no description available
1
1
read-write
0
o not sleep when returning to Thread mode
#0
1
enter sleep, or deep sleep, on return from an ISR
#1
SLEEPDEEP
no description available
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SEVONPEND
no description available
4
1
read-write
0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
#1
CCR
Configuration and Control Register
0xD14
32
read-write
0
0xFFFFFFFF
NONBASETHRDENA
no description available
0
1
read-write
0
processor can enter Thread mode only when no exception is active
#0
1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
#1
USERSETMPEND
Enables unprivileged software access to the STIR
1
1
read-write
0
disable
#0
1
enable
#1
UNALIGN_TRP
Enables unaligned access traps
3
1
read-write
0
do not trap unaligned halfword and word accesses
#0
1
trap unaligned halfword and word accesses
#1
DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
4
1
read-write
0
do not trap divide by 0
#0
1
trap divide by 0
#1
BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
8
1
read-write
0
data bus faults caused by load and store instructions cause a lock-up
#0
1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
#1
STKALIGN
Indicates stack alignment on exception entry
9
1
read-write
0
4-byte aligned
#0
1
8-byte aligned
#1
SHPR1
System Handler Priority Register 1
0xD18
32
read-write
0
0xFFFFFFFF
PRI_4
Priority of system handler 4, MemManage
0
8
read-write
PRI_5
Priority of system handler 5, BusFault
8
8
read-write
PRI_6
Priority of system handler 6, UsageFault
16
8
read-write
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
0
0xFFFFFFFF
PRI_11
Priority of system handler 11, SVCall
24
8
read-write
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
0
0xFFFFFFFF
PRI_14
Priority of system handler 14, PendSV
16
8
read-write
PRI_15
Priority of system handler 15, SysTick exception
24
8
read-write
SHCSR
System Handler Control and State Register
0xD24
32
read-write
0
0xFFFFFFFF
MEMFAULTACT
no description available
0
1
read-write
0
exception is not active
#0
1
exception is active
#1
BUSFAULTACT
no description available
1
1
read-write
0
exception is not active
#0
1
exception is active
#1
USGFAULTACT
no description available
3
1
read-write
0
exception is not active
#0
1
exception is active
#1
SVCALLACT
no description available
7
1
read-write
0
exception is not active
#0
1
exception is active
#1
MONITORACT
no description available
8
1
read-write
0
exception is not active
#0
1
exception is active
#1
PENDSVACT
no description available
10
1
read-write
0
exception is not active
#0
1
exception is active
#1
SYSTICKACT
no description available
11
1
read-write
0
exception is not active
#0
1
exception is active
#1
USGFAULTPENDED
no description available
12
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
MEMFAULTPENDED
no description available
13
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
BUSFAULTPENDED
no description available
14
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
SVCALLPENDED
no description available
15
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
MEMFAULTENA
no description available
16
1
read-write
0
disable the exception
#0
1
enable the exception
#1
BUSFAULTENA
no description available
17
1
read-write
0
disable the exception
#0
1
enable the exception
#1
USGFAULTENA
no description available
18
1
read-write
0
disable the exception
#0
1
enable the exception
#1
CFSR
Configurable Fault Status Registers
0xD28
32
read-write
0
0xFFFFFFFF
IACCVIOL
no description available
0
1
read-write
0
no instruction access violation fault
#0
1
the processor attempted an instruction fetch from a location that does not permit execution
#1
DACCVIOL
no description available
1
1
read-write
0
no data access violation fault
#0
1
the processor attempted a load or store at a location that does not permit the operation
#1
MUNSTKERR
no description available
3
1
read-write
0
no unstacking fault
#0
1
unstack for an exception return has caused one or more access violations
#1
MSTKERR
no description available
4
1
read-write
0
no stacking fault
#0
1
stacking for an exception entry has caused one or more access violations
#1
MLSPERR
no description available
5
1
read-write
0
No MemManage fault occurred during floating-point lazy state preservation
#0
1
A MemManage fault occurred during floating-point lazy state preservation
#1
MMARVALID
no description available
7
1
read-write
0
value in MMAR is not a valid fault address
#0
1
MMAR holds a valid fault address
#1
IBUSERR
no description available
8
1
read-write
0
no instruction bus error
#0
1
instruction bus error
#1
PRECISERR
no description available
9
1
read-write
0
no precise data bus error
#0
1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
#1
IMPRECISERR
no description available
10
1
read-write
0
no imprecise data bus error
#0
1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
#1
UNSTKERR
no description available
11
1
read-write
0
no unstacking fault
#0
1
unstack for an exception return has caused one or more BusFaults
#1
STKERR
no description available
12
1
read-write
0
no stacking fault
#0
1
stacking for an exception entry has caused one or more BusFaults
#1
LSPERR
no description available
13
1
read-write
0
No bus fault occurred during floating-point lazy state preservation
#0
1
A bus fault occurred during floating-point lazy state preservation
#1
BFARVALID
no description available
15
1
read-write
0
value in BFAR is not a valid fault address
#0
1
BFAR holds a valid fault address
#1
UNDEFINSTR
no description available
16
1
read-write
0
no undefined instruction UsageFault
#0
1
the processor has attempted to execute an undefined instruction
#1
INVSTATE
no description available
17
1
read-write
0
no invalid state UsageFault
#0
1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
#1
INVPC
no description available
18
1
read-write
0
no invalid PC load UsageFault
#0
1
the processor has attempted an illegal load of EXC_RETURN to the PC
#1
NOCP
no description available
19
1
read-write
0
no UsageFault caused by attempting to access a coprocessor
#0
1
the processor has attempted to access a coprocessor
#1
UNALIGNED
no description available
24
1
read-write
0
no unaligned access fault, or unaligned access trapping not enabled
#0
1
the processor has made an unaligned memory access
#1
DIVBYZERO
no description available
25
1
read-write
0
no divide by zero fault, or divide by zero trapping not enabled
#0
1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
#1
HFSR
HardFault Status register
0xD2C
32
read-write
0
0xFFFFFFFF
VECTTBL
no description available
1
1
read-write
0
no BusFault on vector table read
#0
1
BusFault on vector table read
#1
FORCED
no description available
30
1
read-write
0
no forced HardFault
#0
1
forced HardFault
#1
DEBUGEVT
no description available
31
1
read-write
DFSR
Debug Fault Status Register
0xD30
32
read-write
0
0xFFFFFFFF
HALTED
no description available
0
1
read-write
0
No active halt request debug event
#0
1
Halt request debug event active
#1
BKPT
no description available
1
1
read-write
0
No current breakpoint debug event
#0
1
At least one current breakpoint debug event
#1
DWTTRAP
no description available
2
1
read-write
0
No current debug events generated by the DWT
#0
1
At least one current debug event generated by the DWT
#1
VCATCH
no description available
3
1
read-write
0
No Vector catch triggered
#0
1
Vector catch triggered
#1
EXTERNAL
no description available
4
1
read-write
0
No EDBGRQ debug event
#0
1
EDBGRQ debug event
#1
MMFAR
MemManage Address Register
0xD34
32
read-write
0
0xFFFFFFFF
ADDRESS
Address of MemManage fault location
0
32
read-write
BFAR
BusFault Address Register
0xD38
32
read-write
0
0xFFFFFFFF
ADDRESS
Address of the BusFault location
0
32
read-write
AFSR
Auxiliary Fault Status Register
0xD3C
32
read-write
0
0xFFFFFFFF
AUXFAULT
Latched version of the AUXFAULT inputs
0
32
read-write
CPACR
Coprocessor Access Control Register
0xD88
32
read-write
0
0xFFFFFFFF
CP10
Access privileges for coprocessor 10.
20
2
read-write
00
Access denied. Any attempted access generates a NOCP UsageFault
#00
01
Privileged access only. An unprivileged access generates a NOCP fault.
#01
10
Reserved. The result of any access is UNPREDICTABLE.
#10
11
Full access.
#11
CP11
Access privileges for coprocessor 11.
22
2
read-write
00
Access denied. Any attempted access generates a NOCP UsageFault
#00
01
Privileged access only. An unprivileged access generates a NOCP fault.
#01
10
Reserved. The result of any access is UNPREDICTABLE.
#10
11
Full access.
#11
FPCCR
Floating-point Context Control Register
0xF34
32
read-write
0xC0000000
0xFFFFFFFF
LSPACT
Lazy state preservation.
0
1
read-write
0
Lazy state preservation is not active.
#0
1
Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred.
#1
USER
Privilege level when the floating-point stack frame was allocated.
1
1
read-write
0
Privilege level was not user when the floating-point stack frame was allocated.
#0
1
Privilege level was user when the floating-point stack frame was allocated.
#1
THREAD
Mode when the floating-point stack frame was allocated.
3
1
read-write
0
Mode was not Thread Mode when the floating-point stack frame was allocated.
#0
1
Mode was Thread Mode when the floating-point stack frame was allocated.
#1
HFRDY
Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated.
4
1
read-write
0
Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
#0
1
Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
#1
MMRDY
Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated.
5
1
read-write
0
MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
#0
1
MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
#1
BFRDY
Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated.
6
1
read-write
0
BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
#0
1
BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
#1
MONRDY
Permission to set the MON_PEND when the floating-point stack frame was allocated.
8
1
read-write
0
DebugMonitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated.
#0
1
DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
#1
LSPEN
Lazy state preservation for floating-point context.
30
1
read-write
0
Disable automatic lazy state preservation for floating-point context.
#0
1
Enable automatic lazy state preservation for floating-point context.
#1
ASPEN
Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.
31
1
read-write
0
Disable CONTROL2 setting on execution of a floating-point instruction.
#0
1
Enable CONTROL2 setting on execution of a floating-point instruction.
#1
FPCAR
Floating-point Context Address Register
0xF38
32
read-write
0
0
ADDRESS
The location of the unpopulated floating-point register space allocated on an exception stack frame.
3
29
read-write
FPDSCR
Floating-point Default Status Control Register
0xF3C
32
read-write
0
0xFFFFFFFF
RMode
Default value for FPSCR.RMode (Rounding Mode control field).
22
2
read-write
00
Round to Nearest (RN) mode
#00
01
Round towards Plus Infinity (RP) mode.
#01
10
Round towards Minus Infinity (RM) mode.
#10
11
Round towards Zero (RZ) mode.
#11
FZ
Default value for FPSCR.FZ (Flush-to-zero mode control bit).
24
1
read-write
0
Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
#0
1
Flush-to-zero mode enabled.
#1
DN
Default value for FPSCR.DN (Default NaN mode control bit).
25
1
read-write
0
NaN operands propagate through to the output of a floating-point operation.
#0
1
Any operation involving one or more NaNs returns the Default NaN.
#1
AHP
Default value for FPSCR.AHP (Alternative half-precision control bit).
26
1
read-write
0
IEEE half-precision format selected.
#0
1
Alternative half-precision format selected.
#1
SysTick
System timer
SYST_
0xE000E010
0
0x10
registers
CSR
SysTick Control and Status Register
0
32
read-write
0x4
0xFFFFFFFF
ENABLE
no description available
0
1
read-write
0
counter disabled
#0
1
counter enabled
#1
TICKINT
no description available
1
1
read-write
0
counting down to 0 does not assert the SysTick exception request
#0
1
counting down to 0 asserts the SysTick exception request
#1
CLKSOURCE
no description available
2
1
read-write
0
external clock
#0
1
processor clock
#1
COUNTFLAG
no description available
16
1
read-write
RVR
SysTick Reload Value Register
0x4
32
read-write
0
0xFFFFFFFF
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
CVR
SysTick Current Value Register
0x8
32
read-write
0
0xFFFFFFFF
CURRENT
Current value at the time the register is accessed
0
24
read-write
CALIB
SysTick Calibration Value Register
0xC
32
read-only
0x80000000
0xFFFFFFFF
TENMS
Reload value to use for 10ms timing
0
24
read-only
SKEW
no description available
30
1
read-only
0
10ms calibration value is exact
#0
1
10ms calibration value is inexact, because of the clock frequency
#1
NOREF
no description available
31
1
read-only
0
The reference clock is provided
#0
1
The reference clock is not provided
#1
NVIC
Nested Vectored Interrupt Controller
0xE000E100
0
0xE04
registers
NVICISER0
Interrupt Set Enable Register n
0
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER1
Interrupt Set Enable Register n
0x4
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER2
Interrupt Set Enable Register n
0x8
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER3
Interrupt Set Enable Register n
0xC
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICICER0
Interrupt Clear Enable Register n
0x80
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER1
Interrupt Clear Enable Register n
0x84
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER2
Interrupt Clear Enable Register n
0x88
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER3
Interrupt Clear Enable Register n
0x8C
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICISPR0
Interrupt Set Pending Register n
0x100
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR1
Interrupt Set Pending Register n
0x104
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR2
Interrupt Set Pending Register n
0x108
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR3
Interrupt Set Pending Register n
0x10C
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICICPR0
Interrupt Clear Pending Register n
0x180
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR1
Interrupt Clear Pending Register n
0x184
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR2
Interrupt Clear Pending Register n
0x188
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR3
Interrupt Clear Pending Register n
0x18C
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICIABR0
Interrupt Active bit Register n
0x200
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR1
Interrupt Active bit Register n
0x204
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR2
Interrupt Active bit Register n
0x208
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR3
Interrupt Active bit Register n
0x20C
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIP0
Interrupt Priority Register n
0x300
8
read-write
0
0xFF
PRI0
Priority of interrupt 0
0
8
read-write
NVICIP1
Interrupt Priority Register n
0x301
8
read-write
0
0xFF
PRI1
Priority of interrupt 1
0
8
read-write
NVICIP2
Interrupt Priority Register n
0x302
8
read-write
0
0xFF
PRI2
Priority of interrupt 2
0
8
read-write
NVICIP3
Interrupt Priority Register n
0x303
8
read-write
0
0xFF
PRI3
Priority of interrupt 3
0
8
read-write
NVICIP4
Interrupt Priority Register n
0x304
8
read-write
0
0xFF
PRI4
Priority of interrupt 4
0
8
read-write
NVICIP5
Interrupt Priority Register n
0x305
8
read-write
0
0xFF
PRI5
Priority of interrupt 5
0
8
read-write
NVICIP6
Interrupt Priority Register n
0x306
8
read-write
0
0xFF
PRI6
Priority of interrupt 6
0
8
read-write
NVICIP7
Interrupt Priority Register n
0x307
8
read-write
0
0xFF
PRI7
Priority of interrupt 7
0
8
read-write
NVICIP8
Interrupt Priority Register n
0x308
8
read-write
0
0xFF
PRI8
Priority of interrupt 8
0
8
read-write
NVICIP9
Interrupt Priority Register n
0x309
8
read-write
0
0xFF
PRI9
Priority of interrupt 9
0
8
read-write
NVICIP10
Interrupt Priority Register n
0x30A
8
read-write
0
0xFF
PRI10
Priority of interrupt 10
0
8
read-write
NVICIP11
Interrupt Priority Register n
0x30B
8
read-write
0
0xFF
PRI11
Priority of interrupt 11
0
8
read-write
NVICIP12
Interrupt Priority Register n
0x30C
8
read-write
0
0xFF
PRI12
Priority of interrupt 12
0
8
read-write
NVICIP13
Interrupt Priority Register n
0x30D
8
read-write
0
0xFF
PRI13
Priority of interrupt 13
0
8
read-write
NVICIP14
Interrupt Priority Register n
0x30E
8
read-write
0
0xFF
PRI14
Priority of interrupt 14
0
8
read-write
NVICIP15
Interrupt Priority Register n
0x30F
8
read-write
0
0xFF
PRI15
Priority of interrupt 15
0
8
read-write
NVICIP16
Interrupt Priority Register n
0x310
8
read-write
0
0xFF
PRI16
Priority of interrupt 16
0
8
read-write
NVICIP17
Interrupt Priority Register n
0x311
8
read-write
0
0xFF
PRI17
Priority of interrupt 17
0
8
read-write
NVICIP18
Interrupt Priority Register n
0x312
8
read-write
0
0xFF
PRI18
Priority of interrupt 18
0
8
read-write
NVICIP19
Interrupt Priority Register n
0x313
8
read-write
0
0xFF
PRI19
Priority of interrupt 19
0
8
read-write
NVICIP20
Interrupt Priority Register n
0x314
8
read-write
0
0xFF
PRI20
Priority of interrupt 20
0
8
read-write
NVICIP21
Interrupt Priority Register n
0x315
8
read-write
0
0xFF
PRI21
Priority of interrupt 21
0
8
read-write
NVICIP22
Interrupt Priority Register n
0x316
8
read-write
0
0xFF
PRI22
Priority of interrupt 22
0
8
read-write
NVICIP23
Interrupt Priority Register n
0x317
8
read-write
0
0xFF
PRI23
Priority of interrupt 23
0
8
read-write
NVICIP24
Interrupt Priority Register n
0x318
8
read-write
0
0xFF
PRI24
Priority of interrupt 24
0
8
read-write
NVICIP25
Interrupt Priority Register n
0x319
8
read-write
0
0xFF
PRI25
Priority of interrupt 25
0
8
read-write
NVICIP26
Interrupt Priority Register n
0x31A
8
read-write
0
0xFF
PRI26
Priority of interrupt 26
0
8
read-write
NVICIP27
Interrupt Priority Register n
0x31B
8
read-write
0
0xFF
PRI27
Priority of interrupt 27
0
8
read-write
NVICIP28
Interrupt Priority Register n
0x31C
8
read-write
0
0xFF
PRI28
Priority of interrupt 28
0
8
read-write
NVICIP29
Interrupt Priority Register n
0x31D
8
read-write
0
0xFF
PRI29
Priority of interrupt 29
0
8
read-write
NVICIP30
Interrupt Priority Register n
0x31E
8
read-write
0
0xFF
PRI30
Priority of interrupt 30
0
8
read-write
NVICIP31
Interrupt Priority Register n
0x31F
8
read-write
0
0xFF
PRI31
Priority of interrupt 31
0
8
read-write
NVICIP32
Interrupt Priority Register n
0x320
8
read-write
0
0xFF
PRI32
Priority of interrupt 32
0
8
read-write
NVICIP33
Interrupt Priority Register n
0x321
8
read-write
0
0xFF
PRI33
Priority of interrupt 33
0
8
read-write
NVICIP34
Interrupt Priority Register n
0x322
8
read-write
0
0xFF
PRI34
Priority of interrupt 34
0
8
read-write
NVICIP35
Interrupt Priority Register n
0x323
8
read-write
0
0xFF
PRI35
Priority of interrupt 35
0
8
read-write
NVICIP36
Interrupt Priority Register n
0x324
8
read-write
0
0xFF
PRI36
Priority of interrupt 36
0
8
read-write
NVICIP37
Interrupt Priority Register n
0x325
8
read-write
0
0xFF
PRI37
Priority of interrupt 37
0
8
read-write
NVICIP38
Interrupt Priority Register n
0x326
8
read-write
0
0xFF
PRI38
Priority of interrupt 38
0
8
read-write
NVICIP39
Interrupt Priority Register n
0x327
8
read-write
0
0xFF
PRI39
Priority of interrupt 39
0
8
read-write
NVICIP40
Interrupt Priority Register n
0x328
8
read-write
0
0xFF
PRI40
Priority of interrupt 40
0
8
read-write
NVICIP41
Interrupt Priority Register n
0x329
8
read-write
0
0xFF
PRI41
Priority of interrupt 41
0
8
read-write
NVICIP42
Interrupt Priority Register n
0x32A
8
read-write
0
0xFF
PRI42
Priority of interrupt 42
0
8
read-write
NVICIP43
Interrupt Priority Register n
0x32B
8
read-write
0
0xFF
PRI43
Priority of interrupt 43
0
8
read-write
NVICIP44
Interrupt Priority Register n
0x32C
8
read-write
0
0xFF
PRI44
Priority of interrupt 44
0
8
read-write
NVICIP45
Interrupt Priority Register n
0x32D
8
read-write
0
0xFF
PRI45
Priority of interrupt 45
0
8
read-write
NVICIP46
Interrupt Priority Register n
0x32E
8
read-write
0
0xFF
PRI46
Priority of interrupt 46
0
8
read-write
NVICIP47
Interrupt Priority Register n
0x32F
8
read-write
0
0xFF
PRI47
Priority of interrupt 47
0
8
read-write
NVICIP48
Interrupt Priority Register n
0x330
8
read-write
0
0xFF
PRI48
Priority of interrupt 48
0
8
read-write
NVICIP49
Interrupt Priority Register n
0x331
8
read-write
0
0xFF
PRI49
Priority of interrupt 49
0
8
read-write
NVICIP50
Interrupt Priority Register n
0x332
8
read-write
0
0xFF
PRI50
Priority of interrupt 50
0
8
read-write
NVICIP51
Interrupt Priority Register n
0x333
8
read-write
0
0xFF
PRI51
Priority of interrupt 51
0
8
read-write
NVICIP52
Interrupt Priority Register n
0x334
8
read-write
0
0xFF
PRI52
Priority of interrupt 52
0
8
read-write
NVICIP53
Interrupt Priority Register n
0x335
8
read-write
0
0xFF
PRI53
Priority of interrupt 53
0
8
read-write
NVICIP54
Interrupt Priority Register n
0x336
8
read-write
0
0xFF
PRI54
Priority of interrupt 54
0
8
read-write
NVICIP55
Interrupt Priority Register n
0x337
8
read-write
0
0xFF
PRI55
Priority of interrupt 55
0
8
read-write
NVICIP56
Interrupt Priority Register n
0x338
8
read-write
0
0xFF
PRI56
Priority of interrupt 56
0
8
read-write
NVICIP57
Interrupt Priority Register n
0x339
8
read-write
0
0xFF
PRI57
Priority of interrupt 57
0
8
read-write
NVICIP58
Interrupt Priority Register n
0x33A
8
read-write
0
0xFF
PRI58
Priority of interrupt 58
0
8
read-write
NVICIP59
Interrupt Priority Register n
0x33B
8
read-write
0
0xFF
PRI59
Priority of interrupt 59
0
8
read-write
NVICIP60
Interrupt Priority Register n
0x33C
8
read-write
0
0xFF
PRI60
Priority of interrupt 60
0
8
read-write
NVICIP61
Interrupt Priority Register n
0x33D
8
read-write
0
0xFF
PRI61
Priority of interrupt 61
0
8
read-write
NVICIP62
Interrupt Priority Register n
0x33E
8
read-write
0
0xFF
PRI62
Priority of interrupt 62
0
8
read-write
NVICIP63
Interrupt Priority Register n
0x33F
8
read-write
0
0xFF
PRI63
Priority of interrupt 63
0
8
read-write
NVICIP64
Interrupt Priority Register n
0x340
8
read-write
0
0xFF
PRI64
Priority of interrupt 64
0
8
read-write
NVICIP65
Interrupt Priority Register n
0x341
8
read-write
0
0xFF
PRI65
Priority of interrupt 65
0
8
read-write
NVICIP66
Interrupt Priority Register n
0x342
8
read-write
0
0xFF
PRI66
Priority of interrupt 66
0
8
read-write
NVICIP67
Interrupt Priority Register n
0x343
8
read-write
0
0xFF
PRI67
Priority of interrupt 67
0
8
read-write
NVICIP68
Interrupt Priority Register n
0x344
8
read-write
0
0xFF
PRI68
Priority of interrupt 68
0
8
read-write
NVICIP69
Interrupt Priority Register n
0x345
8
read-write
0
0xFF
PRI69
Priority of interrupt 69
0
8
read-write
NVICIP70
Interrupt Priority Register n
0x346
8
read-write
0
0xFF
PRI70
Priority of interrupt 70
0
8
read-write
NVICIP71
Interrupt Priority Register n
0x347
8
read-write
0
0xFF
PRI71
Priority of interrupt 71
0
8
read-write
NVICIP72
Interrupt Priority Register n
0x348
8
read-write
0
0xFF
PRI72
Priority of interrupt 72
0
8
read-write
NVICIP73
Interrupt Priority Register n
0x349
8
read-write
0
0xFF
PRI73
Priority of interrupt 73
0
8
read-write
NVICIP74
Interrupt Priority Register n
0x34A
8
read-write
0
0xFF
PRI74
Priority of interrupt 74
0
8
read-write
NVICIP75
Interrupt Priority Register n
0x34B
8
read-write
0
0xFF
PRI75
Priority of interrupt 75
0
8
read-write
NVICIP76
Interrupt Priority Register n
0x34C
8
read-write
0
0xFF
PRI76
Priority of interrupt 76
0
8
read-write
NVICIP77
Interrupt Priority Register n
0x34D
8
read-write
0
0xFF
PRI77
Priority of interrupt 77
0
8
read-write
NVICIP78
Interrupt Priority Register n
0x34E
8
read-write
0
0xFF
PRI78
Priority of interrupt 78
0
8
read-write
NVICIP79
Interrupt Priority Register n
0x34F
8
read-write
0
0xFF
PRI79
Priority of interrupt 79
0
8
read-write
NVICIP80
Interrupt Priority Register n
0x350
8
read-write
0
0xFF
PRI80
Priority of interrupt 80
0
8
read-write
NVICIP81
Interrupt Priority Register n
0x351
8
read-write
0
0xFF
PRI81
Priority of interrupt 81
0
8
read-write
NVICIP82
Interrupt Priority Register n
0x352
8
read-write
0
0xFF
PRI82
Priority of interrupt 82
0
8
read-write
NVICIP83
Interrupt Priority Register n
0x353
8
read-write
0
0xFF
PRI83
Priority of interrupt 83
0
8
read-write
NVICIP84
Interrupt Priority Register n
0x354
8
read-write
0
0xFF
PRI84
Priority of interrupt 84
0
8
read-write
NVICIP85
Interrupt Priority Register n
0x355
8
read-write
0
0xFF
PRI85
Priority of interrupt 85
0
8
read-write
NVICIP86
Interrupt Priority Register n
0x356
8
read-write
0
0xFF
PRI86
Priority of interrupt 86
0
8
read-write
NVICIP87
Interrupt Priority Register n
0x357
8
read-write
0
0xFF
PRI87
Priority of interrupt 87
0
8
read-write
NVICIP88
Interrupt Priority Register n
0x358
8
read-write
0
0xFF
PRI88
Priority of interrupt 88
0
8
read-write
NVICIP89
Interrupt Priority Register n
0x359
8
read-write
0
0xFF
PRI89
Priority of interrupt 89
0
8
read-write
NVICIP90
Interrupt Priority Register n
0x35A
8
read-write
0
0xFF
PRI90
Priority of interrupt 90
0
8
read-write
NVICIP91
Interrupt Priority Register n
0x35B
8
read-write
0
0xFF
PRI91
Priority of interrupt 91
0
8
read-write
NVICIP92
Interrupt Priority Register n
0x35C
8
read-write
0
0xFF
PRI92
Priority of interrupt 92
0
8
read-write
NVICIP93
Interrupt Priority Register n
0x35D
8
read-write
0
0xFF
PRI93
Priority of interrupt 93
0
8
read-write
NVICIP94
Interrupt Priority Register n
0x35E
8
read-write
0
0xFF
PRI94
Priority of interrupt 94
0
8
read-write
NVICIP95
Interrupt Priority Register n
0x35F
8
read-write
0
0xFF
PRI95
Priority of interrupt 95
0
8
read-write
NVICIP96
Interrupt Priority Register n
0x360
8
read-write
0
0xFF
PRI96
Priority of interrupt 96
0
8
read-write
NVICIP97
Interrupt Priority Register n
0x361
8
read-write
0
0xFF
PRI97
Priority of interrupt 97
0
8
read-write
NVICIP98
Interrupt Priority Register n
0x362
8
read-write
0
0xFF
PRI98
Priority of interrupt 98
0
8
read-write
NVICIP99
Interrupt Priority Register n
0x363
8
read-write
0
0xFF
PRI99
Priority of interrupt 99
0
8
read-write
NVICIP100
Interrupt Priority Register n
0x364
8
read-write
0
0xFF
PRI100
Priority of interrupt 100
0
8
read-write
NVICIP101
Interrupt Priority Register n
0x365
8
read-write
0
0xFF
PRI101
Priority of interrupt 101
0
8
read-write
NVICIP102
Interrupt Priority Register n
0x366
8
read-write
0
0xFF
PRI102
Priority of interrupt 102
0
8
read-write
NVICIP103
Interrupt Priority Register n
0x367
8
read-write
0
0xFF
PRI103
Priority of interrupt 103
0
8
read-write
NVICIP104
Interrupt Priority Register n
0x368
8
read-write
0
0xFF
PRI104
Priority of interrupt 104
0
8
read-write
NVICIP105
Interrupt Priority Register n
0x369
8
read-write
0
0xFF
PRI105
Priority of interrupt 105
0
8
read-write
NVICSTIR
Software Trigger Interrupt Register
0xE00
32
read-write
0
0xFFFFFFFF
INTID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
read-write
MCM
Core Platform Miscellaneous Control Module
MCM_
0xE0080000
0x8
0x2C
registers
MCM
17
PLASC
Crossbar Switch (AXBS) Slave Configuration
0x8
16
read-only
0x1F
0xFFFF
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0
8
read-only
0
A bus slave connection to AXBS input port n is absent
#0
1
A bus slave connection to AXBS input port n is present
#1
PLAMC
Crossbar Switch (AXBS) Master Configuration
0xA
16
read-only
0x37
0xFFFF
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0
8
read-only
0
A bus master connection to AXBS input port n is absent
#0
1
A bus master connection to AXBS input port n is present
#1
CR
Control Register
0xC
32
read-write
0
0xFFFFFFFF
SRAMUAP
SRAM_U arbitration priority
24
2
read-write
00
Round robin
#00
01
Special round robin (favors SRAM backoor accesses over the processor)
#01
10
Fixed priority. Processor has highest, backdoor has lowest
#10
11
Fixed priority. Backdoor has highest, processor has lowest
#11
SRAMUWP
SRAM_U write protect
26
1
read-write
SRAMLAP
SRAM_L arbitration priority
28
2
read-write
00
Round robin
#00
01
Special round robin (favors SRAM backoor accesses over the processor)
#01
10
Fixed priority. Processor has highest, backdoor has lowest
#10
11
Fixed priority. Backdoor has highest, processor has lowest
#11
SRAMLWP
SRAM_L Write Protect
30
1
read-write
ISCR
Interrupt Status Register
0x10
32
read-write
0
0xFFFFFFFF
IRQ
Normal Interrupt Pending
1
1
read-write
0
No pending interrupt
#0
1
Due to the ETB counter expiring, a normal interrupt is pending
#1
NMI
Non-maskable Interrupt Pending
2
1
read-write
0
No pending NMI
#0
1
Due to the ETB counter expiring, an NMI is pending
#1
DHREQ
Debug Halt Request Indicator
3
1
read-only
0
No debug halt request
#0
1
Debug halt request initiated
#1
FIOC
FPU invalid operation interrupt status
8
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FDZC
FPU divide-by-zero interrupt status
9
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FOFC
FPU overflow interrupt status
10
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FUFC
FPU underflow interrupt status
11
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FIXC
FPU inexact interrupt status
12
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FIDC
FPU input denormal interrupt status
15
1
read-only
0
No interrupt
#0
1
Interrupt occurred
#1
FIOCE
FPU invalid operation interrupt enable
24
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
FDZCE
FPU divide-by-zero interrupt enable
25
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
FOFCE
FPU overflow interrupt enable
26
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
FUFCE
FPU underflow interrupt enable
27
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
FIXCE
FPU inexact interrupt enable
28
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
FIDCE
FPU input denormal interrupt enable
31
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
ETBCC
ETB Counter Control register
0x14
32
read-write
0
0xFFFFFFFF
CNTEN
Counter Enable
0
1
read-write
0
ETB counter disabled
#0
1
ETB counter enabled
#1
RSPT
Response Type
1
2
read-write
00
No response when the ETB count expires
#00
01
Generate a normal interrupt when the ETB count expires
#01
10
Generate an NMI when the ETB count expires
#10
11
Generate a debug halt when the ETB count expires
#11
RLRQ
Reload Request
3
1
read-write
0
No effect
#0
1
Clears pending debug halt, NMI, or IRQ interrupt requests
#1
ETDIS
ETM-To-TPIU Disable
4
1
read-write
0
ETM-to-TPIU trace path enabled
#0
1
ETM-to-TPIU trace path disabled
#1
ITDIS
ITM-To-TPIU Disable
5
1
read-write
0
ITM-to-TPIU trace path enabled
#0
1
ITM-to-TPIU trace path disabled
#1
ETBRL
ETB Reload register
0x18
32
read-write
0
0xFFFFFFFF
RELOAD
Byte Count Reload Value
0
11
read-write
ETBCNT
ETB Counter Value register
0x1C
32
read-only
0
0xFFFFFFFF
COUNTER
Byte Count Counter Value
0
11
read-only
PID
Process ID register
0x30
32
read-write
0
0xFFFFFFFF
PID
M0_PID And M1_PID For MPU
0
8
read-write
CAU
Memory Mapped Cryptographic Acceleration Unit (MMCAU)
0xE0081000
0
0xB6C
registers
CAU_DIRECT0
Direct access register 0
0
32
write-only
0
0xFFFFFFFF
CAU_DIRECT0
Direct register 0
0
32
write-only
CAU_DIRECT1
Direct access register 1
0x4
32
write-only
0
0xFFFFFFFF
CAU_DIRECT1
Direct register 1
0
32
write-only
CAU_DIRECT2
Direct access register 2
0x8
32
write-only
0
0xFFFFFFFF
CAU_DIRECT2
Direct register 2
0
32
write-only
CAU_DIRECT3
Direct access register 3
0xC
32
write-only
0
0xFFFFFFFF
CAU_DIRECT3
Direct register 3
0
32
write-only
CAU_DIRECT4
Direct access register 4
0x10
32
write-only
0
0xFFFFFFFF
CAU_DIRECT4
Direct register 4
0
32
write-only
CAU_DIRECT5
Direct access register 5
0x14
32
write-only
0
0xFFFFFFFF
CAU_DIRECT5
Direct register 5
0
32
write-only
CAU_DIRECT6
Direct access register 6
0x18
32
write-only
0
0xFFFFFFFF
CAU_DIRECT6
Direct register 6
0
32
write-only
CAU_DIRECT7
Direct access register 7
0x1C
32
write-only
0
0xFFFFFFFF
CAU_DIRECT7
Direct register 7
0
32
write-only
CAU_DIRECT8
Direct access register 8
0x20
32
write-only
0
0xFFFFFFFF
CAU_DIRECT8
Direct register 8
0
32
write-only
CAU_DIRECT9
Direct access register 9
0x24
32
write-only
0
0xFFFFFFFF
CAU_DIRECT9
Direct register 9
0
32
write-only
CAU_DIRECT10
Direct access register 10
0x28
32
write-only
0
0xFFFFFFFF
CAU_DIRECT10
Direct register 10
0
32
write-only
CAU_DIRECT11
Direct access register 11
0x2C
32
write-only
0
0xFFFFFFFF
CAU_DIRECT11
Direct register 11
0
32
write-only
CAU_DIRECT12
Direct access register 12
0x30
32
write-only
0
0xFFFFFFFF
CAU_DIRECT12
Direct register 12
0
32
write-only
CAU_DIRECT13
Direct access register 13
0x34
32
write-only
0
0xFFFFFFFF
CAU_DIRECT13
Direct register 13
0
32
write-only
CAU_DIRECT14
Direct access register 14
0x38
32
write-only
0
0xFFFFFFFF
CAU_DIRECT14
Direct register 14
0
32
write-only
CAU_DIRECT15
Direct access register 15
0x3C
32
write-only
0
0xFFFFFFFF
CAU_DIRECT15
Direct register 15
0
32
write-only
CAU_LDR_CASR
Status register - Load Register command
0x840
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_LDR_CAA
Accumulator register - Load Register command
0x844
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_LDR_CA0
General Purpose Register 0 - Load Register command
0x848
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_LDR_CA1
General Purpose Register 1 - Load Register command
0x84C
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_LDR_CA2
General Purpose Register 2 - Load Register command
0x850
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_LDR_CA3
General Purpose Register 3 - Load Register command
0x854
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_LDR_CA4
General Purpose Register 4 - Load Register command
0x858
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_LDR_CA5
General Purpose Register 5 - Load Register command
0x85C
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_LDR_CA6
General Purpose Register 6 - Load Register command
0x860
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_LDR_CA7
General Purpose Register 7 - Load Register command
0x864
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_LDR_CA8
General Purpose Register 8 - Load Register command
0x868
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_STR_CASR
Status register - Store Register command
0x880
32
read-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
read-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
read-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
read-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_STR_CAA
Accumulator register - Store Register command
0x884
32
read-only
0
0xFFFFFFFF
ACC
ACC
0
32
read-only
CAU_STR_CA0
General Purpose Register 0 - Store Register command
0x888
32
read-only
0
0xFFFFFFFF
CA0
CA0
0
32
read-only
CAU_STR_CA1
General Purpose Register 1 - Store Register command
0x88C
32
read-only
0
0xFFFFFFFF
CA1
CA1
0
32
read-only
CAU_STR_CA2
General Purpose Register 2 - Store Register command
0x890
32
read-only
0
0xFFFFFFFF
CA2
CA2
0
32
read-only
CAU_STR_CA3
General Purpose Register 3 - Store Register command
0x894
32
read-only
0
0xFFFFFFFF
CA3
CA3
0
32
read-only
CAU_STR_CA4
General Purpose Register 4 - Store Register command
0x898
32
read-only
0
0xFFFFFFFF
CA4
CA4
0
32
read-only
CAU_STR_CA5
General Purpose Register 5 - Store Register command
0x89C
32
read-only
0
0xFFFFFFFF
CA5
CA5
0
32
read-only
CAU_STR_CA6
General Purpose Register 6 - Store Register command
0x8A0
32
read-only
0
0xFFFFFFFF
CA6
CA6
0
32
read-only
CAU_STR_CA7
General Purpose Register 7 - Store Register command
0x8A4
32
read-only
0
0xFFFFFFFF
CA7
CA7
0
32
read-only
CAU_STR_CA8
General Purpose Register 8 - Store Register command
0x8A8
32
read-only
0
0xFFFFFFFF
CA8
CA8
0
32
read-only
CAU_ADR_CASR
Status register - Add Register command
0x8C0
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_ADR_CAA
Accumulator register - Add to register command
0x8C4
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_ADR_CA0
General Purpose Register 0 - Add to register command
0x8C8
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_ADR_CA1
General Purpose Register 1 - Add to register command
0x8CC
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_ADR_CA2
General Purpose Register 2 - Add to register command
0x8D0
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_ADR_CA3
General Purpose Register 3 - Add to register command
0x8D4
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_ADR_CA4
General Purpose Register 4 - Add to register command
0x8D8
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_ADR_CA5
General Purpose Register 5 - Add to register command
0x8DC
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_ADR_CA6
General Purpose Register 6 - Add to register command
0x8E0
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_ADR_CA7
General Purpose Register 7 - Add to register command
0x8E4
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_ADR_CA8
General Purpose Register 8 - Add to register command
0x8E8
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_RADR_CASR
Status register - Reverse and Add to Register command
0x900
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_RADR_CAA
Accumulator register - Reverse and Add to Register command
0x904
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_RADR_CA0
General Purpose Register 0 - Reverse and Add to Register command
0x908
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_RADR_CA1
General Purpose Register 1 - Reverse and Add to Register command
0x90C
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_RADR_CA2
General Purpose Register 2 - Reverse and Add to Register command
0x910
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_RADR_CA3
General Purpose Register 3 - Reverse and Add to Register command
0x914
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_RADR_CA4
General Purpose Register 4 - Reverse and Add to Register command
0x918
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_RADR_CA5
General Purpose Register 5 - Reverse and Add to Register command
0x91C
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_RADR_CA6
General Purpose Register 6 - Reverse and Add to Register command
0x920
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_RADR_CA7
General Purpose Register 7 - Reverse and Add to Register command
0x924
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_RADR_CA8
General Purpose Register 8 - Reverse and Add to Register command
0x928
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_XOR_CASR
Status register - Exclusive Or command
0x980
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_XOR_CAA
Accumulator register - Exclusive Or command
0x984
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_XOR_CA0
General Purpose Register 0 - Exclusive Or command
0x988
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_XOR_CA1
General Purpose Register 1 - Exclusive Or command
0x98C
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_XOR_CA2
General Purpose Register 2 - Exclusive Or command
0x990
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_XOR_CA3
General Purpose Register 3 - Exclusive Or command
0x994
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_XOR_CA4
General Purpose Register 4 - Exclusive Or command
0x998
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_XOR_CA5
General Purpose Register 5 - Exclusive Or command
0x99C
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_XOR_CA6
General Purpose Register 6 - Exclusive Or command
0x9A0
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_XOR_CA7
General Purpose Register 7 - Exclusive Or command
0x9A4
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_XOR_CA8
General Purpose Register 8 - Exclusive Or command
0x9A8
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_ROTL_CASR
Status register - Rotate Left command
0x9C0
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_ROTL_CAA
Accumulator register - Rotate Left command
0x9C4
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_ROTL_CA0
General Purpose Register 0 - Rotate Left command
0x9C8
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_ROTL_CA1
General Purpose Register 1 - Rotate Left command
0x9CC
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_ROTL_CA2
General Purpose Register 2 - Rotate Left command
0x9D0
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_ROTL_CA3
General Purpose Register 3 - Rotate Left command
0x9D4
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_ROTL_CA4
General Purpose Register 4 - Rotate Left command
0x9D8
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_ROTL_CA5
General Purpose Register 5 - Rotate Left command
0x9DC
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_ROTL_CA6
General Purpose Register 6 - Rotate Left command
0x9E0
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_ROTL_CA7
General Purpose Register 7 - Rotate Left command
0x9E4
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_ROTL_CA8
General Purpose Register 8 - Rotate Left command
0x9E8
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_AESC_CASR
Status register - AES Column Operation command
0xB00
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_AESC_CAA
Accumulator register - AES Column Operation command
0xB04
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_AESC_CA0
General Purpose Register 0 - AES Column Operation command
0xB08
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_AESC_CA1
General Purpose Register 1 - AES Column Operation command
0xB0C
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_AESC_CA2
General Purpose Register 2 - AES Column Operation command
0xB10
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_AESC_CA3
General Purpose Register 3 - AES Column Operation command
0xB14
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_AESC_CA4
General Purpose Register 4 - AES Column Operation command
0xB18
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_AESC_CA5
General Purpose Register 5 - AES Column Operation command
0xB1C
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_AESC_CA6
General Purpose Register 6 - AES Column Operation command
0xB20
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_AESC_CA7
General Purpose Register 7 - AES Column Operation command
0xB24
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_AESC_CA8
General Purpose Register 8 - AES Column Operation command
0xB28
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only
CAU_AESIC_CASR
Status register - AES Inverse Column Operation command
0xB40
32
write-only
0x20000000
0xFFFFFFFF
IC
no description available
0
1
write-only
0
No illegal commands issued
#0
1
Illegal command issued
#1
DPE
no description available
1
1
write-only
0
No error detected
#0
1
DES key parity error detected
#1
VER
CAU version
28
4
write-only
0001
Initial CAU version
#0001
0010
Second version, added support for SHA-256 algorithm.(This is the value on this device)
#0010
CAU_AESIC_CAA
Accumulator register - AES Inverse Column Operation command
0xB44
32
write-only
0
0xFFFFFFFF
ACC
ACC
0
32
write-only
CAU_AESIC_CA0
General Purpose Register 0 - AES Inverse Column Operation command
0xB48
32
write-only
0
0xFFFFFFFF
CA0
CA0
0
32
write-only
CAU_AESIC_CA1
General Purpose Register 1 - AES Inverse Column Operation command
0xB4C
32
write-only
0
0xFFFFFFFF
CA1
CA1
0
32
write-only
CAU_AESIC_CA2
General Purpose Register 2 - AES Inverse Column Operation command
0xB50
32
write-only
0
0xFFFFFFFF
CA2
CA2
0
32
write-only
CAU_AESIC_CA3
General Purpose Register 3 - AES Inverse Column Operation command
0xB54
32
write-only
0
0xFFFFFFFF
CA3
CA3
0
32
write-only
CAU_AESIC_CA4
General Purpose Register 4 - AES Inverse Column Operation command
0xB58
32
write-only
0
0xFFFFFFFF
CA4
CA4
0
32
write-only
CAU_AESIC_CA5
General Purpose Register 5 - AES Inverse Column Operation command
0xB5C
32
write-only
0
0xFFFFFFFF
CA5
CA5
0
32
write-only
CAU_AESIC_CA6
General Purpose Register 6 - AES Inverse Column Operation command
0xB60
32
write-only
0
0xFFFFFFFF
CA6
CA6
0
32
write-only
CAU_AESIC_CA7
General Purpose Register 7 - AES Inverse Column Operation command
0xB64
32
write-only
0
0xFFFFFFFF
CA7
CA7
0
32
write-only
CAU_AESIC_CA8
General Purpose Register 8 - AES Inverse Column Operation command
0xB68
32
write-only
0
0xFFFFFFFF
CA8
CA8
0
32
write-only