control_ak4558.h 8.2KB

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  1. /*
  2. * HiFi Audio Codec Module support library for Teensy 3.x
  3. *
  4. * Copyright 2015, Michele Perla
  5. *
  6. */
  7. #ifndef control_ak4558_h_
  8. #define control_ak4558_h_
  9. #include "AudioControl.h"
  10. #define AK4558_SERIAL_DEBUG 1
  11. //if 1, then Serial Monitor will show debug information about configuration of the AK4558
  12. // for Teensy audio lib operation the following settings are needed
  13. // 1fs = 44.1 KHz
  14. // sample size = 16 bits
  15. // MCKI : 11.2896 MHz
  16. // BICK : 1.4112 MHz
  17. // LRCK : 44.100 KHz
  18. // to do so we need to set the following bits:
  19. // PMPLL = 0 (EXT Slave Mode; disables internal PLL and uses ext. clock) (by DEFAULT)
  20. // ACKS = 0 (Manual Setting Mode; disables automatic clock selection) (by DEFAULT)
  21. // DFS1-0 = 00 (Sampling Speed = Normal Speed Mode, default)
  22. // MCKS1-0 = 00 (Master Clock Input Frequency Select, set 256fs for Normal Speed Mode -> 11.2896 MHz)
  23. // BCKO1-0 = 00 (BICK Output Frequency at Master Mode = 32fs = 1.4112 MHz)
  24. // TDM1-0 = 00 (Time Division Multiplexing mode OFF) (by DEFAULT)
  25. // DIF2-1-0 = 011 ( 16 bit I2S compatible when BICK = 32fs)
  26. #ifndef PIN_PDN
  27. #define PIN_PDN 1
  28. #endif
  29. // Power-Down & Reset Mode Pin
  30. // “L”: Power-down and Reset, “H”: Normal operation
  31. // The AK4558 should be reset once by bringing PDN pin = “L”
  32. #ifndef AK4558_CAD1
  33. #define AK4558_CAD1 1
  34. #endif
  35. // Chip Address 1 pin
  36. // set to 'H' by default, configurable to 'L' via a jumper on bottom side of the board
  37. #ifndef AK4558_CAD0
  38. #define AK4558_CAD0 1
  39. #endif
  40. // Chip Address 0 pin
  41. // set to 'H' by default, configurable to 'L' via a jumper on bottom side of the board
  42. #define AK4558_I2C_ADDR (0x10 + (AK4558_CAD1<<1) + AK4558_CAD0)
  43. // datasheet page 81:
  44. // This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
  45. // The most significant five bits of the slave address are fixed as “00100”. The next bits are
  46. // CAD1 and CAD0 (device address bit). These bits identify the specific device on the bus.
  47. // The hard-wired input pins (CAD1 and CAD0) set these device address bits (Figure 69)
  48. // Power Management register
  49. #define AK4558_PWR_MNGT 0x00
  50. // D4 D3 D2 D1 D0
  51. // PMADR PMADL PMDAR PMDAL RSTN
  52. #define AK4558_PMADR (1u<<4)
  53. #define AK4558_PMADL (1u<<3)
  54. // PMADL/R: ADC L/Rch Power Management
  55. // 0: ADC L/Rch Power Down (default)
  56. // 1: Normal Operation
  57. #define AK4558_PMDAR (1u<<2)
  58. #define AK4558_PMDAL (1u<<1)
  59. // PMDAL/R: DAC L/Rch Power Management
  60. // 0: DAC L/Rch Power Down (default)
  61. // 1: Normal Operation
  62. #define AK4558_RSTN (1u)
  63. // RSTN: Internal Timing Reset
  64. // 0: Reset Register values are not reset.
  65. // 1: Normal Operation (default)
  66. // PLL Control register
  67. #define AK4558_PLL_CTRL 0X01
  68. // D4 D3 D2 D1 D0
  69. // PLL3 PLL2 PLL1 PLL0 PMPLL
  70. #define AK4558_PLL3 (1u<<4)
  71. #define AK4558_PLL2 (1u<<3)
  72. #define AK4558_PLL1 (1u<<2)
  73. #define AK4558_PLL0 (1u<<1)
  74. // PLL3-0: PLL Reference Clock Select (Table 16)
  75. // Default: “0010” (BICK pin=64fs)
  76. #define AK4558_PMPLL (1u)
  77. // PMPLL: PLL Power Management
  78. // 0: EXT Mode and Power down (default)
  79. // 1: PLL Mode and Power up
  80. // DAC TDM register
  81. #define AK4558_DAC_TDM 0X02
  82. // D1 D0
  83. // SDS1 SDS0
  84. #define AK4558_SDS1 (1u<<1)
  85. #define AK4558_SDS0 (1u)
  86. // SDS1-0: DAC TDM Data Select (Table 24)
  87. // Default: “00”
  88. // Control 1 register
  89. #define AK4558_CTRL_1 0X03
  90. // D7 D6 D5 D4 D3 D2 D1 D0
  91. // TDM1 TDM0 DIF2 DIF1 DIF0 ATS1 ATS0 SMUTE
  92. #define AK4558_TDM1 (1u<<7)
  93. #define AK4558_TDM0 (1u<<6)
  94. // TDM1-0: TDM Format Select (Table 23, Table 25, Table 26)
  95. // Default: “00” (Stereo Mode)
  96. #define AK4558_DIF2 (1u<<5)
  97. #define AK4558_DIF1 (1u<<4)
  98. #define AK4558_DIF0 (1u<<3)
  99. // DIF2-0: Audio Interface Format Mode Select (Table 23)
  100. // Default: “111” (32bit I2S)
  101. #define AK4558_ATS1 (1u<<2)
  102. #define AK4558_ATS0 (1u<<1)
  103. // ATS1-0: Transition Time Setting of Digital Attenuator (Table 31)
  104. // Default: “00”
  105. #define AK4558_SMUTE (1u)
  106. // SMUTE: Soft Mute Enable
  107. // 0: Normal Operation (default)
  108. // 1: All DAC outputs are soft muted.
  109. // Control 2 register
  110. #define AK4558_CTRL_2 0X04
  111. // D4 D3 D2 D1 D0
  112. // MCKS1 MCKS0 DFS1 DFS0 ACKS
  113. #define AK4558_MCKS1 (1u<<4)
  114. #define AK4558_MCKS0 (1u<<3)
  115. // MCKS1-0: Master Clock Input Frequency Select (Table 9, follows):
  116. // MCKS1 MCKS0 NSM DSM QSM
  117. // 0 0 256fs 256fs 128fs
  118. // 0 1 384fs 256fs 128fs
  119. // 1 0 512fs 256fs 128fs (default)
  120. // 1 1 768fs 256fs 128fs
  121. #define AK4558_DFS1 (1u<<2)
  122. #define AK4558_DFS0 (1u<<1)
  123. // DFS1-0: Sampling Speed Control (Table 8)
  124. // The setting of DFS1-0 bits is ignored when ACKS bit =“1”.
  125. #define AK4558_ACKS (1u)
  126. // ACKS: Automatic Clock Recognition Mode
  127. // 0: Disable, Manual Setting Mode (default)
  128. // 1: Enable, Auto Setting Mode
  129. // When ACKS bit = “1”, master clock frequency is detected automatically. In this case, the setting of
  130. // DFS1-0 bits is ignored. When ACKS bit = “0”, DFS1-0 bits set the sampling speed mode. The MCKI
  131. // frequency of each mode is detected automatically.
  132. // Mode Control register
  133. #define AK4558_MODE_CTRL 0X05
  134. // D6 D5 D4 D3 D2 D1 D0
  135. // FS3 FS2 FS1 FS0 BCKO1 BCKO0 LOPS
  136. #define AK4558_FS3 (1u<<6)
  137. #define AK4558_FS2 (1u<<5)
  138. #define AK4558_FS1 (1u<<4)
  139. #define AK4558_FS0 (1u<<3)
  140. // FS3-0: Sampling Frequency (Table 17, Table 18)
  141. // Default: “0101”
  142. #define AK4558_BCKO1 (1u<<2)
  143. #define AK4558_BCKO0 (1u<<1)
  144. // BCKO1-0: BICK Output Frequency Setting in Master Mode (Table 21)
  145. // Default: “01” (64fs)
  146. #define AK4558_LOPS (1u<<0)
  147. // LOPS: Power-save Mode of LOUT/ROUT
  148. // 0: Normal Operation (default)
  149. // 1: Power-save Mode
  150. // Filter Setting register
  151. #define AK4558_FLTR_SET 0x06
  152. // D7 D6 D5 D4 D3 D2 D1 D0
  153. // FIRDA2 FIRDA1 FIRDA0 SLDA SDDA SSLOW DEM1 DEM0
  154. #define AK4558_FIRDA2 (1u<<7)
  155. #define AK4558_FIRDA1 (1u<<6)
  156. #define AK4558_FIRDA0 (1u<<5)
  157. // FIRDA2-0: Out band noise eliminating Filters Setting (Table 32)
  158. // default: “001” (48kHz)
  159. #define AK4558_SLDA (1u<<4)
  160. // SLDA: DAC Slow Roll-off Filter Enable (Table 28)
  161. // 0: Sharp Roll-off filter (default)
  162. // 1: Slow Roll-off Filter
  163. #define AK4558_SDDA (1u<<3)
  164. // SDDA: DAC Short delay Filter Enable (Table 28)
  165. // 0: Normal filter
  166. // 1: Short delay Filter (default)
  167. #define AK4558_SSLOW (1u<<2)
  168. // SSLOW: Digital Filter Bypass Mode Enable
  169. // 0: Roll-off filter (default)
  170. // 1: Super Slow Roll-off Mode
  171. #define AK4558_DEM1 (1u<<1)
  172. #define AK4558_DEM0 (1u)
  173. // DEM1-0: De-emphasis response control for DAC (Table 22)
  174. // Default: “01”, OFF
  175. // HPF Enable, Filter Setting
  176. #define AK4558_HPF_EN_FLTR_SET 0x07
  177. // D3 D2 D1 D0
  178. // SLAD SDAD HPFER HPFEL
  179. #define AK4558_SLAD (1u<<3)
  180. // SLAD: ADC Slow Roll-off Filter Enable (Table 27)
  181. // 0: Sharp Roll-off filter (default)
  182. // 1: Slow Roll-off Filter
  183. #define AK4558_SDAD (1u<<2)
  184. // SDAD: ADC Short delay Filter Enable (Table 27)
  185. // 0: Normal filter
  186. // 1: Short delay Filter (default)
  187. #define AK4558_HPFER (1u<<1)
  188. #define AK4558_HPFEL (1u)
  189. // HPFEL/R: ADC HPF L/Rch Setting
  190. // 0: HPF L/Rch OFF
  191. // 1: HPF L/Rch ON (default)
  192. // LOUT Volume Control register
  193. #define AK4558_LOUT_VOL 0X08
  194. // D7 D6 D5 D4 D3 D2 D1 D0
  195. // ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
  196. //
  197. // ATL 7-0: Attenuation Level (Table 30)
  198. // Default:FF(0dB)
  199. // ROUT Volume Control register
  200. #define AK4558_ROUT_VOL 0X09
  201. // D7 D6 D5 D4 D3 D2 D1 D0
  202. // ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
  203. //
  204. // ATR 7-0: Attenuation Level (Table 30)
  205. // Default:FF(0dB)
  206. class AudioControlAK4558 : public AudioControl
  207. {
  208. public:
  209. bool enable(void); //enables the CODEC, does not power up ADC nor DAC (use enableIn() and enableOut() for selective power up)
  210. bool enableIn(void); //powers up ADC
  211. bool enableOut(void); //powers up DAC
  212. bool disable(void) { return (disableIn()&&disableOut()); } //powers down ADC/DAC
  213. bool disableIn(void); //powers down ADC
  214. bool disableOut(void); //powers down DAC
  215. bool volume(float n); //sets LOUT/ROUT volume to n (range 0.0 - 1.0)
  216. bool volumeLeft(float n); //sets LOUT volume to n (range 0.0 - 1.0)
  217. bool volumeRight(float n); //sets ROUT volume to n (range 0.0 - 1.0)
  218. bool inputLevel(float n) { return false; } //not supported by AK4558
  219. bool inputSelect(int n) { return false; } //sets inputs to mono left, mono right, stereo (default stereo), not yet implemented
  220. private:
  221. uint8_t registers[10];
  222. void initConfig(void);
  223. void readConfig(void);
  224. bool write(unsigned int reg, unsigned int val);
  225. uint8_t convertVolume(float vol);
  226. };
  227. #endif