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  1. #include "Audio.h"
  2. #include "arm_math.h"
  3. // MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
  4. // Possible to create using fractional divider for all USB-compatible Kinetis:
  5. // MCLK = 16e6 * 12 / 17
  6. // MCLK = 24e6 * 8 / 17
  7. // MCLK = 48e6 * 4 / 17
  8. // MCLK = 72e6 * 8 / 51
  9. // MCLK = 96e6 * 2 / 17
  10. // MCLK = 120e6 * 8 / 85
  11. // TODO: instigate using I2S0_MCR to select the crystal directly instead of the system
  12. // clock, which has audio band jitter from the PLL
  13. audio_block_t * AudioOutputI2S::block_left_1st = NULL;
  14. audio_block_t * AudioOutputI2S::block_right_1st = NULL;
  15. audio_block_t * AudioOutputI2S::block_left_2nd = NULL;
  16. audio_block_t * AudioOutputI2S::block_right_2nd = NULL;
  17. uint16_t AudioOutputI2S::block_left_offset = 0;
  18. uint16_t AudioOutputI2S::block_right_offset = 0;
  19. bool AudioOutputI2S::update_responsibility = false;
  20. DMAMEM static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  21. void AudioOutputI2S::begin(void)
  22. {
  23. //pinMode(2, OUTPUT);
  24. block_left_1st = NULL;
  25. block_right_1st = NULL;
  26. config_i2s();
  27. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  28. DMA_CR = 0;
  29. DMA_TCD0_SADDR = i2s_tx_buffer;
  30. DMA_TCD0_SOFF = 2;
  31. DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  32. DMA_TCD0_NBYTES_MLNO = 2;
  33. DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer);
  34. DMA_TCD0_DADDR = &I2S0_TDR0;
  35. DMA_TCD0_DOFF = 0;
  36. DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  37. DMA_TCD0_DLASTSGA = 0;
  38. DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  39. DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  40. DMAMUX0_CHCFG0 = DMAMUX_DISABLE;
  41. DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE;
  42. update_responsibility = update_setup();
  43. DMA_SERQ = 0;
  44. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
  45. NVIC_ENABLE_IRQ(IRQ_DMA_CH0);
  46. }
  47. void dma_ch0_isr(void)
  48. {
  49. const int16_t *src, *end;
  50. int16_t *dest;
  51. audio_block_t *block;
  52. uint32_t saddr, offset;
  53. saddr = (uint32_t)DMA_TCD0_SADDR;
  54. DMA_CINT = 0;
  55. if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
  56. // DMA is transmitting the first half of the buffer
  57. // so we must fill the second half
  58. dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  59. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  60. if (AudioOutputI2S::update_responsibility) AudioStream::update_all();
  61. } else {
  62. // DMA is transmitting the second half of the buffer
  63. // so we must fill the first half
  64. dest = (int16_t *)i2s_tx_buffer;
  65. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  66. }
  67. // TODO: these copy routines could be merged and optimized, maybe in assembly?
  68. block = AudioOutputI2S::block_left_1st;
  69. if (block) {
  70. offset = AudioOutputI2S::block_left_offset;
  71. src = &block->data[offset];
  72. do {
  73. *dest = *src++;
  74. dest += 2;
  75. } while (dest < end);
  76. offset += AUDIO_BLOCK_SAMPLES/2;
  77. if (offset < AUDIO_BLOCK_SAMPLES) {
  78. AudioOutputI2S::block_left_offset = offset;
  79. } else {
  80. AudioOutputI2S::block_left_offset = 0;
  81. AudioStream::release(block);
  82. AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd;
  83. AudioOutputI2S::block_left_2nd = NULL;
  84. }
  85. } else {
  86. do {
  87. *dest = 0;
  88. dest += 2;
  89. } while (dest < end);
  90. }
  91. dest -= AUDIO_BLOCK_SAMPLES - 1;
  92. block = AudioOutputI2S::block_right_1st;
  93. if (block) {
  94. offset = AudioOutputI2S::block_right_offset;
  95. src = &block->data[offset];
  96. do {
  97. *dest = *src++;
  98. dest += 2;
  99. } while (dest < end);
  100. offset += AUDIO_BLOCK_SAMPLES/2;
  101. if (offset < AUDIO_BLOCK_SAMPLES) {
  102. AudioOutputI2S::block_right_offset = offset;
  103. } else {
  104. AudioOutputI2S::block_right_offset = 0;
  105. AudioStream::release(block);
  106. AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd;
  107. AudioOutputI2S::block_right_2nd = NULL;
  108. }
  109. } else {
  110. do {
  111. *dest = 0;
  112. dest += 2;
  113. } while (dest < end);
  114. }
  115. }
  116. void AudioOutputI2S::update(void)
  117. {
  118. // null audio device: discard all incoming data
  119. //if (!active) return;
  120. //audio_block_t *block = receiveReadOnly();
  121. //if (block) release(block);
  122. audio_block_t *block;
  123. block = receiveReadOnly(0); // input 0 = left channel
  124. if (block) {
  125. __disable_irq();
  126. if (block_left_1st == NULL) {
  127. block_left_1st = block;
  128. block_left_offset = 0;
  129. __enable_irq();
  130. } else if (block_left_2nd == NULL) {
  131. block_left_2nd = block;
  132. __enable_irq();
  133. } else {
  134. audio_block_t *tmp = block_left_1st;
  135. block_left_1st = block_left_2nd;
  136. block_left_2nd = block;
  137. block_left_offset = 0;
  138. __enable_irq();
  139. release(tmp);
  140. }
  141. }
  142. block = receiveReadOnly(1); // input 1 = right channel
  143. if (block) {
  144. __disable_irq();
  145. if (block_right_1st == NULL) {
  146. block_right_1st = block;
  147. block_right_offset = 0;
  148. __enable_irq();
  149. } else if (block_right_2nd == NULL) {
  150. block_right_2nd = block;
  151. __enable_irq();
  152. } else {
  153. audio_block_t *tmp = block_right_1st;
  154. block_right_1st = block_right_2nd;
  155. block_right_2nd = block;
  156. block_right_offset = 0;
  157. __enable_irq();
  158. release(tmp);
  159. }
  160. }
  161. }
  162. void AudioOutputI2S::config_i2s(void)
  163. {
  164. SIM_SCGC6 |= SIM_SCGC6_I2S;
  165. SIM_SCGC7 |= SIM_SCGC7_DMA;
  166. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  167. // if either transmitter or receiver is enabled, do nothing
  168. if (I2S0_TCSR & I2S_TCSR_TE) return;
  169. if (I2S0_RCSR & I2S_RCSR_RE) return;
  170. // enable MCLK output
  171. I2S0_MCR = I2S_MCR_MICS(3) | I2S_MCR_MOE;
  172. I2S0_MDR = I2S_MDR_FRACT(1) | I2S_MDR_DIVIDE(16);
  173. // configure transmitter
  174. I2S0_TMR = 0;
  175. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  176. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  177. | I2S_TCR2_BCD | I2S_TCR2_DIV(3);
  178. I2S0_TCR3 = I2S_TCR3_TCE;
  179. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
  180. | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
  181. I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
  182. // configure receiver (sync'd to transmitter clocks)
  183. I2S0_RMR = 0;
  184. I2S0_RCR1 = I2S_RCR1_RFW(1);
  185. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  186. | I2S_RCR2_BCD | I2S_RCR2_DIV(3);
  187. I2S0_RCR3 = I2S_RCR3_RCE;
  188. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
  189. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  190. I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
  191. // configure pin mux for 3 clock signals
  192. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  193. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  194. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  195. }
  196. /******************************************************************/
  197. void AudioOutputI2Sslave::begin(void)
  198. {
  199. //pinMode(2, OUTPUT);
  200. block_left_1st = NULL;
  201. block_right_1st = NULL;
  202. AudioOutputI2Sslave::config_i2s();
  203. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  204. DMA_CR = 0;
  205. DMA_TCD0_SADDR = i2s_tx_buffer;
  206. DMA_TCD0_SOFF = 2;
  207. DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  208. DMA_TCD0_NBYTES_MLNO = 2;
  209. DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer);
  210. DMA_TCD0_DADDR = &I2S0_TDR0;
  211. DMA_TCD0_DOFF = 0;
  212. DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  213. DMA_TCD0_DLASTSGA = 0;
  214. DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  215. DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  216. DMAMUX0_CHCFG0 = DMAMUX_DISABLE;
  217. DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE;
  218. update_responsibility = update_setup();
  219. DMA_SERQ = 0;
  220. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
  221. NVIC_ENABLE_IRQ(IRQ_DMA_CH0);
  222. }
  223. void AudioOutputI2Sslave::config_i2s(void)
  224. {
  225. SIM_SCGC6 |= SIM_SCGC6_I2S;
  226. SIM_SCGC7 |= SIM_SCGC7_DMA;
  227. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  228. // if either transmitter or receiver is enabled, do nothing
  229. if (I2S0_TCSR & I2S_TCSR_TE) return;
  230. if (I2S0_RCSR & I2S_RCSR_RE) return;
  231. // Select input clock 0
  232. // Configure to input the bit-clock from pin, bypasses the MCLK divider
  233. I2S0_MCR = I2S_MCR_MICS(0);
  234. I2S0_MDR = 0;
  235. // configure transmitter
  236. I2S0_TMR = 0;
  237. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  238. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;
  239. I2S0_TCR3 = I2S_TCR3_TCE;
  240. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
  241. | I2S_TCR4_FSE | I2S_TCR4_FSP;
  242. I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
  243. // configure receiver (sync'd to transmitter clocks)
  244. I2S0_RMR = 0;
  245. I2S0_RCR1 = I2S_RCR1_RFW(1);
  246. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;
  247. I2S0_RCR3 = I2S_RCR3_RCE;
  248. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
  249. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  250. I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
  251. // configure pin mux for 3 clock signals
  252. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  253. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  254. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  255. }
  256. /******************************************************************/
  257. DMAMEM static uint32_t i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  258. audio_block_t * AudioInputI2S::block_left = NULL;
  259. audio_block_t * AudioInputI2S::block_right = NULL;
  260. uint16_t AudioInputI2S::block_offset = 0;
  261. bool AudioInputI2S::update_responsibility = false;
  262. void AudioInputI2S::begin(void)
  263. {
  264. //block_left_1st = NULL;
  265. //block_right_1st = NULL;
  266. //pinMode(3, OUTPUT);
  267. //digitalWriteFast(3, HIGH);
  268. //delayMicroseconds(500);
  269. //digitalWriteFast(3, LOW);
  270. AudioOutputI2S::config_i2s();
  271. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  272. DMA_CR = 0;
  273. DMA_TCD1_SADDR = &I2S0_RDR0;
  274. DMA_TCD1_SOFF = 0;
  275. DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  276. DMA_TCD1_NBYTES_MLNO = 2;
  277. DMA_TCD1_SLAST = 0;
  278. DMA_TCD1_DADDR = i2s_rx_buffer;
  279. DMA_TCD1_DOFF = 2;
  280. DMA_TCD1_CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  281. DMA_TCD1_DLASTSGA = -sizeof(i2s_rx_buffer);
  282. DMA_TCD1_BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  283. DMA_TCD1_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  284. DMAMUX0_CHCFG1 = DMAMUX_DISABLE;
  285. DMAMUX0_CHCFG1 = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE;
  286. update_responsibility = update_setup();
  287. DMA_SERQ = 1;
  288. // TODO: is I2S_RCSR_BCE appropriate if sync'd to transmitter clock?
  289. //I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  290. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  291. NVIC_ENABLE_IRQ(IRQ_DMA_CH1);
  292. }
  293. void dma_ch1_isr(void)
  294. {
  295. uint32_t daddr, offset;
  296. const int16_t *src, *end;
  297. int16_t *dest_left, *dest_right;
  298. audio_block_t *left, *right;
  299. //digitalWriteFast(3, HIGH);
  300. daddr = (uint32_t)DMA_TCD1_DADDR;
  301. DMA_CINT = 1;
  302. if (daddr < (uint32_t)i2s_rx_buffer + sizeof(i2s_rx_buffer) / 2) {
  303. // DMA is receiving to the first half of the buffer
  304. // need to remove data from the second half
  305. src = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  306. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  307. if (AudioInputI2S::update_responsibility) AudioStream::update_all();
  308. } else {
  309. // DMA is receiving to the second half of the buffer
  310. // need to remove data from the first half
  311. src = (int16_t *)&i2s_rx_buffer[0];
  312. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  313. }
  314. left = AudioInputI2S::block_left;
  315. right = AudioInputI2S::block_right;
  316. if (left != NULL && right != NULL) {
  317. offset = AudioInputI2S::block_offset;
  318. if (offset <= AUDIO_BLOCK_SAMPLES/2) {
  319. dest_left = &(left->data[offset]);
  320. dest_right = &(right->data[offset]);
  321. AudioInputI2S::block_offset = offset + AUDIO_BLOCK_SAMPLES/2;
  322. do {
  323. //n = *src++;
  324. //*dest_left++ = (int16_t)n;
  325. //*dest_right++ = (int16_t)(n >> 16);
  326. *dest_left++ = *src++;
  327. *dest_right++ = *src++;
  328. } while (src < end);
  329. }
  330. }
  331. //digitalWriteFast(3, LOW);
  332. }
  333. void AudioInputI2S::update(void)
  334. {
  335. audio_block_t *new_left=NULL, *new_right=NULL, *out_left=NULL, *out_right=NULL;
  336. // allocate 2 new blocks, but if one fails, allocate neither
  337. new_left = allocate();
  338. if (new_left != NULL) {
  339. new_right = allocate();
  340. if (new_right == NULL) {
  341. release(new_left);
  342. new_left = NULL;
  343. }
  344. }
  345. __disable_irq();
  346. if (block_offset >= AUDIO_BLOCK_SAMPLES) {
  347. // the DMA filled 2 blocks, so grab them and get the
  348. // 2 new blocks to the DMA, as quickly as possible
  349. out_left = block_left;
  350. block_left = new_left;
  351. out_right = block_right;
  352. block_right = new_right;
  353. block_offset = 0;
  354. __enable_irq();
  355. // then transmit the DMA's former blocks
  356. transmit(out_left, 0);
  357. release(out_left);
  358. transmit(out_right, 1);
  359. release(out_right);
  360. //Serial.print(".");
  361. } else if (new_left != NULL) {
  362. // the DMA didn't fill blocks, but we allocated blocks
  363. if (block_left == NULL) {
  364. // the DMA doesn't have any blocks to fill, so
  365. // give it the ones we just allocated
  366. block_left = new_left;
  367. block_right = new_right;
  368. block_offset = 0;
  369. __enable_irq();
  370. } else {
  371. // the DMA already has blocks, doesn't need these
  372. __enable_irq();
  373. release(new_left);
  374. release(new_right);
  375. }
  376. } else {
  377. // The DMA didn't fill blocks, and we could not allocate
  378. // memory... the system is likely starving for memory!
  379. // Sadly, there's nothing we can do.
  380. __enable_irq();
  381. }
  382. }
  383. /******************************************************************/
  384. void AudioInputI2Sslave::begin(void)
  385. {
  386. //block_left_1st = NULL;
  387. //block_right_1st = NULL;
  388. //pinMode(3, OUTPUT);
  389. //digitalWriteFast(3, HIGH);
  390. //delayMicroseconds(500);
  391. //digitalWriteFast(3, LOW);
  392. AudioOutputI2Sslave::config_i2s();
  393. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  394. DMA_CR = 0;
  395. DMA_TCD1_SADDR = &I2S0_RDR0;
  396. DMA_TCD1_SOFF = 0;
  397. DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  398. DMA_TCD1_NBYTES_MLNO = 2;
  399. DMA_TCD1_SLAST = 0;
  400. DMA_TCD1_DADDR = i2s_rx_buffer;
  401. DMA_TCD1_DOFF = 2;
  402. DMA_TCD1_CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  403. DMA_TCD1_DLASTSGA = -sizeof(i2s_rx_buffer);
  404. DMA_TCD1_BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  405. DMA_TCD1_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  406. DMAMUX0_CHCFG1 = DMAMUX_DISABLE;
  407. DMAMUX0_CHCFG1 = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE;
  408. update_responsibility = update_setup();
  409. DMA_SERQ = 1;
  410. // TODO: is I2S_RCSR_BCE appropriate if sync'd to transmitter clock?
  411. //I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  412. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  413. NVIC_ENABLE_IRQ(IRQ_DMA_CH1);
  414. }
  415. /******************************************************************/