output_i2s_quad.cpp 12KB

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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include <Arduino.h>
  27. #include "output_i2s_quad.h"
  28. #include "output_i2s.h"
  29. #include "memcpy_audio.h"
  30. #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(__IMXRT1062__)
  31. #if defined(__IMXRT1062__)
  32. #include "utility/imxrt_hw.h"
  33. #endif
  34. audio_block_t * AudioOutputI2SQuad::block_ch1_1st = NULL;
  35. audio_block_t * AudioOutputI2SQuad::block_ch2_1st = NULL;
  36. audio_block_t * AudioOutputI2SQuad::block_ch3_1st = NULL;
  37. audio_block_t * AudioOutputI2SQuad::block_ch4_1st = NULL;
  38. audio_block_t * AudioOutputI2SQuad::block_ch1_2nd = NULL;
  39. audio_block_t * AudioOutputI2SQuad::block_ch2_2nd = NULL;
  40. audio_block_t * AudioOutputI2SQuad::block_ch3_2nd = NULL;
  41. audio_block_t * AudioOutputI2SQuad::block_ch4_2nd = NULL;
  42. uint16_t AudioOutputI2SQuad::ch1_offset = 0;
  43. uint16_t AudioOutputI2SQuad::ch2_offset = 0;
  44. uint16_t AudioOutputI2SQuad::ch3_offset = 0;
  45. uint16_t AudioOutputI2SQuad::ch4_offset = 0;
  46. bool AudioOutputI2SQuad::update_responsibility = false;
  47. DMAMEM __attribute__((aligned(32))) static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES*2];
  48. DMAChannel AudioOutputI2SQuad::dma(false);
  49. static const uint32_t zerodata[AUDIO_BLOCK_SAMPLES/4] = {0};
  50. void AudioOutputI2SQuad::begin(void)
  51. {
  52. dma.begin(true); // Allocate the DMA channel first
  53. block_ch1_1st = NULL;
  54. block_ch2_1st = NULL;
  55. block_ch3_1st = NULL;
  56. block_ch4_1st = NULL;
  57. #if defined(KINETISK)
  58. // TODO: can we call normal config_i2s, and then just enable the extra output?
  59. config_i2s();
  60. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 -> ch1 & ch2
  61. CORE_PIN15_CONFIG = PORT_PCR_MUX(6); // pin 15, PTC0, I2S0_TXD1 -> ch3 & ch4
  62. dma.TCD->SADDR = i2s_tx_buffer;
  63. dma.TCD->SOFF = 2;
  64. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1) | DMA_TCD_ATTR_DMOD(3);
  65. dma.TCD->NBYTES_MLNO = 4;
  66. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  67. dma.TCD->DADDR = &I2S0_TDR0;
  68. dma.TCD->DOFF = 4;
  69. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 4;
  70. dma.TCD->DLASTSGA = 0;
  71. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 4;
  72. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  73. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  74. update_responsibility = update_setup();
  75. dma.enable();
  76. I2S0_TCSR = I2S_TCSR_SR;
  77. I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  78. dma.attachInterrupt(isr);
  79. #elif defined(__IMXRT1062__)
  80. const int pinoffset = 0; // TODO: make this configurable...
  81. memset(i2s_tx_buffer, 0, sizeof(i2s_tx_buffer));
  82. AudioOutputI2S::config_i2s();
  83. I2S1_TCR3 = I2S_TCR3_TCE_2CH << pinoffset;
  84. switch (pinoffset) {
  85. case 0:
  86. CORE_PIN7_CONFIG = 3;
  87. CORE_PIN32_CONFIG = 3;
  88. break;
  89. case 1:
  90. CORE_PIN32_CONFIG = 3;
  91. CORE_PIN9_CONFIG = 3;
  92. break;
  93. case 2:
  94. CORE_PIN9_CONFIG = 3;
  95. CORE_PIN6_CONFIG = 3;
  96. }
  97. dma.TCD->SADDR = i2s_tx_buffer;
  98. dma.TCD->SOFF = 2;
  99. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  100. dma.TCD->NBYTES_MLOFFYES = DMA_TCD_NBYTES_DMLOE |
  101. DMA_TCD_NBYTES_MLOFFYES_MLOFF(-8) |
  102. DMA_TCD_NBYTES_MLOFFYES_NBYTES(4);
  103. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  104. dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2 + pinoffset * 4);
  105. dma.TCD->DOFF = 4;
  106. dma.TCD->CITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
  107. dma.TCD->DLASTSGA = -8;
  108. dma.TCD->BITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
  109. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  110. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
  111. dma.enable();
  112. I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
  113. I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  114. I2S1_TCR3 = I2S_TCR3_TCE_2CH << pinoffset;
  115. update_responsibility = update_setup();
  116. dma.attachInterrupt(isr);
  117. #endif
  118. }
  119. void AudioOutputI2SQuad::isr(void)
  120. {
  121. uint32_t saddr;
  122. const int16_t *src1, *src2, *src3, *src4;
  123. const int16_t *zeros = (const int16_t *)zerodata;
  124. int16_t *dest;
  125. saddr = (uint32_t)(dma.TCD->SADDR);
  126. dma.clearInterrupt();
  127. if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
  128. // DMA is transmitting the first half of the buffer
  129. // so we must fill the second half
  130. dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  131. if (update_responsibility) update_all();
  132. } else {
  133. dest = (int16_t *)i2s_tx_buffer;
  134. }
  135. src1 = (block_ch1_1st) ? block_ch1_1st->data + ch1_offset : zeros;
  136. src2 = (block_ch2_1st) ? block_ch2_1st->data + ch2_offset : zeros;
  137. src3 = (block_ch3_1st) ? block_ch3_1st->data + ch3_offset : zeros;
  138. src4 = (block_ch4_1st) ? block_ch4_1st->data + ch4_offset : zeros;
  139. #if 1
  140. memcpy_tointerleaveQuad(dest, src1, src2, src3, src4);
  141. #else
  142. // about this code: https://forum.pjrc.com/threads/64508
  143. for (int i=0; i < AUDIO_BLOCK_SAMPLES/2; i++) {
  144. *dest++ = *src1++;
  145. *dest++ = *src3++;
  146. *dest++ = *src2++;
  147. *dest++ = *src4++;
  148. }
  149. #endif
  150. arm_dcache_flush_delete(dest, sizeof(i2s_tx_buffer) / 2 );
  151. if (block_ch1_1st) {
  152. if (ch1_offset == 0) {
  153. ch1_offset = AUDIO_BLOCK_SAMPLES/2;
  154. } else {
  155. ch1_offset = 0;
  156. release(block_ch1_1st);
  157. block_ch1_1st = block_ch1_2nd;
  158. block_ch1_2nd = NULL;
  159. }
  160. }
  161. if (block_ch2_1st) {
  162. if (ch2_offset == 0) {
  163. ch2_offset = AUDIO_BLOCK_SAMPLES/2;
  164. } else {
  165. ch2_offset = 0;
  166. release(block_ch2_1st);
  167. block_ch2_1st = block_ch2_2nd;
  168. block_ch2_2nd = NULL;
  169. }
  170. }
  171. if (block_ch3_1st) {
  172. if (ch3_offset == 0) {
  173. ch3_offset = AUDIO_BLOCK_SAMPLES/2;
  174. } else {
  175. ch3_offset = 0;
  176. release(block_ch3_1st);
  177. block_ch3_1st = block_ch3_2nd;
  178. block_ch3_2nd = NULL;
  179. }
  180. }
  181. if (block_ch4_1st) {
  182. if (ch4_offset == 0) {
  183. ch4_offset = AUDIO_BLOCK_SAMPLES/2;
  184. } else {
  185. ch4_offset = 0;
  186. release(block_ch4_1st);
  187. block_ch4_1st = block_ch4_2nd;
  188. block_ch4_2nd = NULL;
  189. }
  190. }
  191. }
  192. void AudioOutputI2SQuad::update(void)
  193. {
  194. audio_block_t *block, *tmp;
  195. block = receiveReadOnly(0); // channel 1
  196. if (block) {
  197. __disable_irq();
  198. if (block_ch1_1st == NULL) {
  199. block_ch1_1st = block;
  200. ch1_offset = 0;
  201. __enable_irq();
  202. } else if (block_ch1_2nd == NULL) {
  203. block_ch1_2nd = block;
  204. __enable_irq();
  205. } else {
  206. tmp = block_ch1_1st;
  207. block_ch1_1st = block_ch1_2nd;
  208. block_ch1_2nd = block;
  209. ch1_offset = 0;
  210. __enable_irq();
  211. release(tmp);
  212. }
  213. }
  214. block = receiveReadOnly(1); // channel 2
  215. if (block) {
  216. __disable_irq();
  217. if (block_ch2_1st == NULL) {
  218. block_ch2_1st = block;
  219. ch2_offset = 0;
  220. __enable_irq();
  221. } else if (block_ch2_2nd == NULL) {
  222. block_ch2_2nd = block;
  223. __enable_irq();
  224. } else {
  225. tmp = block_ch2_1st;
  226. block_ch2_1st = block_ch2_2nd;
  227. block_ch2_2nd = block;
  228. ch2_offset = 0;
  229. __enable_irq();
  230. release(tmp);
  231. }
  232. }
  233. block = receiveReadOnly(2); // channel 3
  234. if (block) {
  235. __disable_irq();
  236. if (block_ch3_1st == NULL) {
  237. block_ch3_1st = block;
  238. ch3_offset = 0;
  239. __enable_irq();
  240. } else if (block_ch3_2nd == NULL) {
  241. block_ch3_2nd = block;
  242. __enable_irq();
  243. } else {
  244. tmp = block_ch3_1st;
  245. block_ch3_1st = block_ch3_2nd;
  246. block_ch3_2nd = block;
  247. ch3_offset = 0;
  248. __enable_irq();
  249. release(tmp);
  250. }
  251. }
  252. block = receiveReadOnly(3); // channel 4
  253. if (block) {
  254. __disable_irq();
  255. if (block_ch4_1st == NULL) {
  256. block_ch4_1st = block;
  257. ch4_offset = 0;
  258. __enable_irq();
  259. } else if (block_ch4_2nd == NULL) {
  260. block_ch4_2nd = block;
  261. __enable_irq();
  262. } else {
  263. tmp = block_ch4_1st;
  264. block_ch4_1st = block_ch4_2nd;
  265. block_ch4_2nd = block;
  266. ch4_offset = 0;
  267. __enable_irq();
  268. release(tmp);
  269. }
  270. }
  271. }
  272. #if defined(KINETISK)
  273. // MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
  274. //
  275. #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
  276. // PLL is at 96 MHz in these modes
  277. #define MCLK_MULT 2
  278. #define MCLK_DIV 17
  279. #elif F_CPU == 72000000
  280. #define MCLK_MULT 8
  281. #define MCLK_DIV 51
  282. #elif F_CPU == 120000000
  283. #define MCLK_MULT 8
  284. #define MCLK_DIV 85
  285. #elif F_CPU == 144000000
  286. #define MCLK_MULT 4
  287. #define MCLK_DIV 51
  288. #elif F_CPU == 168000000
  289. #define MCLK_MULT 8
  290. #define MCLK_DIV 119
  291. #elif F_CPU == 180000000
  292. #define MCLK_MULT 16
  293. #define MCLK_DIV 255
  294. #define MCLK_SRC 0
  295. #elif F_CPU == 192000000
  296. #define MCLK_MULT 1
  297. #define MCLK_DIV 17
  298. #elif F_CPU == 216000000
  299. #define MCLK_MULT 12
  300. #define MCLK_DIV 17
  301. #define MCLK_SRC 1
  302. #elif F_CPU == 240000000
  303. #define MCLK_MULT 2
  304. #define MCLK_DIV 85
  305. #define MCLK_SRC 0
  306. #elif F_CPU == 256000000
  307. #define MCLK_MULT 12
  308. #define MCLK_DIV 17
  309. #define MCLK_SRC 1
  310. #elif F_CPU == 16000000
  311. #define MCLK_MULT 12
  312. #define MCLK_DIV 17
  313. #else
  314. #error "This CPU Clock Speed is not supported by the Audio library";
  315. #endif
  316. #ifndef MCLK_SRC
  317. #if F_CPU >= 20000000
  318. #define MCLK_SRC 3 // the PLL
  319. #else
  320. #define MCLK_SRC 0 // system clock
  321. #endif
  322. #endif
  323. void AudioOutputI2SQuad::config_i2s(void)
  324. {
  325. SIM_SCGC6 |= SIM_SCGC6_I2S;
  326. SIM_SCGC7 |= SIM_SCGC7_DMA;
  327. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  328. // if either transmitter or receiver is enabled, do nothing
  329. if (I2S0_TCSR & I2S_TCSR_TE) return;
  330. if (I2S0_RCSR & I2S_RCSR_RE) return;
  331. // enable MCLK output
  332. I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
  333. while (I2S0_MCR & I2S_MCR_DUF) ;
  334. I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
  335. // configure transmitter
  336. I2S0_TMR = 0;
  337. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  338. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  339. | I2S_TCR2_BCD | I2S_TCR2_DIV(3);
  340. I2S0_TCR3 = I2S_TCR3_TCE_2CH;
  341. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
  342. | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
  343. I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
  344. // configure receiver (sync'd to transmitter clocks)
  345. I2S0_RMR = 0;
  346. I2S0_RCR1 = I2S_RCR1_RFW(1);
  347. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  348. | I2S_RCR2_BCD | I2S_RCR2_DIV(3);
  349. I2S0_RCR3 = I2S_RCR3_RCE_2CH;
  350. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
  351. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  352. I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
  353. // configure pin mux for 3 clock signals
  354. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  355. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  356. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  357. }
  358. #endif // KINETISK
  359. #else // not supported
  360. void AudioOutputI2SQuad::begin(void)
  361. {
  362. }
  363. void AudioOutputI2SQuad::update(void)
  364. {
  365. audio_block_t *block;
  366. block = receiveReadOnly(0);
  367. if (block) release(block);
  368. block = receiveReadOnly(1);
  369. if (block) release(block);
  370. block = receiveReadOnly(2);
  371. if (block) release(block);
  372. block = receiveReadOnly(3);
  373. if (block) release(block);
  374. }
  375. #endif