Fix DAC output range

https://forum.pjrc.com/threads/46443-Teensy-3-6-DAC-Output-Bug

output_dac.cpp

@@ -42,7 +42,7 @@ void AudioOutputAnalog::begin(void)
 	SIM_SCGC2 |= SIM_SCGC2_DAC0;
 	DAC0_C0 = DAC_C0_DACEN;                   // 1.2V VDDA is DACREF_2
 	// slowly ramp up to DC voltage, approx 1/4 second
-	for (int16_t i=0; i<2048; i+=8) {
+	for (int16_t i=0; i<=2048; i+=8) {
 		*(int16_t *)&(DAC0_DAT0L) = i;
 		delay(1);
 	}
@@ -139,14 +139,14 @@ void AudioOutputAnalog::isr(void)
 		src = block->data;
 		do {
 			// TODO: this should probably dither
-			*dest++ = ((*src++) + 32767) >> 4;
+			*dest++ = ((*src++) + 32768) >> 4;
 		} while (dest < end);
 		AudioStream::release(block);
 		AudioOutputAnalog::block_left_1st = AudioOutputAnalog::block_left_2nd;
 		AudioOutputAnalog::block_left_2nd = NULL;
 	} else {
 		do {
-			*dest++ = 2047;
+			*dest++ = 2048;
 		} while (dest < end);
 	}
 	if (AudioOutputAnalog::update_responsibility) AudioStream::update_all();

output_dacs.cpp

@@ -48,7 +48,7 @@ void AudioOutputAnalogStereo::begin(void)
 	memset(&block_silent, 0, sizeof(block_silent));
 
 	// slowly ramp up to DC voltage, approx 1/4 second
-	for (int16_t i=0; i<2048; i+=8) {
+	for (int16_t i=0; i<=2048; i+=8) {
 		*(int16_t *)&(DAC0_DAT0L) = i;
 		*(int16_t *)&(DAC1_DAT0L) = i;
 		delay(1);
@@ -174,10 +174,10 @@ void AudioOutputAnalogStereo::isr(void)
 		// TODO: can this be optimized?
 		uint32_t left = *src_left++;
 		uint32_t right = *src_right++;
-		uint32_t out1 = ((left & 0xFFFF) + 32767) >> 4;
-		out1 |= (((right & 0xFFFF) + 32767) >> 4) << 16;
-		uint32_t out2 = ((left >> 16) + 32767) >> 4;
-		out2 |= (((right >> 16) + 32767) >> 4) << 16;
+		uint32_t out1 = ((left & 0xFFFF) + 32768) >> 4;
+		out1 |= (((right & 0xFFFF) + 32768) >> 4) << 16;
+		uint32_t out2 = ((left >> 16) + 32768) >> 4;
+		out2 |= (((right >> 16) + 32768) >> 4) << 16;
 		*dest++ = out1;
 		*dest++ = out2;
 	} while (dest < end);