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@@ -29,30 +29,24 @@ |
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#include "memcpy_audio.h" |
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#include "utility/imxrt_hw.h" |
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#if !defined(I2S_TCR2_BCP) |
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#define I2S_TCR2_BCP ((uint32_t)1<<25) |
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#define I2S_RCR2_BCP ((uint32_t)1<<25) |
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#define I2S_TCR4_FCONT ((uint32_t)1<<28) // FIFO Continue on Error |
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#define I2S_RCR4_FCONT ((uint32_t)1<<28) // FIFO Continue on Error |
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#define I2S_TCR4_FSP ((uint32_t)1<< 1) |
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#define I2S_RCR4_FSP ((uint32_t)1<< 1) |
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#endif |
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audio_block_t * AudioOutputTDM::block_input[16] = { |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL |
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr |
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}; |
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bool AudioOutputTDM::update_responsibility = false; |
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DMAChannel AudioOutputTDM::dma(false); |
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DMAMEM __attribute__((aligned(32))) |
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static uint32_t zeros[AUDIO_BLOCK_SAMPLES/2]; |
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DMAMEM __attribute__((aligned(32))) |
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static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16]; |
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DMAChannel AudioOutputTDM::dma(false); |
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void AudioOutputTDM::begin(void) |
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{ |
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dma.begin(true); // Allocate the DMA channel first |
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for (int i=0; i < 16; i++) { |
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block_input[i] = NULL; |
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block_input[i] = nullptr; |
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} |
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// TODO: should we set & clear the I2S_TCSR_SR bit here? |
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@@ -109,20 +103,29 @@ static void memcpy_tdm_tx(uint32_t *dest, const uint32_t *src1, const uint32_t * |
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{ |
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uint32_t i, in1, in2, out1, out2; |
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for (i=0; i < AUDIO_BLOCK_SAMPLES/2; i++) { |
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for (i=0; i < AUDIO_BLOCK_SAMPLES/4; i++) { |
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in1 = *src1++; |
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in2 = *src2++; |
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out1 = (in1 << 16) | (in2 & 0xFFFF); |
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out2 = (in1 & 0xFFFF0000) | (in2 >> 16); |
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*dest = out1; |
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*(dest + 8) = out2; |
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dest += 16; |
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in1 = *src1++; |
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in2 = *src2++; |
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out1 = (in1 << 16) | (in2 & 0xFFFF); |
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out2 = (in1 & 0xFFFF0000) | (in2 >> 16); |
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*(dest + 16)= out1; |
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*(dest + 24) = out2; |
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dest += 32; |
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} |
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} |
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void AudioOutputTDM::isr(void) |
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{ |
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uint32_t *dest; |
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uint32_t *dest, *dc; |
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const uint32_t *src1, *src2; |
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uint32_t i, saddr; |
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@@ -138,16 +141,22 @@ void AudioOutputTDM::isr(void) |
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dest = tdm_tx_buffer; |
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} |
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if (update_responsibility) AudioStream::update_all(); |
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dc = dest; |
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for (i=0; i < 16; i += 2) { |
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src1 = block_input[i] ? (uint32_t *)(block_input[i]->data) : zeros; |
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src2 = block_input[i+1] ? (uint32_t *)(block_input[i+1]->data) : zeros; |
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memcpy_tdm_tx(dest, src1, src2); |
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dest++; |
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} |
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#if IMXRT_CACHE_ENABLED >= 2 |
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arm_dcache_flush_delete(dc, sizeof(tdm_tx_buffer) / 2 ); |
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#endif |
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for (i=0; i < 16; i++) { |
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if (block_input[i]) { |
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release(block_input[i]); |
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block_input[i] = NULL; |
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block_input[i] = nullptr; |
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} |
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} |
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} |
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@@ -252,14 +261,14 @@ void AudioOutputTDM::config_tdm(void) |
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I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); |
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// configure pin mux for 3 clock signals |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) - 44.1kHz |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK - 11.2 MHz |
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK - 22.5 MHz |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); |
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//PLL: |
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int fs = AUDIO_SAMPLE_RATE_EXACT*2; |
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int fs = AUDIO_SAMPLE_RATE_EXACT; |
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// PLL between 27*24 = 648MHz und 54*24=1296MHz |
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int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4 |
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int n2 = 1 + (24000000 * 27) / (fs * 256 * n1); |
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@@ -273,7 +282,7 @@ void AudioOutputTDM::config_tdm(void) |
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CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK)) |
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| CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4 |
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//n1 = n1 / 2; //Double Speed for TDM |
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n1 = n1 / 2; //Double Speed for TDM |
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CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK)) |
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| CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07 |
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@@ -299,7 +308,6 @@ void AudioOutputTDM::config_tdm(void) |
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| I2S_TCR4_FSE | I2S_TCR4_FSD; |
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I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); |
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// configure receiver (sync'd to transmitter clocks) |
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I2S1_RMR = 0; |
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I2S1_RCR1 = I2S_RCR1_RFW(4); |
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I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1) |