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Quad input on Teensy 3.5 & 3.6 needs pin 38

dds
PaulStoffregen преди 7 години
родител
ревизия
2a2b24a72f
променени са 2 файла, в които са добавени 10 реда и са изтрити 6 реда
  1. +6
    -6
      gui/index.html
  2. +4
    -0
      input_i2s_quad.cpp

+ 6
- 6
gui/index.html Целия файл

@@ -495,12 +495,12 @@ span.mainfunction {color: #993300; font-weight: bolder}
<p>The I2S signals are used in "master" mode, where Teensy creates
all 3 clock signals and controls all data timing.</p>
<table class=doc align=center cellpadding=3>
<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>13</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>30</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>23</td><td>LRCLK</td><td>Output</td></tr>
<tr class=top><th>Teensy<br>3.2 Pin</th><th>Teensy<br>3.5/3.6 Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td align=center>9</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td align=center>11</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>13</td><td align=center>13</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>30</td><td align=center>38</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>23</td><td align=center>23</td><td>LRCLK</td><td>Output</td></tr>
</table>
<p>Audio from
master mode I2S may be used in the same project as ADC, DAC and

+ 4
- 0
input_i2s_quad.cpp Целия файл

@@ -46,7 +46,11 @@ void AudioInputI2SQuad::begin(void)
AudioOutputI2SQuad::config_i2s();

CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
#if defined(__MK20DX256__)
CORE_PIN30_CONFIG = PORT_PCR_MUX(4); // pin 30, PTC11, I2S0_RXD1
#elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
CORE_PIN38_CONFIG = PORT_PCR_MUX(4); // pin 38, PTC11, I2S0_RXD1
#endif

#if defined(KINETISK)
dma.TCD->SADDR = &I2S0_RDR0;

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