| #define input_adc_h_ | #define input_adc_h_ | ||||
| #include "AudioStream.h" | #include "AudioStream.h" | ||||
| #include "DMAChannel.h" | |||||
| #include "utility/dma_chan.h" | #include "utility/dma_chan.h" | ||||
| #ifdef __MK20DX128__ | #ifdef __MK20DX128__ |
| void AudioInputI2S::begin(void) | void AudioInputI2S::begin(void) | ||||
| { | { | ||||
| dma(); // Allocate the DMA channel first | |||||
| //block_left_1st = NULL; | //block_left_1st = NULL; | ||||
| //block_right_1st = NULL; | //block_right_1st = NULL; | ||||
| CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 | CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 | ||||
| DMA_CR = 0; | |||||
| DMA_TCD_SADDR(AUDIO_IN_I2S_DMA_CHANNEL) = &I2S0_RDR0; | |||||
| DMA_TCD_SOFF(AUDIO_IN_I2S_DMA_CHANNEL) = 0; | |||||
| DMA_TCD_ATTR(AUDIO_IN_I2S_DMA_CHANNEL) = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| DMA_TCD_NBYTES_MLNO(AUDIO_IN_I2S_DMA_CHANNEL) = 2; | |||||
| DMA_TCD_SLAST(AUDIO_IN_I2S_DMA_CHANNEL) = 0; | |||||
| DMA_TCD_DADDR(AUDIO_IN_I2S_DMA_CHANNEL) = i2s_rx_buffer; | |||||
| DMA_TCD_DOFF(AUDIO_IN_I2S_DMA_CHANNEL) = 2; | |||||
| DMA_TCD_CITER_ELINKNO(AUDIO_IN_I2S_DMA_CHANNEL) = sizeof(i2s_rx_buffer) / 2; | |||||
| DMA_TCD_DLASTSGA(AUDIO_IN_I2S_DMA_CHANNEL) = -sizeof(i2s_rx_buffer); | |||||
| DMA_TCD_BITER_ELINKNO(AUDIO_IN_I2S_DMA_CHANNEL) = sizeof(i2s_rx_buffer) / 2; | |||||
| DMA_TCD_CSR(AUDIO_IN_I2S_DMA_CHANNEL) = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| DMAMUX0_CHCFG(AUDIO_IN_I2S_DMA_CHANNEL) = DMAMUX_DISABLE; | |||||
| DMAMUX0_CHCFG(AUDIO_IN_I2S_DMA_CHANNEL) = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE; | |||||
| dma().TCD->SADDR = &I2S0_RDR0; | |||||
| dma().TCD->SOFF = 0; | |||||
| dma().TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| dma().TCD->NBYTES_MLNO = 2; | |||||
| dma().TCD->SLAST = 0; | |||||
| dma().TCD->DADDR = i2s_rx_buffer; | |||||
| dma().TCD->DOFF = 2; | |||||
| dma().TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; | |||||
| dma().TCD->DLASTSGA = -sizeof(i2s_rx_buffer); | |||||
| dma().TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; | |||||
| dma().TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| dma().triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX); | |||||
| update_responsibility = update_setup(); | update_responsibility = update_setup(); | ||||
| DMA_SERQ = AUDIO_IN_I2S_DMA_CHANNEL; | |||||
| dma().enable(); | |||||
| I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; | I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; | ||||
| I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX | I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX | ||||
| NVIC_ENABLE_IRQ(IRQ_DMA_CH(AUDIO_IN_I2S_DMA_CHANNEL)); | |||||
| dma().attachInterrupt(isr); | |||||
| } | } | ||||
| void DMA_ISR(AUDIO_IN_I2S_DMA_CHANNEL)(void) | |||||
| void AudioInputI2S::isr(void) | |||||
| { | { | ||||
| uint32_t daddr, offset; | uint32_t daddr, offset; | ||||
| const int16_t *src, *end; | const int16_t *src, *end; | ||||
| audio_block_t *left, *right; | audio_block_t *left, *right; | ||||
| //digitalWriteFast(3, HIGH); | //digitalWriteFast(3, HIGH); | ||||
| daddr = (uint32_t)(DMA_TCD_DADDR(AUDIO_IN_I2S_DMA_CHANNEL)); | |||||
| DMA_CINT = AUDIO_IN_I2S_DMA_CHANNEL; | |||||
| daddr = (uint32_t)(dma().TCD->DADDR); | |||||
| dma().clearInterrupt(); | |||||
| if (daddr < (uint32_t)i2s_rx_buffer + sizeof(i2s_rx_buffer) / 2) { | if (daddr < (uint32_t)i2s_rx_buffer + sizeof(i2s_rx_buffer) / 2) { | ||||
| // DMA is receiving to the first half of the buffer | // DMA is receiving to the first half of the buffer | ||||
| void AudioInputI2Sslave::begin(void) | void AudioInputI2Sslave::begin(void) | ||||
| { | { | ||||
| dma(); // Allocate the DMA channel first | |||||
| //block_left_1st = NULL; | //block_left_1st = NULL; | ||||
| //block_right_1st = NULL; | //block_right_1st = NULL; | ||||
| //pinMode(3, OUTPUT); | |||||
| //digitalWriteFast(3, HIGH); | |||||
| //delayMicroseconds(500); | |||||
| //digitalWriteFast(3, LOW); | |||||
| AudioOutputI2Sslave::config_i2s(); | AudioOutputI2Sslave::config_i2s(); | ||||
| CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 | CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 | ||||
| DMA_CR = 0; | |||||
| DMA_TCD_SADDR(AUDIO_IN_I2S_DMA_CHANNEL) = &I2S0_RDR0; | |||||
| DMA_TCD_SOFF(AUDIO_IN_I2S_DMA_CHANNEL) = 0; | |||||
| DMA_TCD_ATTR(AUDIO_IN_I2S_DMA_CHANNEL) = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| DMA_TCD_NBYTES_MLNO(AUDIO_IN_I2S_DMA_CHANNEL) = 2; | |||||
| DMA_TCD_SLAST(AUDIO_IN_I2S_DMA_CHANNEL) = 0; | |||||
| DMA_TCD_DADDR(AUDIO_IN_I2S_DMA_CHANNEL) = i2s_rx_buffer; | |||||
| DMA_TCD_DOFF(AUDIO_IN_I2S_DMA_CHANNEL) = 2; | |||||
| DMA_TCD_CITER_ELINKNO(AUDIO_IN_I2S_DMA_CHANNEL) = sizeof(i2s_rx_buffer) / 2; | |||||
| DMA_TCD_DLASTSGA(AUDIO_IN_I2S_DMA_CHANNEL) = -sizeof(i2s_rx_buffer); | |||||
| DMA_TCD_BITER_ELINKNO(AUDIO_IN_I2S_DMA_CHANNEL) = sizeof(i2s_rx_buffer) / 2; | |||||
| DMA_TCD_CSR(AUDIO_IN_I2S_DMA_CHANNEL) = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| DMAMUX0_CHCFG(AUDIO_IN_I2S_DMA_CHANNEL) = DMAMUX_DISABLE; | |||||
| DMAMUX0_CHCFG(AUDIO_IN_I2S_DMA_CHANNEL) = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE; | |||||
| dma().TCD->SADDR = &I2S0_RDR0; | |||||
| dma().TCD->SOFF = 0; | |||||
| dma().TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| dma().TCD->NBYTES_MLNO = 2; | |||||
| dma().TCD->SLAST = 0; | |||||
| dma().TCD->DADDR = i2s_rx_buffer; | |||||
| dma().TCD->DOFF = 2; | |||||
| dma().TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; | |||||
| dma().TCD->DLASTSGA = -sizeof(i2s_rx_buffer); | |||||
| dma().TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; | |||||
| dma().TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| dma().triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX); | |||||
| update_responsibility = update_setup(); | update_responsibility = update_setup(); | ||||
| DMA_SERQ = AUDIO_IN_I2S_DMA_CHANNEL; | |||||
| dma().enable(); | |||||
| // TODO: is I2S_RCSR_BCE appropriate if sync'd to transmitter clock? | |||||
| //I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; | |||||
| I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_FRDE | I2S_RCSR_FR; | |||||
| NVIC_ENABLE_IRQ(IRQ_DMA_CH(AUDIO_IN_I2S_DMA_CHANNEL)); | |||||
| I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; | |||||
| I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX | |||||
| dma().attachInterrupt(isr); | |||||
| } | } | ||||
| #define _input_i2s_h_ | #define _input_i2s_h_ | ||||
| #include "AudioStream.h" | #include "AudioStream.h" | ||||
| #include "utility/dma_chan.h" | |||||
| #ifdef __MK20DX128__ | |||||
| #define AUDIO_IN_I2S_DMA_CHANNEL 1 | |||||
| #else | |||||
| #define AUDIO_IN_I2S_DMA_CHANNEL 5 | |||||
| #endif | |||||
| #include "DMAChannel.h" | |||||
| class AudioInputI2S : public AudioStream | class AudioInputI2S : public AudioStream | ||||
| { | { | ||||
| AudioInputI2S(void) : AudioStream(0, NULL) { begin(); } | AudioInputI2S(void) : AudioStream(0, NULL) { begin(); } | ||||
| virtual void update(void); | virtual void update(void); | ||||
| void begin(void); | void begin(void); | ||||
| friend void DMA_ISR(AUDIO_IN_I2S_DMA_CHANNEL)(void); | |||||
| protected: | protected: | ||||
| AudioInputI2S(int dummy): AudioStream(0, NULL) {} // to be used only inside AudioInputI2Sslave !! | AudioInputI2S(int dummy): AudioStream(0, NULL) {} // to be used only inside AudioInputI2Sslave !! | ||||
| static bool update_responsibility; | static bool update_responsibility; | ||||
| static inline DMAChannel &dma() __attribute__((always_inline)) { | |||||
| static DMAChannel mydma; | |||||
| return mydma; | |||||
| } | |||||
| static void isr(void); | |||||
| private: | private: | ||||
| static audio_block_t *block_left; | static audio_block_t *block_left; | ||||
| static audio_block_t *block_right; | static audio_block_t *block_right; |
| Audio KEYWORD2 | |||||
| | |||||
| Audio KEYWORD2 | |||||
| AudioConnection KEYWORD2 | AudioConnection KEYWORD2 | ||||
| AudioInputI2S KEYWORD2 | AudioInputI2S KEYWORD2 | ||||
| AudioOutputI2S KEYWORD2 | AudioOutputI2S KEYWORD2 |
| #define output_dac_h_ | #define output_dac_h_ | ||||
| #include "AudioStream.h" | #include "AudioStream.h" | ||||
| #include "DMAChannel.h" | |||||
| class AudioOutputAnalog : public AudioStream | class AudioOutputAnalog : public AudioStream | ||||
| { | { |
| #include "output_i2s.h" | #include "output_i2s.h" | ||||
| audio_block_t * AudioOutputI2S::block_left_1st = NULL; | audio_block_t * AudioOutputI2S::block_left_1st = NULL; | ||||
| audio_block_t * AudioOutputI2S::block_right_1st = NULL; | audio_block_t * AudioOutputI2S::block_right_1st = NULL; | ||||
| audio_block_t * AudioOutputI2S::block_left_2nd = NULL; | audio_block_t * AudioOutputI2S::block_left_2nd = NULL; | ||||
| void AudioOutputI2S::begin(void) | void AudioOutputI2S::begin(void) | ||||
| { | { | ||||
| //pinMode(2, OUTPUT); | |||||
| dma(); // Allocate the DMA channel first | |||||
| block_left_1st = NULL; | block_left_1st = NULL; | ||||
| block_right_1st = NULL; | block_right_1st = NULL; | ||||
| config_i2s(); | config_i2s(); | ||||
| CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 | CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 | ||||
| DMA_CR = 0; | |||||
| DMA_TCD0_SADDR = i2s_tx_buffer; | |||||
| DMA_TCD0_SOFF = 2; | |||||
| DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| DMA_TCD0_NBYTES_MLNO = 2; | |||||
| DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer); | |||||
| DMA_TCD0_DADDR = &I2S0_TDR0; | |||||
| DMA_TCD0_DOFF = 0; | |||||
| DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| DMA_TCD0_DLASTSGA = 0; | |||||
| DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| DMAMUX0_CHCFG0 = DMAMUX_DISABLE; | |||||
| DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE; | |||||
| dma().TCD->SADDR = i2s_tx_buffer; | |||||
| dma().TCD->SOFF = 2; | |||||
| dma().TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| dma().TCD->NBYTES_MLNO = 2; | |||||
| dma().TCD->SLAST = -sizeof(i2s_tx_buffer); | |||||
| dma().TCD->DADDR = &I2S0_TDR0; | |||||
| dma().TCD->DOFF = 0; | |||||
| dma().TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| dma().TCD->DLASTSGA = 0; | |||||
| dma().TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| dma().TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| dma().triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); | |||||
| update_responsibility = update_setup(); | update_responsibility = update_setup(); | ||||
| DMA_SERQ = 0; | |||||
| dma().enable(); | |||||
| I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | ||||
| NVIC_ENABLE_IRQ(IRQ_DMA_CH0); | |||||
| dma().attachInterrupt(isr); | |||||
| } | } | ||||
| void dma_ch0_isr(void) | |||||
| void AudioOutputI2S::isr(void) | |||||
| { | { | ||||
| const int16_t *src, *end; | const int16_t *src, *end; | ||||
| int16_t *dest; | int16_t *dest; | ||||
| audio_block_t *block; | audio_block_t *block; | ||||
| uint32_t saddr, offset; | uint32_t saddr, offset; | ||||
| saddr = (uint32_t)DMA_TCD0_SADDR; | |||||
| DMA_CINT = 0; | |||||
| saddr = (uint32_t)(dma().TCD->SADDR); | |||||
| dma().clearInterrupt(); | |||||
| if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { | if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { | ||||
| // DMA is transmitting the first half of the buffer | // DMA is transmitting the first half of the buffer | ||||
| // so we must fill the second half | // so we must fill the second half | ||||
| // enable MCLK output | // enable MCLK output | ||||
| I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; | I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; | ||||
| I2S0_MDR = I2S_MDR_FRACT(MCLK_MULT-1) | I2S_MDR_DIVIDE(MCLK_DIV-1); | |||||
| I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1)); | |||||
| // configure transmitter | // configure transmitter | ||||
| I2S0_TMR = 0; | I2S0_TMR = 0; | ||||
| void AudioOutputI2Sslave::begin(void) | void AudioOutputI2Sslave::begin(void) | ||||
| { | { | ||||
| dma(); // Allocate the DMA channel first | |||||
| //pinMode(2, OUTPUT); | //pinMode(2, OUTPUT); | ||||
| block_left_1st = NULL; | block_left_1st = NULL; | ||||
| block_right_1st = NULL; | block_right_1st = NULL; | ||||
| AudioOutputI2Sslave::config_i2s(); | AudioOutputI2Sslave::config_i2s(); | ||||
| CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 | CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 | ||||
| DMA_CR = 0; | |||||
| DMA_TCD0_SADDR = i2s_tx_buffer; | |||||
| DMA_TCD0_SOFF = 2; | |||||
| DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| DMA_TCD0_NBYTES_MLNO = 2; | |||||
| DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer); | |||||
| DMA_TCD0_DADDR = &I2S0_TDR0; | |||||
| DMA_TCD0_DOFF = 0; | |||||
| DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| DMA_TCD0_DLASTSGA = 0; | |||||
| DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| DMAMUX0_CHCFG0 = DMAMUX_DISABLE; | |||||
| DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE; | |||||
| dma().TCD->SADDR = i2s_tx_buffer; | |||||
| dma().TCD->SOFF = 2; | |||||
| dma().TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); | |||||
| dma().TCD->NBYTES_MLNO = 2; | |||||
| dma().TCD->SLAST = -sizeof(i2s_tx_buffer); | |||||
| dma().TCD->DADDR = &I2S0_TDR0; | |||||
| dma().TCD->DOFF = 0; | |||||
| dma().TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| dma().TCD->DLASTSGA = 0; | |||||
| dma().TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | |||||
| dma().TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | |||||
| dma().triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); | |||||
| update_responsibility = update_setup(); | update_responsibility = update_setup(); | ||||
| DMA_SERQ = 0; | |||||
| dma().enable(); | |||||
| I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | ||||
| NVIC_ENABLE_IRQ(IRQ_DMA_CH0); | |||||
| dma().attachInterrupt(isr); | |||||
| } | } | ||||
| void AudioOutputI2Sslave::config_i2s(void) | void AudioOutputI2Sslave::config_i2s(void) |
| #define output_i2s_h_ | #define output_i2s_h_ | ||||
| #include "AudioStream.h" | #include "AudioStream.h" | ||||
| #include "DMAChannel.h" | |||||
| class AudioOutputI2S : public AudioStream | class AudioOutputI2S : public AudioStream | ||||
| { | { | ||||
| AudioOutputI2S(void) : AudioStream(2, inputQueueArray) { begin(); } | AudioOutputI2S(void) : AudioStream(2, inputQueueArray) { begin(); } | ||||
| virtual void update(void); | virtual void update(void); | ||||
| void begin(void); | void begin(void); | ||||
| friend void dma_ch0_isr(void); | |||||
| friend class AudioInputI2S; | friend class AudioInputI2S; | ||||
| protected: | protected: | ||||
| AudioOutputI2S(int dummy): AudioStream(2, inputQueueArray) {} // to be used only inside AudioOutputI2Sslave !! | AudioOutputI2S(int dummy): AudioStream(2, inputQueueArray) {} // to be used only inside AudioOutputI2Sslave !! | ||||
| static audio_block_t *block_left_1st; | static audio_block_t *block_left_1st; | ||||
| static audio_block_t *block_right_1st; | static audio_block_t *block_right_1st; | ||||
| static bool update_responsibility; | static bool update_responsibility; | ||||
| static inline DMAChannel &dma() __attribute__((always_inline)) { | |||||
| static DMAChannel mydma; | |||||
| return mydma; | |||||
| } | |||||
| static void isr(void); | |||||
| private: | private: | ||||
| static audio_block_t *block_left_2nd; | static audio_block_t *block_left_2nd; | ||||
| static audio_block_t *block_right_2nd; | static audio_block_t *block_right_2nd; |
| #define output_pwm_h_ | #define output_pwm_h_ | ||||
| #include "AudioStream.h" | #include "AudioStream.h" | ||||
| #include "DMAChannel.h" | |||||
| #include "utility/dma_chan.h" | #include "utility/dma_chan.h" | ||||
| #ifdef __MK20DX128__ | #ifdef __MK20DX128__ |