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/******************************************************************/ |
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void AudioOutputI2Sslave::begin(void) |
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{ |
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//pinMode(2, OUTPUT); |
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block_left_1st = NULL; |
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block_right_1st = NULL; |
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AudioOutputI2Sslave::config_i2s(); |
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 |
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DMA_CR = 0; |
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DMA_TCD0_SADDR = i2s_tx_buffer; |
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DMA_TCD0_SOFF = 2; |
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DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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DMA_TCD0_NBYTES_MLNO = 2; |
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DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer); |
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DMA_TCD0_DADDR = &I2S0_TDR0; |
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DMA_TCD0_DOFF = 0; |
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DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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DMA_TCD0_DLASTSGA = 0; |
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DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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DMAMUX0_CHCFG0 = DMAMUX_DISABLE; |
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DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE; |
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update_responsibility = update_setup(); |
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DMA_SERQ = 0; |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; |
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NVIC_ENABLE_IRQ(IRQ_DMA_CH0); |
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} |
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void AudioOutputI2Sslave::config_i2s(void) |
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{ |
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SIM_SCGC6 |= SIM_SCGC6_I2S; |
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SIM_SCGC7 |= SIM_SCGC7_DMA; |
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
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// if either transmitter or receiver is enabled, do nothing |
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if (I2S0_TCSR & I2S_TCSR_TE) return; |
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if (I2S0_RCSR & I2S_RCSR_RE) return; |
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// Select input clock 0 |
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// Configure to input the bit-clock from pin, bypasses the MCLK divider |
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I2S0_MCR = I2S_MCR_MICS(0); |
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I2S0_MDR = 0; |
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// configure transmitter |
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I2S0_TMR = 0; |
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I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size |
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I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP; |
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I2S0_TCR3 = I2S_TCR3_TCE; |
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I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF |
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| I2S_TCR4_FSE | I2S_TCR4_FSP; |
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I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15); |
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// configure receiver (sync'd to transmitter clocks) |
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I2S0_RMR = 0; |
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I2S0_RCR1 = I2S_RCR1_RFW(1); |
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I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP; |
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I2S0_RCR3 = I2S_RCR3_RCE; |
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I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF |
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| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; |
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I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15); |
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// configure pin mux for 3 clock signals |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
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} |
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/******************************************************************/ |
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/******************************************************************/ |
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/******************************************************************/ |
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/******************************************************************/ |
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void AudioInputI2Sslave::begin(void) |
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{ |
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//block_left_1st = NULL; |
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//block_right_1st = NULL; |
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//pinMode(3, OUTPUT); |
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//digitalWriteFast(3, HIGH); |
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//delayMicroseconds(500); |
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//digitalWriteFast(3, LOW); |
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AudioOutputI2Sslave::config_i2s(); |
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CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 |
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DMA_CR = 0; |
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DMA_TCD1_SADDR = &I2S0_RDR0; |
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DMA_TCD1_SOFF = 0; |
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DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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DMA_TCD1_NBYTES_MLNO = 2; |
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DMA_TCD1_SLAST = 0; |
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DMA_TCD1_DADDR = i2s_rx_buffer; |
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DMA_TCD1_DOFF = 2; |
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DMA_TCD1_CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; |
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DMA_TCD1_DLASTSGA = -sizeof(i2s_rx_buffer); |
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DMA_TCD1_BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; |
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DMA_TCD1_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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DMAMUX0_CHCFG1 = DMAMUX_DISABLE; |
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DMAMUX0_CHCFG1 = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE; |
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update_responsibility = update_setup(); |
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DMA_SERQ = 1; |
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// TODO: is I2S_RCSR_BCE appropriate if sync'd to transmitter clock? |
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//I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; |
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I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_FRDE | I2S_RCSR_FR; |
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NVIC_ENABLE_IRQ(IRQ_DMA_CH1); |
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} |
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/******************************************************************/ |
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write(WM8731_REG_DIGITAL, 0x08); // DAC soft mute |
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write(WM8731_REG_DIGITAL, 0x08); // DAC soft mute |
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write(WM8731_REG_ANALOG, 0x00); // disable all |
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write(WM8731_REG_ANALOG, 0x00); // disable all |
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write(WM8731_REG_POWERDOWN, 0x60); // linein, mic, adc, dac, lineout |
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write(WM8731_REG_POWERDOWN, 0x00); // codec powerdown |
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write(WM8731_REG_LHEADOUT, 0x80); // volume off |
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write(WM8731_REG_LHEADOUT, 0x80); // volume off |
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write(WM8731_REG_RHEADOUT, 0x80); |
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write(WM8731_REG_RHEADOUT, 0x80); |
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/******************************************************************/ |
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bool AudioControlWM8731master::enable(void) |
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{ |
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Wire.begin(); |
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delay(5); |
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//write(WM8731_REG_RESET, 0); |
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write(WM8731_REG_INTERFACE, 0x42); // I2S, 16 bit, MCLK master |
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write(WM8731_REG_SAMPLING, 0x20); // 256*Fs, 44.1 kHz, MCLK/1 |
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// In order to prevent pops, the DAC should first be soft-muted (DACMU), |
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// the output should then be de-selected from the line and headphone output |
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// (DACSEL), then the DAC powered down (DACPD). |
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write(WM8731_REG_DIGITAL, 0x08); // DAC soft mute |
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write(WM8731_REG_ANALOG, 0x00); // disable all |
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write(WM8731_REG_POWERDOWN, 0x00); // codec powerdown |
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write(WM8731_REG_LHEADOUT, 0x80); // volume off |
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write(WM8731_REG_RHEADOUT, 0x80); |
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delay(100); // how long to power up? |
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write(WM8731_REG_ACTIVE, 1); |
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delay(5); |
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write(WM8731_REG_DIGITAL, 0x00); // DAC unmuted |
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write(WM8731_REG_ANALOG, 0x10); // DAC selected |
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return true; |
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} |
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/******************************************************************/ |
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/******************************************************************/ |
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#define CHIP_ID 0x0000 |
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#define CHIP_ID 0x0000 |