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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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#if defined(__IMXRT1062__) |
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CORE_PIN8_CONFIG = 3; //1:RX_DATA0 |
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#elif defined(__IMXRT1052__) |
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CORE_PIN7_CONFIG = 3; //1:RX_DATA0 |
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CORE_PIN7_CONFIG = 3; //1:RX_DATA0 |
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#endif |
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IOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 2; |
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IOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 2; |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0+2); |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0+2); |