| dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; | ||||
| dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | ||||
| dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); | dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); | ||||
| dma.enable(); | |||||
| I2S0_TCSR = I2S_TCSR_SR; | I2S0_TCSR = I2S_TCSR_SR; | ||||
| I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; | I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; | ||||
| dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; | ||||
| dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); | dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); | ||||
| dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); | dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); | ||||
| dma.enable(); | |||||
| I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; | I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; | ||||
| I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; | I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; | ||||
| #endif | #endif | ||||
| update_responsibility = update_setup(); | update_responsibility = update_setup(); | ||||
| dma.attachInterrupt(isr); | dma.attachInterrupt(isr); | ||||
| dma.enable(); | |||||
| } | } | ||||