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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma.enable(); |
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I2S0_TCSR = I2S_TCSR_SR; |
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I2S0_TCSR = I2S_TCSR_SR; |
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); |
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dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); |
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dma.enable(); |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; |
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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#endif |
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#endif |
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update_responsibility = update_setup(); |
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update_responsibility = update_setup(); |
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dma.attachInterrupt(isr); |
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dma.attachInterrupt(isr); |
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dma.enable(); |
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} |
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} |
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