various (see below)

input_i2s
input_i2s2
output_i2s2
output_tdm
output_tdm2

Audio.h

 #include "input_adc.h"
 #include "input_adcs.h"
 #include "input_i2s.h"
+#include "input_i2s2.h"
 #include "input_i2s_quad.h"
 #include "input_tdm.h"
 #include "input_pdm.h"
 #include "output_spdif.h"
 #include "output_pt8211.h"
 #include "output_tdm.h"
+#include "output_tdm2.h"
 #include "output_adat.h"
 #include "play_memory.h"
 #include "play_queue.h"

input_i2s2.cpp

+/* Audio Library for Teensy 3.X
+ * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
+ *
+ * Development of this audio library was funded by PJRC.COM, LLC by sales of
+ * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
+ * open source software by purchasing Teensy or other PJRC products.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice, development funding notice, and this permission
+ * notice shall be included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
+#include <Arduino.h>
+#include "input_i2s2.h"
+#include "output_i2s2.h"
+
+static uint32_t i2s2_rx_buffer[AUDIO_BLOCK_SAMPLES];
+audio_block_t * AudioInputI2S2::block_left = NULL;
+audio_block_t * AudioInputI2S2::block_right = NULL;
+uint16_t AudioInputI2S2::block_offset = 0;
+bool AudioInputI2S2::update_responsibility = false;
+DMAChannel AudioInputI2S2::dma(false);
+
+
+void AudioInputI2S2::begin(void)
+{
+	dma.begin(true); // Allocate the DMA channel first
+
+	//block_left_1st = NULL;
+	//block_right_1st = NULL;
+
+	// TODO: should we set & clear the I2S_RCSR_SR bit here?
+	AudioOutputI2S2::config_i2s();
+
+	CORE_PIN33_CONFIG = 2;  //2:RX_DATA0
+	IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0;
+
+	dma.TCD->SADDR = (void *)((uint32_t)&I2S2_RDR0+2);
+	dma.TCD->SOFF = 0;
+	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
+	dma.TCD->NBYTES_MLNO = 2;
+	dma.TCD->SLAST = 0;
+	dma.TCD->DADDR = i2s2_rx_buffer;
+	dma.TCD->DOFF = 2;
+	dma.TCD->CITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
+	dma.TCD->DLASTSGA = -sizeof(i2s2_rx_buffer);
+	dma.TCD->BITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
+	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
+	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);
+
+	I2S2_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE;
+	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE;
+
+	update_responsibility = update_setup();
+	dma.enable();
+	dma.attachInterrupt(isr);
+	//pinMode(13, OUTPUT);
+}
+
+void AudioInputI2S2::isr(void)
+{
+	uint32_t daddr, offset;
+	const int16_t *src, *end;
+	int16_t *dest_left, *dest_right;
+	audio_block_t *left, *right;
+
+	//digitalWriteFast(13, HIGH);
+	daddr = (uint32_t)(dma.TCD->DADDR);
+	dma.clearInterrupt();
+
+	if (daddr < (uint32_t)i2s2_rx_buffer + sizeof(i2s2_rx_buffer) / 2) {
+		// DMA is receiving to the first half of the buffer
+		// need to remove data from the second half
+		src = (int16_t *)&i2s2_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
+		end = (int16_t *)&i2s2_rx_buffer[AUDIO_BLOCK_SAMPLES];
+		if (AudioInputI2S2::update_responsibility) AudioStream::update_all();
+	} else {
+		// DMA is receiving to the second half of the buffer
+		// need to remove data from the first half
+		src = (int16_t *)&i2s2_rx_buffer[0];
+		end = (int16_t *)&i2s2_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
+	}
+	left = AudioInputI2S2::block_left;
+	right = AudioInputI2S2::block_right;
+	if (left != NULL && right != NULL) {
+		offset = AudioInputI2S2::block_offset;
+		if (offset <= AUDIO_BLOCK_SAMPLES/2) {
+			dest_left = &(left->data[offset]);
+			dest_right = &(right->data[offset]);
+			AudioInputI2S2::block_offset = offset + AUDIO_BLOCK_SAMPLES/2;
+
+			do {
+				//Serial.println(*src);
+				//n = *src++;
+				//*dest_left++ = (int16_t)n;
+				//*dest_right++ = (int16_t)(n >> 16);
+				*dest_left++ = *src++;
+				*dest_right++ = *src++;
+			} while (src < end);
+		}
+	}
+	//digitalWriteFast(13, LOW);
+}
+
+
+
+void AudioInputI2S2::update(void)
+{
+	audio_block_t *new_left=NULL, *new_right=NULL, *out_left=NULL, *out_right=NULL;
+
+	// allocate 2 new blocks, but if one fails, allocate neither
+	new_left = allocate();
+	if (new_left != NULL) {
+		new_right = allocate();
+		if (new_right == NULL) {
+			release(new_left);
+			new_left = NULL;
+		}
+	}
+	__disable_irq();
+	if (block_offset >= AUDIO_BLOCK_SAMPLES) {
+		// the DMA filled 2 blocks, so grab them and get the
+		// 2 new blocks to the DMA, as quickly as possible
+		out_left = block_left;
+		block_left = new_left;
+		out_right = block_right;
+		block_right = new_right;
+		block_offset = 0;
+		__enable_irq();
+		// then transmit the DMA's former blocks
+		transmit(out_left, 0);
+		release(out_left);
+		transmit(out_right, 1);
+		release(out_right);
+		//Serial.print(".");
+	} else if (new_left != NULL) {
+		// the DMA didn't fill blocks, but we allocated blocks
+		if (block_left == NULL) {
+			// the DMA doesn't have any blocks to fill, so
+			// give it the ones we just allocated
+			block_left = new_left;
+			block_right = new_right;
+			block_offset = 0;
+			__enable_irq();
+		} else {
+			// the DMA already has blocks, doesn't need these
+			__enable_irq();
+			release(new_left);
+			release(new_right);
+		}
+	} else {
+		// The DMA didn't fill blocks, and we could not allocate
+		// memory... the system is likely starving for memory!
+		// Sadly, there's nothing we can do.
+		__enable_irq();
+	}
+}
+
+
+/******************************************************************/
+
+#if 0
+void AudioInputI2S2slave::begin(void)
+{
+	dma.begin(true); // Allocate the DMA channel first
+
+	//block_left_1st = NULL;
+	//block_right_1st = NULL;
+
+	AudioOutputI2S2slave::config_i2s();
+
+	CORE_PIN33_CONFIG = 2;  //2:RX_DATA0
+	IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0;
+
+	dma.TCD->SADDR = (void *)((uint32_t)&I2S2_RDR0 + 2);
+	dma.TCD->SOFF = 0;
+	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
+	dma.TCD->NBYTES_MLNO = 2;
+	dma.TCD->SLAST = 0;
+	dma.TCD->DADDR = i2s2_rx_buffer;
+	dma.TCD->DOFF = 2;
+	dma.TCD->CITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
+	dma.TCD->DLASTSGA = -sizeof(i2s2_rx_buffer);
+	dma.TCD->BITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
+	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
+
+	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);
+	update_responsibility = update_setup();
+	dma.enable();
+
+	I2S2_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
+	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
+	dma.attachInterrupt(isr);
+
+}
+#endif
+#endif

input_i2s2.h

+/* Audio Library for Teensy 3.X
+ * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
+ *
+ * Development of this audio library was funded by PJRC.COM, LLC by sales of
+ * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
+ * open source software by purchasing Teensy or other PJRC products.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice, development funding notice, and this permission
+ * notice shall be included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
+#ifndef _input_i2s2_h_
+#define _input_i2s2_h_
+
+#include "Arduino.h"
+#include "AudioStream.h"
+#include "DMAChannel.h"
+
+class AudioInputI2S2 : public AudioStream
+{
+public:
+	AudioInputI2S2(void) : AudioStream(0, NULL) { begin(); }
+	virtual void update(void);
+	void begin(void);
+protected:
+	AudioInputI2S2(int dummy): AudioStream(0, NULL) {} // to be used only inside AudioInputI2Sslave !!
+	static bool update_responsibility;
+	static DMAChannel dma;
+	static void isr(void);
+private:
+	static audio_block_t *block_left;
+	static audio_block_t *block_right;
+	static uint16_t block_offset;
+};
+
+
+class AudioInputI2S2slave : public AudioInputI2S2
+{
+public:
+	AudioInputI2S2slave(void) : AudioInputI2S2(0) { begin(); }
+	void begin(void);
+	friend void dma_ch1_isr(void);
+};
+
+#endif
+#endif //#if defined(__IMXRT1052__) || defined(__IMXRT1062__)

keywords.txt

 Audio	KEYWORD2
 AudioConnection	KEYWORD2
 AudioInputI2S	KEYWORD2
+AudioInputI2S2	KEYWORD2
 AudioInputI2SQuad	KEYWORD2
 AudioInputI2Sslave	KEYWORD2
 AudioInputTDM	KEYWORD2
 AudioInputPDM	KEYWORD2
 AudioInputUSB	KEYWORD2
 AudioOutputI2S	KEYWORD2
+AudioOutputI2S2	KEYWORD2
 AudioOutputI2SQuad	KEYWORD2
 AudioOutputI2Sslave	KEYWORD2
 AudioOutputSPDIF	KEYWORD2

output_i2s.cpp

 #if defined(__IMXRT1052__) || defined(__IMXRT1062__)
 #include "utility/imxrt_hw.h"
 
-//TODO: Copy these to imrtx.h:
-#if !defined(I2S_TCR2_BCP)
-#define I2S_TCR2_BCP			((uint32_t)1<<25)
-#define I2S_RCR2_BCP			((uint32_t)1<<25)
-#define I2S_TCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error
-#define I2S_RCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error
-#define I2S_TCR4_FSP			((uint32_t)1<< 1)
-#define I2S_RCR4_FSP			((uint32_t)1<< 1)
-#endif
 
 void AudioOutputI2S::begin(void)
 {
 
 	config_i2s();
 	CORE_PIN6_CONFIG  = 3;  //1:TX_DATA0
-  #if defined(SAI2)
-  	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
-  #endif
 
 	dma.TCD->SADDR = i2s_tx_buffer;
 	dma.TCD->SOFF = 2;
 	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
 	dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2);
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
-	//I2S1_RCSR = (1<<25); //Reset
-	//I2S1_TCSR = (1<<25); //Reset
+
 	I2S1_RCSR |= I2S_RCSR_RE;
-	//I2S1_TCSR = I2S_TCSR_SR;
 	I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
-#if defined(SAI2)
-	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
-	I2S2_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;  //SAI2
-#endif
+
 	update_responsibility = update_setup();
 	dma.attachInterrupt(isr);
 	dma.enable();
 //	CORE_PIN6_CONFIG  = 3;  //1:TX_DATA0
 //	CORE_PIN7_CONFIG  = 3;  //1:RX_DATA0
 
-#if defined(SAI2)
-	i2s = ((I2S_STRUCT *)0x40388000);
-	if (i2s->TX.CSR & I2S_TCSR_TE) return;
-	if (i2s->RX.CSR & I2S_RCSR_RE) return;
-
-	CORE_PIN5_CONFIG  = 2;  //2:MCLK
-	CORE_PIN4_CONFIG  = 2;  //2:TX_BCLK
-	CORE_PIN3_CONFIG  = 2;  //2:TX_SYNC
-//	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
-//	CORE_PIN33_CONFIG = 2;  //2:RX_DATA0
-#endif
-
 	int rsync = 0;
 	int tsync = 1;
 
 	I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
 	I2S1_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1));
 
-
-#if defined(SAI2)
-	CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
-
-	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
-		   | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
-	CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
-		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
-	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
-			| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0));	//Select MCLK
-	sai_rxConfig(32, 2, 1);
-	sai_txConfig(32, 2, 0);
-
-#endif
-
 #endif
 }
 

output_i2s.h

 #include "AudioStream.h"
 #include "DMAChannel.h"
 
-/*
-typedef struct
-{
-  uint32_t CSR;
-  uint32_t CR1,CR2,CR3,CR4,CR5;
-  union {
-	uint32_t DR[8];
-	uint16_t DR16[16];
-  };
-  uint32_t FR[8];
-  uint32_t MR;
-} I2S_PORT;
-
-typedef struct
-{
-  uint32_t VERID;
-  uint32_t PARAM;
-  I2S_PORT TX;
-  uint32_t unused[9];
-  I2S_PORT RX;
-} I2S_STRUCT;
-*/
-
 class AudioOutputI2S : public AudioStream
 {
 public:

output_i2s2.cpp

 uint16_t  AudioOutputI2S2::block_left_offset = 0;
 uint16_t  AudioOutputI2S2::block_right_offset = 0;
 bool AudioOutputI2S2::update_responsibility = false;
-static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
+static uint32_t i2s2_tx_buffer[AUDIO_BLOCK_SAMPLES];
 DMAChannel AudioOutputI2S2::dma(false);
 
 
 	config_i2s();
   	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
 
-	dma.TCD->SADDR = i2s_tx_buffer;
+	dma.TCD->SADDR = i2s2_tx_buffer;
 	dma.TCD->SOFF = 2;
 	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
 	dma.TCD->NBYTES_MLNO = 2;
-	dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
+	dma.TCD->SLAST = -sizeof(i2s2_tx_buffer);
 	dma.TCD->DOFF = 0;
-	dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
+	dma.TCD->CITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
 	dma.TCD->DLASTSGA = 0;
-	dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
+	dma.TCD->BITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
 	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
 	dma.TCD->DADDR = (void *)((uint32_t)&I2S2_TDR0 + 2);
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
 
 	saddr = (uint32_t)(dma.TCD->SADDR);
 	dma.clearInterrupt();
-	if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
+	if (saddr < (uint32_t)i2s2_tx_buffer + sizeof(i2s2_tx_buffer) / 2) {
 		// DMA is transmitting the first half of the buffer
 		// so we must fill the second half
-		dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
+		dest = (int16_t *)&i2s2_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
 		if (AudioOutputI2S2::update_responsibility) AudioStream::update_all();
 	} else {
 		// DMA is transmitting the second half of the buffer
 		// so we must fill the first half
-		dest = (int16_t *)i2s_tx_buffer;
+		dest = (int16_t *)i2s2_tx_buffer;
 	}
 
 	blockL = AudioOutputI2S2::block_left_1st;
 }
 
 void AudioOutputI2S2::config_i2s(void)
-{	
+{
 	CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
 //PLL:
 	int fs = AUDIO_SAMPLE_RATE_EXACT;
 	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
 		   | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
 	CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
-		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
+		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) 
+		   | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
 	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
 			| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0));	//Select MCLK
 
 
 }
 
-
-
 /******************************************************************/
 #if 0
-void AudioOutputI2Sslave::begin(void)
+void AudioOutputI2S2slave::begin(void)
 {
 	dma.begin(true); // Allocate the DMA channel first
 
 	block_left_1st = NULL;
 	block_right_1st = NULL;
 
-	AudioOutputI2Sslave::config_i2s();
+	AudioOutputI2S2slave::config_i2s();
 
-#if defined(KINETISK)
-	CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
-	dma.TCD->SADDR = i2s_tx_buffer;
-	dma.TCD->SOFF = 2;
-	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
-	dma.TCD->NBYTES_MLNO = 2;
-	dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
-	dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
-	dma.TCD->DOFF = 0;
-	dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
-	dma.TCD->DLASTSGA = 0;
-	dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
-	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
-	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
-	I2S0_TCSR = I2S_TCSR_SR;
-	I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
-
-#elif 0 && ( defined(__IMXRT1052__) || defined(__IMXRT1062__) )
-#if defined(SAI1)
-	CORE_PIN6_CONFIG  = 3;  //1:TX_DATA0
-	//CORE_PIN7_CONFIG  = 3;  //1:RX_DATA0
-#elif defined(SAI2)
 	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
 	//CORE_PIN33_CONFIG = 2;  //2:RX_DATA0
-#endif
-	dma.TCD->SADDR = i2s_tx_buffer;
+
+	dma.TCD->SADDR = i2s2_tx_buffer;
 	dma.TCD->SOFF = 2;
 	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
 	dma.TCD->NBYTES_MLNO = 2;
-	dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
-	dma.TCD->DADDR = (void *)&i2s->TX.DR16[1];
+	dma.TCD->SLAST = -sizeof(i2s2_tx_buffer);
+	dma.TCD->DADDR = (void *)((uint32_t)&I2S2_TDR0 + 2);
 	dma.TCD->DOFF = 0;
-	dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
+	dma.TCD->CITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
 	dma.TCD->DLASTSGA = 0;
-	dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
+	dma.TCD->BITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
-#endif
 
 	update_responsibility = update_setup();
 	dma.enable();
 	dma.attachInterrupt(isr);
 }
 
-void AudioOutputI2Sslave::config_i2s(void)
+void AudioOutputI2S2slave::config_i2s(void)
 {
-#if defined(KINETISK)
-	// if either transmitter or receiver is enabled, do nothing
-	if (I2S0_TCSR & I2S_TCSR_TE) return;
-	if (I2S0_RCSR & I2S_RCSR_RE) return;
-
-	SIM_SCGC6 |= SIM_SCGC6_I2S;
-	SIM_SCGC7 |= SIM_SCGC7_DMA;
-	SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
-	// configure pin mux for 3 clock signals
-
-	CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
-	CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin  9, PTC3, I2S0_TX_BCLK
-	CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
-	// Select input clock 0
-	// Configure to input the bit-clock from pin, bypasses the MCLK divider
-	I2S0_MCR = I2S_MCR_MICS(0);
-	I2S0_MDR = 0;
-
-	// configure transmitter
-	I2S0_TMR = 0;
-	I2S0_TCR1 = I2S_TCR1_TFW(1);  // watermark at half fifo size
-	I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;
-
-	I2S0_TCR3 = I2S_TCR3_TCE;
-	I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
-		| I2S_TCR4_FSE | I2S_TCR4_FSP;
 
-	I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
 
-	// configure receiver (sync'd to transmitter clocks)
-	I2S0_RMR = 0;
-	I2S0_RCR1 = I2S_RCR1_RFW(1);
-	I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;
-
-	I2S0_RCR3 = I2S_RCR3_RCE;
-	I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
-		| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
-
-	I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
-
-#elif 0 && (defined(__IMXRT1052__) || defined(__IMXRT1062__) )
-
-  #if defined(SAI1)
-	i2s = ((I2S_STRUCT *)0x40384000);
-	// if either transmitter or receiver is enabled, do nothing
-	if (i2s->TX.CSR & I2S_TCSR_TE) return;
-	if (i2s->RX.CSR & I2S_RCSR_RE) return;
-
-	CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
-/*
-	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
-		   | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
-	CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
-		   | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
-		   | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
-*/
-//TODO:
-	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | ((uint32_t)(1<<20)) ))
-			| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0));	//Select MCLK
-
-	CORE_PIN23_CONFIG = 3;  //1:MCLK
-	CORE_PIN21_CONFIG = 3;  //1:RX_BCLK
-	CORE_PIN20_CONFIG = 3;  //1:RX_SYNC
-	int rsync = 0;
-	int tsync = 1;
-  #elif defined(SAI2)
-	i2s = ((I2S_STRUCT *)0x40388000);
-	if (i2s->TX.CSR & I2S_TCSR_TE) return;
-	if (i2s->RX.CSR & I2S_RCSR_RE) return;
+	if (I2S2_TCSR & I2S_TCSR_TE) return;
+	if (I2S2_TCSR & I2S_RCSR_RE) return;
 
 	CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
 /*
 	CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
 		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
 */
-//TODO:
-
-	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | ((uint32_t)(1<<19)) ))
-			/*| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR*/ | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0);	//Select MCLK
+//	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | ((uint32_t)(1<<19)) ))
+//			/*| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR*/ | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0);	//Select MCLK
 
 	CORE_PIN5_CONFIG  = 2;  //2:MCLK
 	CORE_PIN4_CONFIG  = 2;  //2:TX_BCLK
 	int rsync = 1;
 	int tsync = 0;
 
-  #endif
-
 	// configure transmitter
-	i2s->TX.MR = 0;
-	i2s->TX.CR1 = I2S_TCR1_RFW(1);  // watermark at half fifo size
-	i2s->TX.CR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP;
-	i2s->TX.CR3 = I2S_TCR3_TCE;
-	i2s->TX.CR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
+	I2S2_TMR = 0;
+	I2S2_TCR1 = I2S_TCR1_RFW(1);  // watermark at half fifo size
+	I2S2_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP;
+	I2S2_TCR3 = I2S_TCR3_TCE;
+	I2S2_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
 		    | I2S_TCR4_FSE | I2S_TCR4_FSP;
-	i2s->TX.CR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
+	I2S2_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
 
 	// configure receiver
-	i2s->RX.MR = 0;
-	i2s->RX.CR1 = I2S_RCR1_RFW(1);
-	i2s->RX.CR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP;
-	i2s->RX.CR3 = I2S_RCR3_RCE;
-	i2s->RX.CR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
+	I2S2_TMR = 0;
+	I2S2_TCR1 = I2S_RCR1_RFW(1);
+	I2S2_TCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP;
+	I2S2_TCR3 = I2S_RCR3_RCE;
+	I2S2_TCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
 		    | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
-	i2s->RX.CR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
-
-#endif
+	I2S2_TCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
+	
 }
-#endif //if 0
-#endif //defined(__IMXRT1062__)
+#endif
+#endif //defined(__IMXRT1062__)

output_i2s2.h

 	AudioOutputI2S2(void) : AudioStream(2, inputQueueArray) { begin(); }
 	virtual void update(void);
 	void begin(void);
-	friend class AudioInputI2S;
+	friend class AudioInputI2S2;
 protected:
 	AudioOutputI2S2(int dummy): AudioStream(2, inputQueueArray) {} // to be used only inside AudioOutputI2Sslave !!
 	static void config_i2s(void);
 	audio_block_t *inputQueueArray[2];
 };
 
-#if 0
-class AudioOutputI2Sslave : public AudioOutputI2S
+
+class AudioOutputI2S2slave : public AudioOutputI2S2
 {
 public:
-	AudioOutputI2Sslave(void) : AudioOutputI2S(0) { begin(); } ;
+	AudioOutputI2S2slave(void) : AudioOutputI2S2(0) { begin(); } ;
 	void begin(void);
-	friend class AudioInputI2Sslave;
+	friend class AudioInputI2S2slave;
 	friend void dma_ch0_isr(void);
 protected:
 	static void config_i2s(void);
 };
-#endif
+
 
 #endif
 #endif //defined(__IMXRT1062__)

output_tdm.cpp

 #include <Arduino.h>
 #include "output_tdm.h"
 #include "memcpy_audio.h"
-#if defined(KINETISK)
+#include "utility/imxrt_hw.h"
+
+#if !defined(I2S_TCR2_BCP)
+#define I2S_TCR2_BCP			((uint32_t)1<<25)
+#define I2S_RCR2_BCP			((uint32_t)1<<25)
+#define I2S_TCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error
+#define I2S_RCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error
+#define I2S_TCR4_FSP			((uint32_t)1<< 1)
+#define I2S_RCR4_FSP			((uint32_t)1<< 1)
+#endif
 
 audio_block_t * AudioOutputTDM::block_input[16] = {
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 };
 bool AudioOutputTDM::update_responsibility = false;
 static uint32_t zeros[AUDIO_BLOCK_SAMPLES/2];
-DMAMEM static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16];
+static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16];
 DMAChannel AudioOutputTDM::dma(false);
 
 void AudioOutputTDM::begin(void)
 
 	// TODO: should we set & clear the I2S_TCSR_SR bit here?
 	config_tdm();
+#if defined(KINETISK)
 	CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
 
 	dma.TCD->SADDR = tdm_tx_buffer;
 	dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
 	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
+
 	update_responsibility = update_setup();
 	dma.enable();
 
 	I2S0_TCSR = I2S_TCSR_SR;
 	I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
+#elif defined(__IMXRT1052__) || defined(__IMXRT1062__)
+	CORE_PIN6_CONFIG  = 3;  //1:TX_DATA0
+
+	dma.TCD->SADDR = tdm_tx_buffer;
+	dma.TCD->SOFF = 4;
+	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
+	dma.TCD->NBYTES_MLNO = 4;
+	dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
+	dma.TCD->DADDR = &I2S1_TDR0;
+	dma.TCD->DOFF = 0;
+	dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
+	dma.TCD->DLASTSGA = 0;
+	dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
+	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
+	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
+
+	update_responsibility = update_setup();
+	dma.enable();
+
+	I2S1_RCSR |= I2S_RCSR_RE;
+	I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
+
+#endif
 	dma.attachInterrupt(isr);
 }
 
 	}
 }
 
-
+#if defined(KINETISK)
 // MCLK needs to be 48e6 / 1088 * 512 = 22.588235 MHz -> 44.117647 kHz sample rate
 //
 #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
   #define MCLK_SRC  0  // system clock
 #endif
 #endif
+#endif
 
 void AudioOutputTDM::config_tdm(void)
 {
+#if defined(KINETISK)
 	SIM_SCGC6 |= SIM_SCGC6_I2S;
 	SIM_SCGC7 |= SIM_SCGC7_DMA;
 	SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
 	CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
 	CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin  9, PTC3, I2S0_TX_BCLK
 	CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
-}
 
+#elif defined(__IMXRT1052__) || defined(__IMXRT1062__)
+	CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
+//PLL:
+	int fs = AUDIO_SAMPLE_RATE_EXACT*2;
+	// PLL between 27*24 = 648MHz und 54*24=1296MHz
+	int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
+	int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
+
+	double C = ((double)fs * 256 * n1 * n2) / 24000000;
+	int c0 = C;
+	int c2 = 10000;
+	int c1 = C * c2 - (c0 * c2);
+	set_audioClock(c0, c1, c2);
+	// clear SAI1_CLK register locations
+	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
+		   | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
+
+	//n1 = n1 / 2; //Double Speed for TDM
+
+	CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
+		   | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
+		   | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
+
+	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
+			| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0));	//Select MCLK
+
+	// if either transmitter or receiver is enabled, do nothing
+	if (I2S1_TCSR & I2S_TCSR_TE) return;
+	if (I2S1_RCSR & I2S_RCSR_RE) return;
+
+	// configure transmitter
+	int rsync = 0;
+	int tsync = 1;
+
+	I2S1_TMR = 0;
+	I2S1_TCR1 = I2S_TCR1_RFW(4);
+	I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
+		| I2S_TCR2_BCD | I2S_TCR2_DIV(0);
+	I2S1_TCR3 = I2S_TCR3_TCE;
+	I2S1_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
+		| I2S_TCR4_FSE | I2S_TCR4_FSD;
+	I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
 
+	// configure receiver (sync'd to transmitter clocks)
+	I2S1_RMR = 0;
+	I2S1_RCR1 = I2S_RCR1_RFW(4);
+	I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
+		| I2S_RCR2_BCD | I2S_RCR2_DIV(0);
+	I2S1_RCR3 = I2S_RCR3_RCE;
+	I2S1_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
+		| I2S_RCR4_FSE | I2S_RCR4_FSD;
+	I2S1_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
+
+	CORE_PIN23_CONFIG = 3;  //1:MCLK
+	CORE_PIN21_CONFIG = 3;  //1:RX_BCLK
+	CORE_PIN20_CONFIG = 3;  //1:RX_SYNC
+#endif
+}
 
-#endif // KINETISK

output_tdm2.cpp

+/* Audio Library for Teensy 3.X
+ * Copyright (c) 2017, Paul Stoffregen, paul@pjrc.com
+ *
+ * Development of this audio library was funded by PJRC.COM, LLC by sales of
+ * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
+ * open source software by purchasing Teensy or other PJRC products.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice, development funding notice, and this permission
+ * notice shall be included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+ #if defined(__IMXRT1052__) || defined(__IMXRT1062__)
+#include <Arduino.h>
+#include "output_tdm2.h"
+#include "memcpy_audio.h"
+#include "utility/imxrt_hw.h"
+
+audio_block_t * AudioOutputTDM2::block_input[16] = {
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+};
+bool AudioOutputTDM2::update_responsibility = false;
+static uint32_t zeros[AUDIO_BLOCK_SAMPLES/2];
+static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16];
+DMAChannel AudioOutputTDM2::dma(false);
+
+void AudioOutputTDM2::begin(void)
+{
+	dma.begin(true); // Allocate the DMA channel first
+
+	for (int i=0; i < 16; i++) {
+		block_input[i] = NULL;
+	}
+
+	// TODO: should we set & clear the I2S_TCSR_SR bit here?
+	config_tdm();
+
+	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
+
+	dma.TCD->SADDR = tdm_tx_buffer;
+	dma.TCD->SOFF = 4;
+	dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
+	dma.TCD->NBYTES_MLNO = 4;
+	dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
+	dma.TCD->DADDR = &I2S2_TDR0;
+	dma.TCD->DOFF = 0;
+	dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
+	dma.TCD->DLASTSGA = 0;
+	dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
+	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
+	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
+
+	update_responsibility = update_setup();
+	dma.enable();
+
+	//I2S2_RCSR |= I2S_RCSR_RE;
+	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
+
+	dma.attachInterrupt(isr);
+}
+
+// TODO: needs optimization...
+static void memcpy_tdm_tx(uint32_t *dest, const uint32_t *src1, const uint32_t *src2)
+{
+	uint32_t i, in1, in2, out1, out2;
+
+	for (i=0; i < AUDIO_BLOCK_SAMPLES/2; i++) {
+		in1 = *src1++;
+		in2 = *src2++;
+		out1 = (in1 << 16) | (in2 & 0xFFFF);
+		out2 = (in1 & 0xFFFF0000) | (in2 >> 16);
+		*dest = out1;
+		*(dest + 8) = out2;
+		dest += 16;
+	}
+}
+
+void AudioOutputTDM2::isr(void)
+{
+	uint32_t *dest;
+	const uint32_t *src1, *src2;
+	uint32_t i, saddr;
+
+	saddr = (uint32_t)(dma.TCD->SADDR);
+	dma.clearInterrupt();
+	if (saddr < (uint32_t)tdm_tx_buffer + sizeof(tdm_tx_buffer) / 2) {
+		// DMA is transmitting the first half of the buffer
+		// so we must fill the second half
+		dest = tdm_tx_buffer + AUDIO_BLOCK_SAMPLES*8;
+	} else {
+		// DMA is transmitting the second half of the buffer
+		// so we must fill the first half
+		dest = tdm_tx_buffer;
+	}
+	if (update_responsibility) AudioStream::update_all();
+	for (i=0; i < 16; i += 2) {
+		src1 = block_input[i] ? (uint32_t *)(block_input[i]->data) : zeros;
+		src2 = block_input[i+1] ? (uint32_t *)(block_input[i+1]->data) : zeros;
+		memcpy_tdm_tx(dest, src1, src2);
+		dest++;
+	}
+	for (i=0; i < 16; i++) {
+		if (block_input[i]) {
+			release(block_input[i]);
+			block_input[i] = NULL;
+		}
+	}
+}
+
+
+void AudioOutputTDM2::update(void)
+{
+	audio_block_t *prev[16];
+	unsigned int i;
+
+	__disable_irq();
+	for (i=0; i < 16; i++) {
+		prev[i] = block_input[i];
+		block_input[i] = receiveReadOnly(i);
+	}
+	__enable_irq();
+	for (i=0; i < 16; i++) {
+		if (prev[i]) release(prev[i]);
+	}
+}
+
+void AudioOutputTDM2::config_tdm(void)
+{
+
+	CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
+//PLL:
+	int fs = AUDIO_SAMPLE_RATE_EXACT*2; //176.4 khZ
+	// PLL between 27*24 = 648MHz und 54*24=1296MHz
+	int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
+	int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
+
+	double C = ((double)fs * 256 * n1 * n2) / 24000000;
+	int c0 = C;
+	int c2 = 10000;
+	int c1 = C * c2 - (c0 * c2);
+	set_audioClock(c0, c1, c2);
+	// clear SAI1_CLK register locations
+
+	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
+		   | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
+
+	//n1 = n1 / 2; //Double Speed for TDM
+
+	CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
+		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) // &0x07
+		   | CCM_CS2CDR_SAI2_CLK_PODF(n2-1); // &0x3f
+
+	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
+			| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0));	//Select MCLK
+
+
+
+	// if either transmitter or receiver is enabled, do nothing
+	if (I2S2_TCSR & I2S_TCSR_TE) return;
+	if (I2S2_RCSR & I2S_RCSR_RE) return;
+
+	// configure transmitter
+	int rsync = 1;
+	int tsync = 0;
+
+	I2S2_TMR = 0;
+	I2S2_TCR1 = I2S_TCR1_RFW(4);
+	I2S2_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
+		| I2S_TCR2_BCD | I2S_TCR2_DIV(0);
+	I2S2_TCR3 = I2S_TCR3_TCE;
+	I2S2_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
+		| I2S_TCR4_FSE | I2S_TCR4_FSD;
+	I2S2_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
+
+	// configure receiver (sync'd to transmitter clocks)
+	I2S2_RMR = 0;
+	I2S2_RCR1 = I2S_RCR1_RFW(4);
+	I2S2_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
+		| I2S_RCR2_BCD | I2S_RCR2_DIV(0);
+	I2S2_RCR3 = I2S_RCR3_RCE;
+	I2S2_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
+		| I2S_RCR4_FSE | I2S_RCR4_FSD;
+	I2S2_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
+
+	CORE_PIN5_CONFIG  = 2;  //2:MCLK
+	CORE_PIN4_CONFIG  = 2;  //2:TX_BCLK
+	CORE_PIN3_CONFIG  = 2;  //2:TX_SYNC
+
+}
+
+#endif

output_tdm2.h

+/* Audio Library for Teensy 3.X
+ * Copyright (c) 2017, Paul Stoffregen, paul@pjrc.com
+ *
+ * Development of this audio library was funded by PJRC.COM, LLC by sales of
+ * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
+ * open source software by purchasing Teensy or other PJRC products.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice, development funding notice, and this permission
+ * notice shall be included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
+#ifndef output_tdm2_h_
+#define output_tdm2_h_
+
+#include "Arduino.h"
+#include "AudioStream.h"
+#include "DMAChannel.h"
+
+class AudioOutputTDM2 : public AudioStream
+{
+public:
+	AudioOutputTDM2(void) : AudioStream(16, inputQueueArray) { begin(); }
+	virtual void update(void);
+	void begin(void);
+	friend class AudioInputTDM2;
+protected:
+	static void config_tdm(void);
+	static audio_block_t *block_input[16];
+	static bool update_responsibility;
+	static DMAChannel dma;
+	static void isr(void);
+private:
+	audio_block_t *inputQueueArray[16];
+};
+
+
+#endif
+#endif