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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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CORE_PIN7_CONFIG = 3; //1:RX_DATA0 |
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CORE_PIN7_CONFIG = 3; //1:RX_DATA0 |
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IOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 2; |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0+2); |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0+2); |
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dma.TCD->SOFF = 0; |
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dma.TCD->SOFF = 0; |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX); |
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// I2S1_RCSR = 0; |
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// I2S1_TCSR = 0; |
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// I2S1_RCSR = (1<<25); //Reset |
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// I2S1_TCSR = (1<<25); //Reset |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE; |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE; |
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I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; |
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I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; |
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/* |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; |
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I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX |
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*/ |
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#endif |
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#endif |
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update_responsibility = update_setup(); |
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update_responsibility = update_setup(); |
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void AudioInputI2Sslave::begin(void) |
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void AudioInputI2Sslave::begin(void) |
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{ |
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{ |
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#if 0 |
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dma.begin(true); // Allocate the DMA channel first |
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dma.begin(true); // Allocate the DMA channel first |
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//block_left_1st = NULL; |
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//block_left_1st = NULL; |
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//block_right_1st = NULL; |
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//block_right_1st = NULL; |
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AudioOutputI2Sslave::config_i2s(); |
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AudioOutputI2Sslave::config_i2s(); |
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CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 |
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#if defined(KINETISK) |
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#if defined(KINETISK) |
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CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0 |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2); |
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dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2); |
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dma.TCD->SOFF = 0; |
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dma.TCD->SOFF = 0; |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer); |
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dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer); |
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dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; |
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dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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#endif |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX); |
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update_responsibility = update_setup(); |
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update_responsibility = update_setup(); |
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dma.enable(); |
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dma.enable(); |
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I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; |
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I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX |
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dma.attachInterrupt(isr); |
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dma.attachInterrupt(isr); |
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#endif |
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#endif |
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} |
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} |
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