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/* Audio Library for Teensy 3.X |
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* Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com |
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* |
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* Development of this audio library was funded by PJRC.COM, LLC by sales of |
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* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop |
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* open source software by purchasing Teensy or other PJRC products. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice, development funding notice, and this permission |
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* notice shall be included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#include "control_cs42448.h" |
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#include "Wire.h" |
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#define CS42448_Chip_ID 0x01 |
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#define CS42448_Power_Control 0x02 |
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#define CS42448_Functional_Mode 0x03 |
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#define CS42448_Interface_Formats 0x04 |
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#define CS42448_ADC_Control_DAC_DeEmphasis 0x05 |
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#define CS42448_Transition_Control 0x06 |
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#define CS42448_DAC_Channel_Mute 0x07 |
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#define CS42448_AOUT1_Volume_Control 0x08 |
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#define CS42448_AOUT2_Volume_Control 0x09 |
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#define CS42448_AOUT3_Volume_Control 0x0A |
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#define CS42448_AOUT4_Volume_Control 0x0B |
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#define CS42448_AOUT5_Volume_Control 0x0C |
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#define CS42448_AOUT6_Volume_Control 0x0D |
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#define CS42448_AOUT7_Volume_Control 0x0E |
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#define CS42448_AOUT8_Volume_Control 0x0F |
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#define CS42448_DAC_Channel_Invert 0x10 |
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#define CS42448_AIN1_Volume_Control 0x11 |
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#define CS42448_AIN2_Volume_Control 0x12 |
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#define CS42448_AIN3_Volume_Control 0x13 |
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#define CS42448_AIN4_Volume_Control 0x14 |
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#define CS42448_AIN5_Volume_Control 0x15 |
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#define CS42448_AIN6_Volume_Control 0x16 |
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#define CS42448_ADC_Channel_Invert 0x17 |
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#define CS42448_Status_Control 0x18 |
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#define CS42448_Status 0x19 |
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#define CS42448_Status_Mask 0x1A |
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#define CS42448_MUTEC_Pin_Control 0x1B |
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// 4.9 Recommended Power-Up Sequence |
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// 1. Hold RST low until the power supply and clocks are stable. In this state, |
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// the control port is reset to its default settings and VQ will remain low. |
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// 2. Bring RST high. The device will initially be in a low power state with VQ |
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// low. All features will default as described in the "Register Quick Reference" |
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// on page 40. |
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// 3. Perform a write operation to the Power Control register ("Power Control |
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// (Address 02h)" on page 43) to set bit 0 to a '1'b. This will place the |
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// device in a power down state. |
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// 4. Load the desired register settings while keeping the PDN bit set to '1'b. |
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// 5. Mute all DACs. Muting the DACs suppresses any noise associated with the |
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// CODEC's first initialization after power is applied. |
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// 6. Set the PDN bit in the power control register to '0'b. VQ will ramp to |
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// approximately VA/2 according to the Popguard specification in section |
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// "Popguard" on page 29. |
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// 7. Following approximately 2000 LRCK cycles, the device is initialized and |
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// ready for normal operation. |
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// 8. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and |
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// then un-mute the DACs. |
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// 9. Normal operation begins. |
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static const uint8_t default_config[] = { |
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0xF4, // CS42448_Functional_Mode = slave mode, MCLK 25.6 MHz max |
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0x76, // CS42448_Interface_Formats = TDM mode |
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0x1C, // CS42448_ADC_Control_DAC_DeEmphasis = single ended ADC |
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0x63, // CS42448_Transition_Control = soft vol control |
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0xFF // CS42448_DAC_Channel_Mute = all outputs mute |
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}; |
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bool AudioControlCS42448::enable(void) |
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{ |
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Wire.begin(); |
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// TODO: wait for reset signal high?? |
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if (!write(CS42448_Power_Control, 0xFF)) return false; // power down |
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if (!write(CS42448_Functional_Mode, default_config, sizeof(default_config))) return false; |
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if (!write(CS42448_Power_Control, 0)) return false; // power up |
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return true; |
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} |
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bool AudioControlCS42448::volumeInteger(uint32_t n) |
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{ |
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uint8_t data[9]; |
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data[0] = 0; |
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for (int i=1; i < 9; i++) { |
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data[i] = n; |
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} |
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return write(CS42448_DAC_Channel_Mute, data, 9); |
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} |
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bool AudioControlCS42448::volumeInteger(int channel, uint32_t n) |
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{ |
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return true; |
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} |
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bool AudioControlCS42448::inputLevelInteger(int32_t n) |
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{ |
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return true; |
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} |
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bool AudioControlCS42448::inputLevelInteger(int chnnel, int32_t n) |
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{ |
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return true; |
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} |
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bool AudioControlCS42448::write(uint32_t address, uint32_t data) |
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{ |
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Wire.beginTransmission(i2c_addr); |
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Wire.write(address); |
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Wire.write(data); |
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if (Wire.endTransmission() == 0) return true; |
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return false; |
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} |
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bool AudioControlCS42448::write(uint32_t address, const void *data, uint32_t len) |
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{ |
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Wire.beginTransmission(i2c_addr); |
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Wire.write(address | 0x80); |
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const uint8_t *p = (const uint8_t *)data; |
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const uint8_t *end = p + len; |
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while (p < end) { |
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Wire.write(*p++); |
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} |
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if (Wire.endTransmission() == 0) return true; |
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return false; |
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} |
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