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@@ -26,9 +26,9 @@ |
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//Adapted to PT8211, Frank Bösing, Ben-Rheinland |
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#include <Arduino.h> |
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#include "output_pt8211.h" |
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#if !defined(KINETISL) |
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#include "memcpy_audio.h" |
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#include "utility/imxrt_hw.h" |
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@@ -48,7 +48,9 @@ DMAChannel AudioOutputPT8211::dma(false); |
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void AudioOutputPT8211::begin(void) |
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{ |
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memset(i2s_tx_buffer, 0, sizeof(i2s_tx_buffer)); |
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dma.begin(true); // Allocate the DMA channel first |
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block_left_1st = NULL; |
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@@ -78,12 +80,12 @@ void AudioOutputPT8211::begin(void) |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; |
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return; |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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#if defined(__IMXRT1052__) |
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CORE_PIN6_CONFIG = 3; //1:TX_DATA0 |
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#elif defined(__IMXRT1062__) |
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arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); |
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
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arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); |
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
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#endif |
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dma.TCD->SADDR = i2s_tx_buffer; |
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@@ -106,7 +108,7 @@ void AudioOutputPT8211::begin(void) |
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dma.attachInterrupt(isr); |
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dma.enable(); |
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return; |
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#endif |
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#endif |
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} |
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void AudioOutputPT8211::isr(void) |
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@@ -501,7 +503,7 @@ void AudioOutputPT8211::config_i2s(void) |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
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//CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
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#elif ( defined(__IMXRT1052__) || defined(__IMXRT1062__) ) |
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CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); |
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@@ -556,9 +558,174 @@ void AudioOutputPT8211::config_i2s(void) |
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I2S1_RCR1 = I2S_RCR1_RFW(0); |
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I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP | I2S_RCR2_MSEL(1) | I2S_TCR2_BCD | I2S_TCR2_DIV(div); |
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I2S1_RCR3 = I2S_RCR3_RCE; |
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// I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; //TDA1543 |
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// I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; //TDA1543 |
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I2S1_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF /*| I2S_RCR4_FSE*/ | I2S_RCR4_FSP | I2S_RCR4_FSD; //PT8211 |
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I2S1_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15); |
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#endif |
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} |
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#elif defined(KINETISL) |
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/************************************************************************************** |
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* Teensy LC |
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***************************************************************************************/ |
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// added jan 2021, Frank Bösing |
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audio_block_t * AudioOutputPT8211::block_left = NULL; |
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audio_block_t * AudioOutputPT8211::block_right = NULL; |
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bool AudioOutputPT8211::update_responsibility = false; |
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#define NUM_SAMPLES (AUDIO_BLOCK_SAMPLES / 2) |
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DMAMEM static int16_t i2s_tx_buffer1[NUM_SAMPLES*2]; |
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DMAMEM static int16_t i2s_tx_buffer2[NUM_SAMPLES*2]; |
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DMAChannel AudioOutputPT8211::dma1(false); |
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DMAChannel AudioOutputPT8211::dma2(false); |
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void AudioOutputPT8211::begin(void) |
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{ |
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memset(i2s_tx_buffer1, 0, sizeof( i2s_tx_buffer1 ) ); |
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memset(i2s_tx_buffer2, 0, sizeof( i2s_tx_buffer2 ) ); |
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dma1.begin(true); // Allocate the DMA channel first |
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dma2.begin(true); |
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SIM_SCGC6 |= SIM_SCGC6_I2S;//Enable I2S periphal |
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// enable MCLK |
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I2S0_MCR = I2S_MCR_MICS(0) | I2S_MCR_MOE; |
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//MDR is not available on Teensy LC |
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// configure transmitter |
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I2S0_TMR = 0; |
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I2S0_TCR1 = I2S_TCR1_TFW(0); |
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I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1) | I2S_TCR2_BCD | I2S_TCR2_DIV(16); |
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I2S0_TCR3 = I2S_TCR3_TCE; |
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I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF /*| I2S_TCR4_FSE*/ | I2S_TCR4_FSP | I2S_TCR4_FSD; |
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I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15); |
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// configure pin mux |
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK //5.6MHz(44117HZ) |
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//CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
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//configure both DMA channels |
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dma1.sourceBuffer(i2s_tx_buffer1, sizeof(i2s_tx_buffer1)); |
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dma1.destination(*(int16_t *)&I2S0_TDR0); |
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dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma1.interruptAtCompletion(); |
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dma1.disableOnCompletion(); |
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dma1.attachInterrupt(isr1); |
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dma2.destination(*(int16_t *)&I2S0_TDR0); |
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dma2.sourceBuffer(i2s_tx_buffer2, sizeof(i2s_tx_buffer2)); |
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dma2.interruptAtCompletion(); |
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dma2.disableOnCompletion(); |
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dma2.attachInterrupt(isr2); |
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update_responsibility = update_setup(); |
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dma1.enable(); |
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I2S0_TCSR = I2S_TCSR_SR; |
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FWDE; |
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} |
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void AudioOutputPT8211::update(void) |
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{ |
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if (!block_left) block_left = receiveReadOnly(0);// input 0 = left channel |
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if (!block_right) block_right = receiveReadOnly(1);// input 1 = right channel |
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} |
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inline __attribute__((always_inline, hot)) |
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void interleave(const int16_t *dest,const audio_block_t *block_left, const audio_block_t *block_right, const size_t offset) |
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{ |
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uint32_t *p = (uint32_t*)dest; |
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uint32_t *end = p + NUM_SAMPLES; |
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if (block_left != nullptr && block_right != nullptr) { |
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int16_t *l = (int16_t*)&block_left->data[offset]; |
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int16_t *r = (int16_t*)&block_right->data[offset]; |
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do { |
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*p++ = (uint32_t)(*l++) << 16 | (uint32_t)(*r++); |
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*p++ = (uint32_t)(*l++) << 16 | (uint32_t)(*r++); |
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*p++ = (uint32_t)(*l++) << 16 | (uint32_t)(*r++); |
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*p++ = (uint32_t)(*l++) << 16 | (uint32_t)(*r++); |
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} while (p < end); |
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return; |
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} |
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if (block_left != nullptr) { |
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int16_t *l = (int16_t*)&block_left->data[offset]; |
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do { |
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*p++ = (uint32_t)(*l++) << 16; |
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*p++ = (uint32_t)(*l++) << 16; |
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*p++ = (uint32_t)(*l++) << 16; |
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*p++ = (uint32_t)(*l++) << 16; |
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} while (p < end); |
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return; |
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} |
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if (block_right != nullptr) { |
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int16_t *r = (int16_t*)&block_right->data[offset]; |
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do { |
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*p++ =(uint32_t)(*r++); |
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*p++ =(uint32_t)(*r++); |
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*p++ =(uint32_t)(*r++); |
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*p++ =(uint32_t)(*r++); |
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} while (p < end); |
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return; |
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} |
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do { |
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*p++ = 0; |
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*p++ = 0; |
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} while (p < end); |
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} |
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void AudioOutputPT8211::isr1(void) |
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{ //DMA Channel 1 Interrupt |
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//Start Channel 2: |
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dma2.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma2.enable(); |
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//Reset & Copy Data Channel 1 |
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dma1.clearInterrupt(); |
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dma1.sourceBuffer(i2s_tx_buffer1, sizeof(i2s_tx_buffer1)); |
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interleave(&i2s_tx_buffer1[0], AudioOutputPT8211::block_left, AudioOutputPT8211::block_right, 0); |
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} |
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void AudioOutputPT8211::isr2(void) |
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{ //DMA Channel 2 Interrupt |
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//Start Channel 1: |
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dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma1.enable(); |
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//Reset & Copy Data Channel 2 |
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dma2.clearInterrupt(); |
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dma2.sourceBuffer(i2s_tx_buffer2, sizeof(i2s_tx_buffer2)); |
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audio_block_t *block_left = AudioOutputPT8211::block_left; |
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audio_block_t *block_right = AudioOutputPT8211::block_right; |
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interleave(&i2s_tx_buffer2[0], block_left, block_right, NUM_SAMPLES); |
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if (block_left) AudioStream::release(block_left); |
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if (block_right) AudioStream::release(block_right); |
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AudioOutputPT8211::block_left = nullptr; |
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AudioOutputPT8211::block_right = nullptr; |
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if (AudioOutputPT8211::update_responsibility) AudioStream::update_all(); |
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} |
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#else |
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//#error Output PT8211: No code for this CPU |
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#endif |