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Fix TDM2 on Teensy 4.0

dds
PaulStoffregen 5 years ago
parent
commit
d65af6cb4a
3 changed files with 9 additions and 17 deletions
  1. +2
    -2
      input_tdm2.cpp
  2. +0
    -4
      output_tdm.cpp
  3. +7
    -11
      output_tdm2.cpp

+ 2
- 2
input_tdm2.cpp View File

* THE SOFTWARE. * THE SOFTWARE.
*/ */


#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
#if defined(__IMXRT1062__)
#include <Arduino.h> #include <Arduino.h>
#include "input_tdm2.h" #include "input_tdm2.h"
#include "output_tdm2.h" #include "output_tdm2.h"
// TODO: should we set & clear the I2S_RCSR_SR bit here? // TODO: should we set & clear the I2S_RCSR_SR bit here?
AudioOutputTDM2::config_tdm(); AudioOutputTDM2::config_tdm();


CORE_PIN33_CONFIG = 2; //2:RX_DATA0
CORE_PIN5_CONFIG = 2; //2:RX_DATA0
IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0; IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0;
dma.TCD->SADDR = &I2S2_RDR0; dma.TCD->SADDR = &I2S2_RDR0;
dma.TCD->SOFF = 0; dma.TCD->SOFF = 0;

+ 0
- 4
output_tdm.cpp View File

IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)) IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK


// if either transmitter or receiver is enabled, do nothing
if (I2S1_TCSR & I2S_TCSR_TE) return;
if (I2S1_RCSR & I2S_RCSR_RE) return;

// configure transmitter // configure transmitter
int rsync = 0; int rsync = 0;
int tsync = 1; int tsync = 1;

+ 7
- 11
output_tdm2.cpp View File

* THE SOFTWARE. * THE SOFTWARE.
*/ */


#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
#if defined(__IMXRT1062__)
#include <Arduino.h> #include <Arduino.h>
#include "output_tdm2.h" #include "output_tdm2.h"
#include "memcpy_audio.h" #include "memcpy_audio.h"


void AudioOutputTDM2::config_tdm(void) void AudioOutputTDM2::config_tdm(void)
{ {

CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON); CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);

// if either transmitter or receiver is enabled, do nothing
if (I2S2_TCSR & I2S_TCSR_TE) return;
if (I2S2_RCSR & I2S_RCSR_RE) return;
//PLL: //PLL:
int fs = AUDIO_SAMPLE_RATE_EXACT; //176.4 khZ int fs = AUDIO_SAMPLE_RATE_EXACT; //176.4 khZ
// PLL between 27*24 = 648MHz und 54*24=1296MHz // PLL between 27*24 = 648MHz und 54*24=1296MHz
IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)) IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0)); //Select MCLK | (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0)); //Select MCLK




// if either transmitter or receiver is enabled, do nothing
if (I2S2_TCSR & I2S_TCSR_TE) return;
if (I2S2_RCSR & I2S_RCSR_RE) return;

// configure transmitter // configure transmitter
int rsync = 1; int rsync = 1;
int tsync = 0; int tsync = 0;
| I2S_RCR4_FSE | I2S_RCR4_FSD; | I2S_RCR4_FSE | I2S_RCR4_FSD;
I2S2_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); I2S2_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);


CORE_PIN5_CONFIG = 2; //2:MCLK
CORE_PIN33_CONFIG = 2; //2:MCLK
CORE_PIN4_CONFIG = 2; //2:TX_BCLK CORE_PIN4_CONFIG = 2; //2:TX_BCLK
CORE_PIN3_CONFIG = 2; //2:TX_SYNC CORE_PIN3_CONFIG = 2; //2:TX_SYNC

} }


#endif
#endif

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