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SIM_SCGC2 |= SIM_SCGC2_DAC0; |
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SIM_SCGC2 |= SIM_SCGC2_DAC0; |
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DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2 |
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DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2 |
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// slowly ramp up to DC voltage, approx 1/4 second |
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// slowly ramp up to DC voltage, approx 1/4 second |
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for (int16_t i=0; i<2047; i++) { |
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*(int16_t *)&(DAC0_DAT0L) = i; |
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delayMicroseconds(262); |
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for (int16_t i=0; i<128; i++) { |
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analogWrite(A14, i); |
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delay(2); |
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} |
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} |
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// set the programmable delay block to trigger DMA requests |
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// set the programmable delay block to trigger DMA requests |
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SIM_SCGC6 |= SIM_SCGC6_PDB; |
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SIM_SCGC6 |= SIM_SCGC6_PDB; |
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PDB0_IDLY = 50; // TODO: is this ok? |
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PDB0_IDLY = 1; |
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PDB0_MOD = PDB_PERIOD; |
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PDB0_MOD = PDB_PERIOD; |
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PDB0_SC = PDB_CONFIG | PDB_SC_LDOK; |
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PDB0_SC = PDB_CONFIG | PDB_SC_LDOK; |
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PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG | PDB_SC_PDBIE | PDB_SC_DMAEN; |
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PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG | PDB_SC_PDBIE | PDB_SC_DMAEN; |
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//PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG | PDB_SC_PDBIE; |
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//NVIC_ENABLE_IRQ(IRQ_PDB); |
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#if 1 |
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SIM_SCGC7 |= SIM_SCGC7_DMA; |
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SIM_SCGC7 |= SIM_SCGC7_DMA; |
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
|
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DMA_CR = 0; |
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DMA_CR = 0; |
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DMA_TCD4_DLASTSGA = 0; |
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DMA_TCD4_DLASTSGA = 0; |
|
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DMA_TCD4_BITER_ELINKNO = sizeof(dac_buffer) / 2; |
|
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DMA_TCD4_BITER_ELINKNO = sizeof(dac_buffer) / 2; |
|
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DMA_TCD4_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
|
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DMA_TCD4_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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DMAMUX0_CHCFG4 = DMAMUX_DISABLE; |
|
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DMAMUX0_CHCFG4 = DMAMUX_DISABLE; |
|
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DMAMUX0_CHCFG4 = DMAMUX_SOURCE_PDB | DMAMUX_ENABLE; |
|
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DMAMUX0_CHCFG4 = DMAMUX_SOURCE_PDB | DMAMUX_ENABLE; |
|
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update_responsibility = update_setup(); |
|
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update_responsibility = update_setup(); |
|
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DMA_SERQ = 4; |
|
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DMA_SERQ = 4; |
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|
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NVIC_ENABLE_IRQ(IRQ_DMA_CH4); |
|
|
NVIC_ENABLE_IRQ(IRQ_DMA_CH4); |
|
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#endif |
|
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|
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} |
|
|
} |
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|
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//void pdb_isr(void) |
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//{ |
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|
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// static uint16_t val=0; |
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|
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// |
|
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|
|
// PDB0_SC = PDB_CONFIG | PDB_SC_PDBIE; |
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|
|
// if (val == 0) val = 4095; // testing only, full scale 22.05 kHz output |
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|
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// else val = 0; |
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|
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|
|
// DAC0_DAT0L = val & 255; |
|
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|
|
// DAC0_DATH = val >> 8; |
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|
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//} |
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|
|
void AudioOutputAnalog::update(void) |
|
|
void AudioOutputAnalog::update(void) |
|
|
{ |
|
|
{ |
|
|
audio_block_t *block; |
|
|
audio_block_t *block; |
|
|
|
|
|
|
|
|
// so we must fill the second half |
|
|
// so we must fill the second half |
|
|
dest = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES]; |
|
|
dest = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES]; |
|
|
end = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES*2]; |
|
|
end = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES*2]; |
|
|
if (AudioOutputAnalog::update_responsibility) AudioStream::update_all(); |
|
|
|
|
|
} else { |
|
|
} else { |
|
|
// DMA is transmitting the second half of the buffer |
|
|
// DMA is transmitting the second half of the buffer |
|
|
// so we must fill the first half |
|
|
// so we must fill the first half |
|
|
|
|
|
|
|
|
src = &block->data[offset]; |
|
|
src = &block->data[offset]; |
|
|
do { |
|
|
do { |
|
|
// TODO: this should probably dither |
|
|
// TODO: this should probably dither |
|
|
*dest++ = ((*src++) + 32767) >> 4; // TODO: optimize |
|
|
|
|
|
|
|
|
*dest++ = ((*src++) + 32767) >> 4; |
|
|
} while (dest < end); |
|
|
} while (dest < end); |
|
|
AudioStream::release(block); |
|
|
AudioStream::release(block); |
|
|
AudioOutputAnalog::block_left_1st = AudioOutputAnalog::block_left_2nd; |
|
|
AudioOutputAnalog::block_left_1st = AudioOutputAnalog::block_left_2nd; |
|
|
|
|
|
|
|
|
*dest++ = 2047; |
|
|
*dest++ = 2047; |
|
|
} while (dest < end); |
|
|
} while (dest < end); |
|
|
} |
|
|
} |
|
|
Serial.print("."); |
|
|
|
|
|
|
|
|
if (AudioOutputAnalog::update_responsibility) AudioStream::update_all(); |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
#else |
|
|
#else |