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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; |
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; |
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return; |
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return; |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
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arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); |
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#if defined(__IMXRT1052__) |
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#if defined(__IMXRT1052__) |
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CORE_PIN6_CONFIG = 3; //1:TX_DATA0 |
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CORE_PIN6_CONFIG = 3; //1:TX_DATA0 |
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#elif defined(__IMXRT1062__) |
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#elif defined(__IMXRT1062__) |
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arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); |
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
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#endif |
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#endif |
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