| I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; | ||||
| return; | return; | ||||
| #elif defined(__IMXRT1052__) || defined(__IMXRT1062__) | #elif defined(__IMXRT1052__) || defined(__IMXRT1062__) | ||||
| arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); | |||||
| #if defined(__IMXRT1052__) | #if defined(__IMXRT1052__) | ||||
| CORE_PIN6_CONFIG = 3; //1:TX_DATA0 | CORE_PIN6_CONFIG = 3; //1:TX_DATA0 | ||||
| #elif defined(__IMXRT1062__) | #elif defined(__IMXRT1062__) | ||||
| arm_dcache_flush_delete(i2s_tx_buffer, sizeof(i2s_tx_buffer)); | |||||
| CORE_PIN7_CONFIG = 3; //1:TX_DATA0 | CORE_PIN7_CONFIG = 3; //1:TX_DATA0 | ||||
| #endif | #endif | ||||