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/******************************************************************/ |
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/******************************************************************/ |
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/******************************************************************/ |
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// #define PDB_CONFIG (PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | PDB_SC_CONT) |
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// #define PDB_PERIOD 1087 // 48e6 / 44100 |
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#if defined(__MK20DX256__) && defined(DMA_TCD4_SADDR) |
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DMAMEM static uint16_t dac_buffer[AUDIO_BLOCK_SAMPLES*2]; |
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audio_block_t * AudioOutputAnalog::block_left_1st = NULL; |
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audio_block_t * AudioOutputAnalog::block_left_2nd = NULL; |
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bool AudioOutputAnalog::update_responsibility = false; |
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void AudioOutputAnalog::begin(void) |
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{ |
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SIM_SCGC2 |= SIM_SCGC2_DAC0; |
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DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2 |
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// slowly ramp up to DC voltage, approx 1/4 second |
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for (int16_t i=0; i<2047; i++) { |
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*(int16_t *)&(DAC0_DAT0L) = i; |
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delayMicroseconds(262); |
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} |
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// set the programmable delay block to trigger DMA requests |
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SIM_SCGC6 |= SIM_SCGC6_PDB; |
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PDB0_IDLY = 50; // TODO: is this ok? |
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PDB0_MOD = PDB_PERIOD; |
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PDB0_SC = PDB_CONFIG | PDB_SC_LDOK; |
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PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG | PDB_SC_PDBIE | PDB_SC_DMAEN; |
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//PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG | PDB_SC_PDBIE; |
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//NVIC_ENABLE_IRQ(IRQ_PDB); |
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#if 1 |
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SIM_SCGC7 |= SIM_SCGC7_DMA; |
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
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DMA_CR = 0; |
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DMA_TCD4_SADDR = dac_buffer; |
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DMA_TCD4_SOFF = 2; |
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DMA_TCD4_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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DMA_TCD4_NBYTES_MLNO = 2; |
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DMA_TCD4_SLAST = -sizeof(dac_buffer); |
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DMA_TCD4_DADDR = &DAC0_DAT0L; |
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DMA_TCD4_DOFF = 0; |
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DMA_TCD4_CITER_ELINKNO = sizeof(dac_buffer) / 2; |
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DMA_TCD4_DLASTSGA = 0; |
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DMA_TCD4_BITER_ELINKNO = sizeof(dac_buffer) / 2; |
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DMA_TCD4_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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DMAMUX0_CHCFG4 = DMAMUX_DISABLE; |
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DMAMUX0_CHCFG4 = DMAMUX_SOURCE_PDB | DMAMUX_ENABLE; |
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update_responsibility = update_setup(); |
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DMA_SERQ = 4; |
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NVIC_ENABLE_IRQ(IRQ_DMA_CH4); |
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#endif |
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} |
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//void pdb_isr(void) |
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//{ |
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// static uint16_t val=0; |
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// |
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// PDB0_SC = PDB_CONFIG | PDB_SC_PDBIE; |
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// if (val == 0) val = 4095; // testing only, full scale 22.05 kHz output |
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// else val = 0; |
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// DAC0_DAT0L = val & 255; |
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// DAC0_DATH = val >> 8; |
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//} |
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void AudioOutputAnalog::update(void) |
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{ |
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audio_block_t *block; |
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block = receiveReadOnly(0); // input 0 |
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if (block) { |
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__disable_irq(); |
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if (block_left_1st == NULL) { |
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block_left_1st = block; |
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__enable_irq(); |
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} else if (block_left_2nd == NULL) { |
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block_left_2nd = block; |
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__enable_irq(); |
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} else { |
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audio_block_t *tmp = block_left_1st; |
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block_left_1st = block_left_2nd; |
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block_left_2nd = block; |
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__enable_irq(); |
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release(tmp); |
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} |
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} |
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} |
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// TODO: the DAC has much higher bandwidth than the datasheet says |
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// can we output a 2X oversampled output, for easier filtering? |
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void dma_ch4_isr(void) |
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{ |
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const int16_t *src, *end; |
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int16_t *dest; |
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audio_block_t *block; |
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uint32_t saddr, offset; |
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saddr = (uint32_t)DMA_TCD4_SADDR; |
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DMA_CINT = 4; |
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if (saddr < (uint32_t)dac_buffer + sizeof(dac_buffer) / 2) { |
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// DMA is transmitting the first half of the buffer |
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// so we must fill the second half |
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dest = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES]; |
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end = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES*2]; |
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if (AudioOutputAnalog::update_responsibility) AudioStream::update_all(); |
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} else { |
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// DMA is transmitting the second half of the buffer |
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// so we must fill the first half |
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dest = (int16_t *)dac_buffer; |
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end = (int16_t *)&dac_buffer[AUDIO_BLOCK_SAMPLES]; |
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} |
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block = AudioOutputAnalog::block_left_1st; |
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if (block) { |
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src = &block->data[offset]; |
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do { |
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// TODO: this should probably dither |
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*dest++ = ((*src++) + 32767) >> 4; // TODO: optimize |
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} while (dest < end); |
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AudioStream::release(block); |
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AudioOutputAnalog::block_left_1st = AudioOutputAnalog::block_left_2nd; |
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AudioOutputAnalog::block_left_2nd = NULL; |
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} else { |
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do { |
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*dest++ = 2047; |
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} while (dest < end); |
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} |
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Serial.print("."); |
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} |
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#else |
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void AudioOutputAnalog::begin(void) |
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{ |
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} |
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void AudioOutputAnalog::update(void) |
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{ |
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audio_block_t *block; |
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block = receiveReadOnly(0); // input 0 |
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if (block) release(block); |
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} |
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#endif // defined(__MK20DX256__) && defined(DMA_TCD4_SADDR) |
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