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Add pinout documentation for I2S & TDM on Teensy 4.0

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PaulStoffregen 5 years ago
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1 changed files with 20 additions and 20 deletions
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<p>The I2S signals are used in "master" mode, where Teensy creates <p>The I2S signals are used in "master" mode, where Teensy creates
all 3 clock signals and controls all data timing.</p> all 3 clock signals and controls all data timing.</p>
<table class=doc align=center cellpadding=3> <table class=doc align=center cellpadding=3>
<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>13</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>23</td><td>LRCLK</td><td>Output</td></tr>
<tr class=top><th>T3.x<br>Pin</th><th>T4.0<br>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td align=center>21</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td align=center>23</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>13</td><td align=center>8</td><td>RX</td><td>Input</td></tr>
<tr class=odd><td align=center>23</td><td align=center>20</td><td>LRCLK</td><td>Output</td></tr>
</table> </table>
<p>Audio from <p>Audio from
master mode I2S may be used in the same project as ADC, DAC and master mode I2S may be used in the same project as ADC, DAC and
<a href="https://forum.pjrc.com/threads/42894">Invensense ICS-52000 microphones</a>. <a href="https://forum.pjrc.com/threads/42894">Invensense ICS-52000 microphones</a>.
</p> </p>
<table class=doc align=center cellpadding=3> <table class=doc align=center cellpadding=3>
<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td>BCLK</td><td>Output, 11.3 MHz</td></tr>
<tr class=odd><td align=center>11</td><td>MCLK</td><td>Output, 22.6 MHz</td></tr>
<tr class=odd><td align=center>13</td><td>RX</td><td>Input, 11.3 Mbit/sec</td></tr>
<tr class=odd><td align=center>23</td><td>FS</td><td>Output</td></tr>
<tr class=top><th>T3.x<br>Pin</th><th>T4.0<br>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td align=center>21</td><td>BCLK</td><td>Output, 11.3 MHz</td></tr>
<tr class=odd><td align=center>11</td><td align=center>23</td><td>MCLK</td><td>Output, 22.6 MHz</td></tr>
<tr class=odd><td align=center>13</td><td align=center>8</td><td>RX</td><td>Input, 11.3 Mbit/sec</td></tr>
<tr class=odd><td align=center>23</td><td align=center>21</td><td>FS</td><td>Output</td></tr>
</table> </table>
<p>Audio from <p>Audio from
master mode TDM may be used in the same project as ADC, DAC and master mode TDM may be used in the same project as ADC, DAC and
<p>The I2S signals are used in "master" mode, where Teensy creates <p>The I2S signals are used in "master" mode, where Teensy creates
all 3 clock signals and controls all data timing.</p> all 3 clock signals and controls all data timing.</p>
<table class=doc align=center cellpadding=3> <table class=doc align=center cellpadding=3>
<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>22</td><td>TX</td><td>Output</td></tr>
<tr class=odd><td align=center>23</td><td>LRCLK</td><td>Output</td></tr>
<tr class=top><th>T3.x<br>Pin</th><th>T4.0<br>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td align=center>21</td><td>BCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>11</td><td align=center>23</td><td>MCLK</td><td>Output</td></tr>
<tr class=odd><td align=center>22</td><td align=center>7</td><td>TX</td><td>Output</td></tr>
<tr class=odd><td align=center>23</td><td align=center>20</td><td>LRCLK</td><td>Output</td></tr>
</table> </table>
<p>Audio from <p>Audio from
master mode I2S may be used in the same project as ADC, DAC and master mode I2S may be used in the same project as ADC, DAC and
CS42448 Circuit Board</a>. CS42448 Circuit Board</a>.
</p> </p>
<table class=doc align=center cellpadding=3> <table class=doc align=center cellpadding=3>
<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td>BCLK</td><td>Output, 11.3 MHz</td></tr>
<tr class=odd><td align=center>11</td><td>MCLK</td><td>Output, 22.6 MHz</td></tr>
<tr class=odd><td align=center>22</td><td>TX</td><td>Output, 11.3 Mbit/sec</td></tr>
<tr class=odd><td align=center>23</td><td>WS</td><td>Output</td></tr>
<tr class=top><th>T3.x<br>Pin</th><th>T4.0<br>Pin</th><th>Signal</th><th>Direction</th></tr>
<tr class=odd><td align=center>9</td><td align=center>21</td><td>BCLK</td><td>Output, 11.3 MHz</td></tr>
<tr class=odd><td align=center>11</td><td align=center>23</td><td>MCLK</td><td>Output, 22.6 MHz</td></tr>
<tr class=odd><td align=center>22</td><td align=center>7</td><td>TX</td><td>Output, 11.3 Mbit/sec</td></tr>
<tr class=odd><td align=center>23</td><td align=center>20</td><td>WS</td><td>Output</td></tr>
</table> </table>
<p>Audio from <p>Audio from
master mode TDM may be used in the same project as ADC, DAC and master mode TDM may be used in the same project as ADC, DAC and

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