Browse Source

MQS: Play nice

keeps 352kHZ PWM, but reduces hardware-oversampling to 32x
dds
Frank Bösing 3 years ago
parent
commit
f2f51ea543
1 changed files with 4 additions and 5 deletions
  1. +4
    -5
      output_mqs.cpp

+ 4
- 5
output_mqs.cpp View File

//TODO: Check if frequencies are correct! //TODO: Check if frequencies are correct!


int fs = AUDIO_SAMPLE_RATE_EXACT; int fs = AUDIO_SAMPLE_RATE_EXACT;
int oversample = 64*8;
// PLL between 27*24 = 648MHz und 54*24=1296MHz // PLL between 27*24 = 648MHz und 54*24=1296MHz
int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4 int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
int n2 = 1 + (24000000 * 27) / (fs * oversample * n1);
int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);


double C = ((double)fs * oversample * n1 * n2) / 24000000;
double C = ((double)fs * 256 * n1 * n2) / 24000000;
int c0 = C; int c0 = C;
int c2 = 10000; int c2 = 10000;
int c1 = C * c2 - (c0 * c2); int c1 = C * c2 - (c0 * c2);
| (IOMUXC_GPR_GPR1_SAI3_MCLK_DIR | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(0)); //Select MCLK | (IOMUXC_GPR_GPR1_SAI3_MCLK_DIR | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(0)); //Select MCLK


IOMUXC_GPR_GPR2 = (IOMUXC_GPR_GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)) IOMUXC_GPR_GPR2 = (IOMUXC_GPR_GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK))
| IOMUXC_GPR_GPR2_MQS_EN | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE | IOMUXC_GPR_GPR2_MQS_CLK_DIV(0);
| IOMUXC_GPR_GPR2_MQS_EN /*| IOMUXC_GPR_GPR2_MQS_OVERSAMPLE */| IOMUXC_GPR_GPR2_MQS_CLK_DIV(0);


if (I2S3_TCSR & I2S_TCSR_TE) return; if (I2S3_TCSR & I2S_TCSR_TE) return;


// I2S3_TCSR = (1<<25); //Reset // I2S3_TCSR = (1<<25); //Reset
I2S3_TCR1 = I2S_TCR1_RFW(1); I2S3_TCR1 = I2S_TCR1_RFW(1);
I2S3_TCR2 = I2S_TCR2_SYNC(0) /*| I2S_TCR2_BCP*/ // sync=0; tx is async; I2S3_TCR2 = I2S_TCR2_SYNC(0) /*| I2S_TCR2_BCP*/ // sync=0; tx is async;
| (I2S_TCR2_BCD | I2S_TCR2_DIV((7)) | I2S_TCR2_MSEL(1));
| (I2S_TCR2_BCD | I2S_TCR2_DIV((3)) | I2S_TCR2_MSEL(1));
I2S3_TCR3 = I2S_TCR3_TCE; I2S3_TCR3 = I2S_TCR3_TCE;
I2S3_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((16-1)) | I2S_TCR4_MF | I2S_TCR4_FSD /*| I2S_TCR4_FSE*/ /* | I2S_TCR4_FSP */; I2S3_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((16-1)) | I2S_TCR4_MF | I2S_TCR4_FSD /*| I2S_TCR4_FSE*/ /* | I2S_TCR4_FSP */;
I2S3_TCR5 = I2S_TCR5_WNW((16-1)) | I2S_TCR5_W0W((16-1)) | I2S_TCR5_FBT((16-1)); I2S3_TCR5 = I2S_TCR5_WNW((16-1)) | I2S_TCR5_W0W((16-1)) | I2S_TCR5_FBT((16-1));

Loading…
Cancel
Save