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@@ -33,7 +33,7 @@ |
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// 7:0 REVID 0x00 - revision number for SGTL5000. |
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#define CHIP_DIG_POWER 0x0002 |
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// 6 ADC_POWERUP 1=Enable, 0=disable the ADC block, both digital & analog, |
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// 6 ADC_POWERUP 1=Enable, 0=disable the ADC block, both digital & analog, |
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// 5 DAC_POWERUP 1=Enable, 0=disable the DAC block, both analog and digital |
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// 4 DAP_POWERUP 1=Enable, 0=disable the DAP block |
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// 1 I2S_OUT_POWERUP 1=Enable, 0=disable the I2S data output |
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@@ -509,16 +509,36 @@ void AudioControlSGTL5000::setAddress(uint8_t level) |
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} |
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} |
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bool AudioControlSGTL5000::enable(void) |
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bool AudioControlSGTL5000::enable(void) { |
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#if defined(KINETISL) |
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return enable(16000000); // SGTL as Master with 16MHz MCLK from Teensy LC |
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#else |
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return enable(0); |
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#endif |
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} |
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bool AudioControlSGTL5000::enable(const unsigned extMCLK, const uint32_t pllFreq) |
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{ |
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muted = true; |
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Wire.begin(); |
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delay(5); |
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//Check if we are in Master Mode and if the Teensy had a reset: |
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unsigned int n = read(CHIP_I2S_CTRL); |
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if ( (extMCLK > 0) && (n == (0x0030 | (1<<7))) ) { |
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//Yes. Do not initialize. |
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muted = false; |
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semi_automated = true; |
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return true; |
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} |
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//Serial.print("chip ID = "); |
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//delay(5); |
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//unsigned int n = read(CHIP_ID); |
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//Serial.println(n, HEX); |
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muted = true; |
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int r = write(CHIP_ANA_POWER, 0x4060); // VDDD is externally driven with 1.8V |
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if (!r) return false; |
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write(CHIP_LINREG_CTRL, 0x006C); // VDDA & VDDIO both over 3.1V |
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@@ -526,23 +546,52 @@ bool AudioControlSGTL5000::enable(void) |
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write(CHIP_LINE_OUT_CTRL, 0x0F22); // LO_VAGCNTRL=1.65V, OUT_CURRENT=0.54mA |
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write(CHIP_SHORT_CTRL, 0x4446); // allow up to 125mA |
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write(CHIP_ANA_CTRL, 0x0137); // enable zero cross detectors |
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write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac |
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if (extMCLK > 0) { |
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//SGTL is I2S Master |
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//Datasheet Pg. 14: Using the PLL - Asynchronous SYS_MCLK input |
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if (extMCLK > 17000000) { |
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write(CHIP_CLK_TOP_CTRL, 1); |
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} else { |
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write(CHIP_CLK_TOP_CTRL, 0); |
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} |
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uint32_t int_divisor = (pllFreq / extMCLK) & 0x1f; |
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uint32_t frac_divisor = (uint32_t)((((float)pllFreq / extMCLK) - int_divisor) * 2048.0f) & 0x7ff; |
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write(CHIP_PLL_CTRL, (int_divisor << 11) | frac_divisor); |
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write(CHIP_ANA_POWER, 0x40FF | (1<<10) | (1<<8) ); // power up: lineout, hp, adc, dac, PLL_POWERUP, VCOAMP_POWERUP |
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} else { |
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//SGTL is I2S Slave |
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write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac |
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} |
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write(CHIP_DIG_POWER, 0x0073); // power up all digital stuff |
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delay(400); |
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write(CHIP_LINE_OUT_VOL, 0x1D1D); // default approx 1.3 volts peak-to-peak |
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write(CHIP_CLK_CTRL, 0x0004); // 44.1 kHz, 256*Fs |
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write(CHIP_I2S_CTRL, 0x0030); // SCLK=64*Fs, 16bit, I2S format |
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if (extMCLK > 0) { |
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//SGTL is I2S Master |
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write(CHIP_CLK_CTRL, 0x0004 | 0x03); // 44.1 kHz, 256*Fs, use PLL |
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write(CHIP_I2S_CTRL, 0x0030 | (1<<7)); // SCLK=64*Fs, 16bit, I2S format |
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} else { |
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//SGTL is I2S Slave |
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write(CHIP_CLK_CTRL, 0x0004); // 44.1 kHz, 256*Fs |
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write(CHIP_I2S_CTRL, 0x0030); // SCLK=64*Fs, 16bit, I2S format |
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} |
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// default signal routing is ok? |
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write(CHIP_SSS_CTRL, 0x0010); // ADC->I2S, I2S->DAC |
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write(CHIP_ADCDAC_CTRL, 0x0000); // disable dac mute |
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write(CHIP_DAC_VOL, 0x3C3C); // digital gain, 0dB |
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write(CHIP_ANA_HP_CTRL, 0x7F7F); // set volume (lowest level) |
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write(CHIP_ANA_CTRL, 0x0036); // enable zero cross detectors |
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//mute = false; |
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semi_automated = true; |
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return true; |
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} |
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unsigned int AudioControlSGTL5000::read(unsigned int reg) |
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{ |
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unsigned int val; |
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@@ -796,7 +845,7 @@ void AudioControlSGTL5000::eqFilter(uint8_t filterNum, int *filterParameters) |
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{ |
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// TODO: add the part that selects 7 PEQ filters. |
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if(semi_automated) automate(1,1,filterNum+1); |
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modify(DAP_FILTER_COEF_ACCESS,(uint16_t)filterNum,15); |
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modify(DAP_FILTER_COEF_ACCESS,(uint16_t)filterNum,15); |
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write(DAP_COEF_WR_B0_MSB,(*filterParameters>>4)&65535); |
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write(DAP_COEF_WR_B0_LSB,(*filterParameters++)&15); |
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write(DAP_COEF_WR_B1_MSB,(*filterParameters>>4)&65535); |
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@@ -816,23 +865,23 @@ void AudioControlSGTL5000::eqFilter(uint8_t filterNum, int *filterParameters) |
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0 - 0 dB |
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1 - 6.0 dB |
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2 - 12 dB |
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lbiResponse; Integrator Response |
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0 - 0 mS |
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1 - 25 mS |
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2 - 50 mS |
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3 - 100 mS |
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hardLimit |
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0 - Hard limit disabled. AVC Compressor/Expander enabled. |
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1 - Hard limit enabled. The signal is limited to the programmed threshold (signal saturates at the threshold) |
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threshold |
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floating point in range 0 to -96 dB |
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attack |
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floating point figure is dB/s rate at which gain is increased |
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decay |
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floating point figure is dB/s rate at which gain is reduced |
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*/ |
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@@ -935,12 +984,12 @@ void calcBiquad(uint8_t filtertype, float fC, float dB_Gain, float Q, uint32_t q |
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float A; |
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if(filtertype<FILTER_PARAEQ) A=pow(10,dB_Gain/20); else A=pow(10,dB_Gain/40); |
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float W0 = 2*3.14159265358979323846*fC/fS; |
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float W0 = 2*3.14159265358979323846*fC/fS; |
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float cosw=cosf(W0); |
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float sinw=sinf(W0); |
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//float alpha = sinw*sinh((log(2)/2)*BW*W0/sinw); |
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//float beta = sqrt(2*A); |
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float alpha = sinw / (2 * Q); |
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float alpha = sinw / (2 * Q); |
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float beta = sqrtf(A)/Q; |
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float b0,b1,b2,a0,a1,a2; |
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