- switch to single-DMA architecture (was having to manually reset address/byte counter each time anyway, so no real benefit of using two)
- add 2-block output pipeline (mirroring Teensy 3.x)
- (sneak in timer frequency increase - may want to revert this)
- actiate DMA on timer expiration (required to use DMA from timer)
- have to manually enable DMA after setup and after each call to isr
- implement isr
	- check if dma is done (not sure this is required, but thought I saw it call once when it wasn't, and in theory you get called on errors too)
	- reset source buffer to point to other staging memory
	- re-enable dma at completion
	- otherwise similar to teensy3.x version

https://forum.pjrc.com/threads/46443-Teensy-3-6-DAC-Output-Bug