/* Audio Library for Teensy 3.X * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com * * Development of this audio library was funded by PJRC.COM, LLC by sales of * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop * open source software by purchasing Teensy or other PJRC products. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice, development funding notice, and this permission * notice shall be included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include #include "output_i2s.h" #include "memcpy_audio.h" audio_block_t * AudioOutputI2S::block_left_1st = NULL; audio_block_t * AudioOutputI2S::block_right_1st = NULL; audio_block_t * AudioOutputI2S::block_left_2nd = NULL; audio_block_t * AudioOutputI2S::block_right_2nd = NULL; uint16_t AudioOutputI2S::block_left_offset = 0; uint16_t AudioOutputI2S::block_right_offset = 0; bool AudioOutputI2S::update_responsibility = false; DMAChannel AudioOutputI2S::dma(false); DMAMEM __attribute__((aligned(32))) static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; #if defined(__IMXRT1052__) || defined(__IMXRT1062__) #include "utility/imxrt_hw.h" void AudioOutputI2S::begin(void) { dma.begin(true); // Allocate the DMA channel first block_left_1st = NULL; block_right_1st = NULL; config_i2s(); #if defined(__IMXRT1052__) CORE_PIN6_CONFIG = 3; //1:TX_DATA0 #elif defined(__IMXRT1062__) CORE_PIN7_CONFIG = 3; //1:TX_DATA0 #endif dma.TCD->SADDR = i2s_tx_buffer; dma.TCD->SOFF = 2; dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); dma.TCD->NBYTES_MLNO = 2; dma.TCD->SLAST = -sizeof(i2s_tx_buffer); dma.TCD->DOFF = 0; dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->DLASTSGA = 0; dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); I2S1_RCSR |= I2S_RCSR_RE; I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; update_responsibility = update_setup(); dma.attachInterrupt(isr); dma.enable(); } #endif #if defined(KINETISK) void AudioOutputI2S::begin(void) { dma.begin(true); // Allocate the DMA channel first block_left_1st = NULL; block_right_1st = NULL; // TODO: should we set & clear the I2S_TCSR_SR bit here? config_i2s(); CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 dma.TCD->SADDR = i2s_tx_buffer; dma.TCD->SOFF = 2; dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); dma.TCD->NBYTES_MLNO = 2; dma.TCD->SLAST = -sizeof(i2s_tx_buffer); dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2); dma.TCD->DOFF = 0; dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->DLASTSGA = 0; dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); update_responsibility = update_setup(); dma.enable(); I2S0_TCSR = I2S_TCSR_SR; I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; dma.attachInterrupt(isr); } #endif void AudioOutputI2S::isr(void) { #if defined(KINETISK) || defined(__IMXRT1052__) || defined(__IMXRT1062__) int16_t *dest; audio_block_t *blockL, *blockR; uint32_t saddr, offsetL, offsetR; saddr = (uint32_t)(dma.TCD->SADDR); dma.clearInterrupt(); if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { // DMA is transmitting the first half of the buffer // so we must fill the second half dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; if (AudioOutputI2S::update_responsibility) AudioStream::update_all(); } else { // DMA is transmitting the second half of the buffer // so we must fill the first half dest = (int16_t *)i2s_tx_buffer; } blockL = AudioOutputI2S::block_left_1st; blockR = AudioOutputI2S::block_right_1st; offsetL = AudioOutputI2S::block_left_offset; offsetR = AudioOutputI2S::block_right_offset; if (blockL && blockR) { memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR); offsetL += AUDIO_BLOCK_SAMPLES / 2; offsetR += AUDIO_BLOCK_SAMPLES / 2; } else if (blockL) { memcpy_tointerleaveL(dest, blockL->data + offsetL); offsetL += AUDIO_BLOCK_SAMPLES / 2; } else if (blockR) { memcpy_tointerleaveR(dest, blockR->data + offsetR); offsetR += AUDIO_BLOCK_SAMPLES / 2; } else { memset(dest,0,AUDIO_BLOCK_SAMPLES * 2); } #if IMXRT_CACHE_ENABLED >= 2 arm_dcache_flush_delete(dest, sizeof(i2s_tx_buffer) / 2 ); #endif if (offsetL < AUDIO_BLOCK_SAMPLES) { AudioOutputI2S::block_left_offset = offsetL; } else { AudioOutputI2S::block_left_offset = 0; AudioStream::release(blockL); AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd; AudioOutputI2S::block_left_2nd = NULL; } if (offsetR < AUDIO_BLOCK_SAMPLES) { AudioOutputI2S::block_right_offset = offsetR; } else { AudioOutputI2S::block_right_offset = 0; AudioStream::release(blockR); AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd; AudioOutputI2S::block_right_2nd = NULL; } #else const int16_t *src, *end; int16_t *dest; audio_block_t *block; uint32_t saddr, offset; saddr = (uint32_t)(dma.CFG->SAR); dma.clearInterrupt(); if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { // DMA is transmitting the first half of the buffer // so we must fill the second half dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; if (AudioOutputI2S::update_responsibility) AudioStream::update_all(); } else { // DMA is transmitting the second half of the buffer // so we must fill the first half dest = (int16_t *)i2s_tx_buffer; end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; } block = AudioOutputI2S::block_left_1st; if (block) { offset = AudioOutputI2S::block_left_offset; src = &block->data[offset]; do { *dest = *src++; dest += 2; } while (dest < end); offset += AUDIO_BLOCK_SAMPLES/2; if (offset < AUDIO_BLOCK_SAMPLES) { AudioOutputI2S::block_left_offset = offset; } else { AudioOutputI2S::block_left_offset = 0; AudioStream::release(block); AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd; AudioOutputI2S::block_left_2nd = NULL; } } else { do { *dest = 0; dest += 2; } while (dest < end); } dest -= AUDIO_BLOCK_SAMPLES - 1; block = AudioOutputI2S::block_right_1st; if (block) { offset = AudioOutputI2S::block_right_offset; src = &block->data[offset]; do { *dest = *src++; dest += 2; } while (dest < end); offset += AUDIO_BLOCK_SAMPLES/2; if (offset < AUDIO_BLOCK_SAMPLES) { AudioOutputI2S::block_right_offset = offset; } else { AudioOutputI2S::block_right_offset = 0; AudioStream::release(block); AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd; AudioOutputI2S::block_right_2nd = NULL; } } else { do { *dest = 0; dest += 2; } while (dest < end); } #endif } void AudioOutputI2S::update(void) { // null audio device: discard all incoming data //if (!active) return; //audio_block_t *block = receiveReadOnly(); //if (block) release(block); audio_block_t *block; block = receiveReadOnly(0); // input 0 = left channel if (block) { __disable_irq(); if (block_left_1st == NULL) { block_left_1st = block; block_left_offset = 0; __enable_irq(); } else if (block_left_2nd == NULL) { block_left_2nd = block; __enable_irq(); } else { audio_block_t *tmp = block_left_1st; block_left_1st = block_left_2nd; block_left_2nd = block; block_left_offset = 0; __enable_irq(); release(tmp); } } block = receiveReadOnly(1); // input 1 = right channel if (block) { __disable_irq(); if (block_right_1st == NULL) { block_right_1st = block; block_right_offset = 0; __enable_irq(); } else if (block_right_2nd == NULL) { block_right_2nd = block; __enable_irq(); } else { audio_block_t *tmp = block_right_1st; block_right_1st = block_right_2nd; block_right_2nd = block; block_right_offset = 0; __enable_irq(); release(tmp); } } } #if defined(KINETISK) || defined(KINETISL) // MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate // #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000 // PLL is at 96 MHz in these modes #define MCLK_MULT 2 #define MCLK_DIV 17 #elif F_CPU == 72000000 #define MCLK_MULT 8 #define MCLK_DIV 51 #elif F_CPU == 120000000 #define MCLK_MULT 8 #define MCLK_DIV 85 #elif F_CPU == 144000000 #define MCLK_MULT 4 #define MCLK_DIV 51 #elif F_CPU == 168000000 #define MCLK_MULT 8 #define MCLK_DIV 119 #elif F_CPU == 180000000 #define MCLK_MULT 16 #define MCLK_DIV 255 #define MCLK_SRC 0 #elif F_CPU == 192000000 #define MCLK_MULT 1 #define MCLK_DIV 17 #elif F_CPU == 216000000 #define MCLK_MULT 8 #define MCLK_DIV 153 #define MCLK_SRC 0 #elif F_CPU == 240000000 #define MCLK_MULT 4 #define MCLK_DIV 85 #elif F_CPU == 16000000 #define MCLK_MULT 12 #define MCLK_DIV 17 #else #error "This CPU Clock Speed is not supported by the Audio library"; #endif #ifndef MCLK_SRC #if F_CPU >= 20000000 #define MCLK_SRC 3 // the PLL #else #define MCLK_SRC 0 // system clock #endif #endif #endif void AudioOutputI2S::config_i2s(void) { #if defined(KINETISK) || defined(KINETISL) SIM_SCGC6 |= SIM_SCGC6_I2S; SIM_SCGC7 |= SIM_SCGC7_DMA; SIM_SCGC6 |= SIM_SCGC6_DMAMUX; // if either transmitter or receiver is enabled, do nothing if (I2S0_TCSR & I2S_TCSR_TE) return; if (I2S0_RCSR & I2S_RCSR_RE) return; // enable MCLK output I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; while (I2S0_MCR & I2S_MCR_DUF) ; I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1)); // configure transmitter I2S0_TMR = 0; I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1) | I2S_TCR2_BCD | I2S_TCR2_DIV(1); I2S0_TCR3 = I2S_TCR3_TCE; I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); // configure receiver (sync'd to transmitter clocks) I2S0_RMR = 0; I2S0_RCR1 = I2S_RCR1_RFW(1); I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1) | I2S_RCR2_BCD | I2S_RCR2_DIV(1); I2S0_RCR3 = I2S_RCR3_RCE; I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); // configure pin mux for 3 clock signals CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK #elif ( defined(__IMXRT1052__) || defined(__IMXRT1062__) ) CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); //PLL: int fs = AUDIO_SAMPLE_RATE_EXACT; // PLL between 27*24 = 648MHz und 54*24=1296MHz int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4 int n2 = 1 + (24000000 * 27) / (fs * 256 * n1); double C = ((double)fs * 256 * n1 * n2) / 24000000; int c0 = C; int c2 = 10000; int c1 = C * c2 - (c0 * c2); set_audioClock(c0, c1, c2); // clear SAI1_CLK register locations CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK)) | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4 CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK)) | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07 | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)) | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK // if either transmitter or receiver is enabled, do nothing if (I2S1_TCSR & I2S_TCSR_TE) return; if (I2S1_RCSR & I2S_RCSR_RE) return; CORE_PIN23_CONFIG = 3; //1:MCLK CORE_PIN21_CONFIG = 3; //1:RX_BCLK CORE_PIN20_CONFIG = 3; //1:RX_SYNC // CORE_PIN6_CONFIG = 3; //1:TX_DATA0 // CORE_PIN7_CONFIG = 3; //1:RX_DATA0 int rsync = 0; int tsync = 1; I2S1_TMR = 0; //I2S1_TCSR = (1<<25); //Reset I2S1_TCR1 = I2S_TCR1_RFW(1); I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async; | (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1)); I2S1_TCR3 = I2S_TCR3_TCE; I2S1_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP; I2S1_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1)); I2S1_RMR = 0; //I2S1_RCSR = (1<<25); //Reset I2S1_RCR1 = I2S_RCR1_RFW(1); I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP // sync=0; rx is async; | (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1)); I2S1_RCR3 = I2S_RCR3_RCE; I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; I2S1_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1)); #endif } /******************************************************************/ void AudioOutputI2Sslave::begin(void) { dma.begin(true); // Allocate the DMA channel first //pinMode(2, OUTPUT); block_left_1st = NULL; block_right_1st = NULL; AudioOutputI2Sslave::config_i2s(); #if defined(KINETISK) CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 dma.TCD->SADDR = i2s_tx_buffer; dma.TCD->SOFF = 2; dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); dma.TCD->NBYTES_MLNO = 2; dma.TCD->SLAST = -sizeof(i2s_tx_buffer); dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2); dma.TCD->DOFF = 0; dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->DLASTSGA = 0; dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); I2S0_TCSR = I2S_TCSR_SR; I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; #elif 0 && ( defined(__IMXRT1052__) || defined(__IMXRT1062__) ) #if defined(SAI1) CORE_PIN6_CONFIG = 3; //1:TX_DATA0 //CORE_PIN7_CONFIG = 3; //1:RX_DATA0 #elif defined(SAI2) CORE_PIN2_CONFIG = 2; //2:TX_DATA0 //CORE_PIN33_CONFIG = 2; //2:RX_DATA0 #endif dma.TCD->SADDR = i2s_tx_buffer; dma.TCD->SOFF = 2; dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); dma.TCD->NBYTES_MLNO = 2; dma.TCD->SLAST = -sizeof(i2s_tx_buffer); dma.TCD->DADDR = (void *)&i2s->TX.DR16[1]; dma.TCD->DOFF = 0; dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.TCD->DLASTSGA = 0; dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX); #endif update_responsibility = update_setup(); dma.enable(); dma.attachInterrupt(isr); } void AudioOutputI2Sslave::config_i2s(void) { SIM_SCGC6 |= SIM_SCGC6_I2S; SIM_SCGC7 |= SIM_SCGC7_DMA; SIM_SCGC6 |= SIM_SCGC6_DMAMUX; // if either transmitter or receiver is enabled, do nothing if (I2S0_TCSR & I2S_TCSR_TE) return; if (I2S0_RCSR & I2S_RCSR_RE) return; // Select input clock 0 // Configure to input the bit-clock from pin, bypasses the MCLK divider I2S0_MCR = I2S_MCR_MICS(0); I2S0_MDR = 0; // configure transmitter I2S0_TMR = 0; I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP; I2S0_TCR3 = I2S_TCR3_TCE; I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP; I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); // configure receiver (sync'd to transmitter clocks) I2S0_RMR = 0; I2S0_RCR1 = I2S_RCR1_RFW(1); I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP; I2S0_RCR3 = I2S_RCR3_RCE; I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); // configure pin mux for 3 clock signals CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK #elif 0 && (defined(__IMXRT1052__) || defined(__IMXRT1062__) ) #if defined(SAI1) i2s = ((I2S_STRUCT *)0x40384000); // if either transmitter or receiver is enabled, do nothing if (i2s->TX.CSR & I2S_TCSR_TE) return; if (i2s->RX.CSR & I2S_RCSR_RE) return; CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); /* CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK)) | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4 CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK)) | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07 | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f */ //TODO: IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | ((uint32_t)(1<<20)) )) | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK CORE_PIN23_CONFIG = 3; //1:MCLK CORE_PIN21_CONFIG = 3; //1:RX_BCLK CORE_PIN20_CONFIG = 3; //1:RX_SYNC int rsync = 0; int tsync = 1; #elif defined(SAI2) i2s = ((I2S_STRUCT *)0x40388000); if (i2s->TX.CSR & I2S_TCSR_TE) return; if (i2s->RX.CSR & I2S_RCSR_RE) return; CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON); /* CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK)) | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4, CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK)) | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) | CCM_CS2CDR_SAI2_CLK_PODF(n2-1); */ //TODO: IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | ((uint32_t)(1<<19)) )) /*| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR*/ | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0); //Select MCLK CORE_PIN5_CONFIG = 2; //2:MCLK CORE_PIN4_CONFIG = 2; //2:TX_BCLK CORE_PIN3_CONFIG = 2; //2:TX_SYNC int rsync = 1; int tsync = 0; #endif // configure transmitter i2s->TX.MR = 0; i2s->TX.CR1 = I2S_TCR1_RFW(1); // watermark at half fifo size i2s->TX.CR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP; i2s->TX.CR3 = I2S_TCR3_TCE; i2s->TX.CR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP; i2s->TX.CR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); // configure receiver i2s->RX.MR = 0; i2s->RX.CR1 = I2S_RCR1_RFW(1); i2s->RX.CR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP; i2s->RX.CR3 = I2S_RCR3_RCE; i2s->RX.CR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; i2s->RX.CR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); #endif }