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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include <Arduino.h>
  27. #include "output_i2s.h"
  28. #include "memcpy_audio.h"
  29. audio_block_t * AudioOutputI2S::block_left_1st = NULL;
  30. audio_block_t * AudioOutputI2S::block_right_1st = NULL;
  31. audio_block_t * AudioOutputI2S::block_left_2nd = NULL;
  32. audio_block_t * AudioOutputI2S::block_right_2nd = NULL;
  33. uint16_t AudioOutputI2S::block_left_offset = 0;
  34. uint16_t AudioOutputI2S::block_right_offset = 0;
  35. bool AudioOutputI2S::update_responsibility = false;
  36. static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  37. DMAChannel AudioOutputI2S::dma(false);
  38. #if defined(__IMXRT1052__) || defined(__IMXRT1062__)
  39. #include "utility/imxrt_hw.h"
  40. void AudioOutputI2S::begin(void)
  41. {
  42. dma.begin(true); // Allocate the DMA channel first
  43. block_left_1st = NULL;
  44. block_right_1st = NULL;
  45. config_i2s();
  46. CORE_PIN6_CONFIG = 3; //1:TX_DATA0
  47. dma.TCD->SADDR = i2s_tx_buffer;
  48. dma.TCD->SOFF = 2;
  49. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  50. dma.TCD->NBYTES_MLNO = 2;
  51. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  52. dma.TCD->DOFF = 0;
  53. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  54. dma.TCD->DLASTSGA = 0;
  55. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  56. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  57. dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2);
  58. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
  59. I2S1_RCSR |= I2S_RCSR_RE;
  60. I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  61. update_responsibility = update_setup();
  62. dma.attachInterrupt(isr);
  63. dma.enable();
  64. }
  65. #endif
  66. #if defined(KINETISK)
  67. void AudioOutputI2S::begin(void)
  68. {
  69. dma.begin(true); // Allocate the DMA channel first
  70. block_left_1st = NULL;
  71. block_right_1st = NULL;
  72. // TODO: should we set & clear the I2S_TCSR_SR bit here?
  73. config_i2s();
  74. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  75. dma.TCD->SADDR = i2s_tx_buffer;
  76. dma.TCD->SOFF = 2;
  77. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  78. dma.TCD->NBYTES_MLNO = 2;
  79. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  80. dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
  81. dma.TCD->DOFF = 0;
  82. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  83. dma.TCD->DLASTSGA = 0;
  84. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  85. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  86. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  87. update_responsibility = update_setup();
  88. dma.enable();
  89. I2S0_TCSR = I2S_TCSR_SR;
  90. I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  91. dma.attachInterrupt(isr);
  92. }
  93. #endif
  94. void AudioOutputI2S::isr(void)
  95. {
  96. #if defined(KINETISK) || defined(__IMXRT1052__) || defined(__IMXRT1062__)
  97. int16_t *dest;
  98. audio_block_t *blockL, *blockR;
  99. uint32_t saddr, offsetL, offsetR;
  100. saddr = (uint32_t)(dma.TCD->SADDR);
  101. dma.clearInterrupt();
  102. if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
  103. // DMA is transmitting the first half of the buffer
  104. // so we must fill the second half
  105. dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  106. if (AudioOutputI2S::update_responsibility) AudioStream::update_all();
  107. } else {
  108. // DMA is transmitting the second half of the buffer
  109. // so we must fill the first half
  110. dest = (int16_t *)i2s_tx_buffer;
  111. }
  112. blockL = AudioOutputI2S::block_left_1st;
  113. blockR = AudioOutputI2S::block_right_1st;
  114. offsetL = AudioOutputI2S::block_left_offset;
  115. offsetR = AudioOutputI2S::block_right_offset;
  116. if (blockL && blockR) {
  117. memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR);
  118. offsetL += AUDIO_BLOCK_SAMPLES / 2;
  119. offsetR += AUDIO_BLOCK_SAMPLES / 2;
  120. } else if (blockL) {
  121. memcpy_tointerleaveL(dest, blockL->data + offsetL);
  122. offsetL += AUDIO_BLOCK_SAMPLES / 2;
  123. } else if (blockR) {
  124. memcpy_tointerleaveR(dest, blockR->data + offsetR);
  125. offsetR += AUDIO_BLOCK_SAMPLES / 2;
  126. } else {
  127. memset(dest,0,AUDIO_BLOCK_SAMPLES * 2);
  128. return;
  129. }
  130. if (offsetL < AUDIO_BLOCK_SAMPLES) {
  131. AudioOutputI2S::block_left_offset = offsetL;
  132. } else {
  133. AudioOutputI2S::block_left_offset = 0;
  134. AudioStream::release(blockL);
  135. AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd;
  136. AudioOutputI2S::block_left_2nd = NULL;
  137. }
  138. if (offsetR < AUDIO_BLOCK_SAMPLES) {
  139. AudioOutputI2S::block_right_offset = offsetR;
  140. } else {
  141. AudioOutputI2S::block_right_offset = 0;
  142. AudioStream::release(blockR);
  143. AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd;
  144. AudioOutputI2S::block_right_2nd = NULL;
  145. }
  146. #else
  147. const int16_t *src, *end;
  148. int16_t *dest;
  149. audio_block_t *block;
  150. uint32_t saddr, offset;
  151. saddr = (uint32_t)(dma.CFG->SAR);
  152. dma.clearInterrupt();
  153. if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
  154. // DMA is transmitting the first half of the buffer
  155. // so we must fill the second half
  156. dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  157. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  158. if (AudioOutputI2S::update_responsibility) AudioStream::update_all();
  159. } else {
  160. // DMA is transmitting the second half of the buffer
  161. // so we must fill the first half
  162. dest = (int16_t *)i2s_tx_buffer;
  163. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  164. }
  165. block = AudioOutputI2S::block_left_1st;
  166. if (block) {
  167. offset = AudioOutputI2S::block_left_offset;
  168. src = &block->data[offset];
  169. do {
  170. *dest = *src++;
  171. dest += 2;
  172. } while (dest < end);
  173. offset += AUDIO_BLOCK_SAMPLES/2;
  174. if (offset < AUDIO_BLOCK_SAMPLES) {
  175. AudioOutputI2S::block_left_offset = offset;
  176. } else {
  177. AudioOutputI2S::block_left_offset = 0;
  178. AudioStream::release(block);
  179. AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd;
  180. AudioOutputI2S::block_left_2nd = NULL;
  181. }
  182. } else {
  183. do {
  184. *dest = 0;
  185. dest += 2;
  186. } while (dest < end);
  187. }
  188. dest -= AUDIO_BLOCK_SAMPLES - 1;
  189. block = AudioOutputI2S::block_right_1st;
  190. if (block) {
  191. offset = AudioOutputI2S::block_right_offset;
  192. src = &block->data[offset];
  193. do {
  194. *dest = *src++;
  195. dest += 2;
  196. } while (dest < end);
  197. offset += AUDIO_BLOCK_SAMPLES/2;
  198. if (offset < AUDIO_BLOCK_SAMPLES) {
  199. AudioOutputI2S::block_right_offset = offset;
  200. } else {
  201. AudioOutputI2S::block_right_offset = 0;
  202. AudioStream::release(block);
  203. AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd;
  204. AudioOutputI2S::block_right_2nd = NULL;
  205. }
  206. } else {
  207. do {
  208. *dest = 0;
  209. dest += 2;
  210. } while (dest < end);
  211. }
  212. #endif
  213. }
  214. void AudioOutputI2S::update(void)
  215. {
  216. // null audio device: discard all incoming data
  217. //if (!active) return;
  218. //audio_block_t *block = receiveReadOnly();
  219. //if (block) release(block);
  220. audio_block_t *block;
  221. block = receiveReadOnly(0); // input 0 = left channel
  222. if (block) {
  223. __disable_irq();
  224. if (block_left_1st == NULL) {
  225. block_left_1st = block;
  226. block_left_offset = 0;
  227. __enable_irq();
  228. } else if (block_left_2nd == NULL) {
  229. block_left_2nd = block;
  230. __enable_irq();
  231. } else {
  232. audio_block_t *tmp = block_left_1st;
  233. block_left_1st = block_left_2nd;
  234. block_left_2nd = block;
  235. block_left_offset = 0;
  236. __enable_irq();
  237. release(tmp);
  238. }
  239. }
  240. block = receiveReadOnly(1); // input 1 = right channel
  241. if (block) {
  242. __disable_irq();
  243. if (block_right_1st == NULL) {
  244. block_right_1st = block;
  245. block_right_offset = 0;
  246. __enable_irq();
  247. } else if (block_right_2nd == NULL) {
  248. block_right_2nd = block;
  249. __enable_irq();
  250. } else {
  251. audio_block_t *tmp = block_right_1st;
  252. block_right_1st = block_right_2nd;
  253. block_right_2nd = block;
  254. block_right_offset = 0;
  255. __enable_irq();
  256. release(tmp);
  257. }
  258. }
  259. }
  260. #if defined(KINETISK) || defined(KINETISL)
  261. // MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
  262. //
  263. #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
  264. // PLL is at 96 MHz in these modes
  265. #define MCLK_MULT 2
  266. #define MCLK_DIV 17
  267. #elif F_CPU == 72000000
  268. #define MCLK_MULT 8
  269. #define MCLK_DIV 51
  270. #elif F_CPU == 120000000
  271. #define MCLK_MULT 8
  272. #define MCLK_DIV 85
  273. #elif F_CPU == 144000000
  274. #define MCLK_MULT 4
  275. #define MCLK_DIV 51
  276. #elif F_CPU == 168000000
  277. #define MCLK_MULT 8
  278. #define MCLK_DIV 119
  279. #elif F_CPU == 180000000
  280. #define MCLK_MULT 16
  281. #define MCLK_DIV 255
  282. #define MCLK_SRC 0
  283. #elif F_CPU == 192000000
  284. #define MCLK_MULT 1
  285. #define MCLK_DIV 17
  286. #elif F_CPU == 216000000
  287. #define MCLK_MULT 8
  288. #define MCLK_DIV 153
  289. #define MCLK_SRC 0
  290. #elif F_CPU == 240000000
  291. #define MCLK_MULT 4
  292. #define MCLK_DIV 85
  293. #elif F_CPU == 16000000
  294. #define MCLK_MULT 12
  295. #define MCLK_DIV 17
  296. #else
  297. #error "This CPU Clock Speed is not supported by the Audio library";
  298. #endif
  299. #ifndef MCLK_SRC
  300. #if F_CPU >= 20000000
  301. #define MCLK_SRC 3 // the PLL
  302. #else
  303. #define MCLK_SRC 0 // system clock
  304. #endif
  305. #endif
  306. #endif
  307. void AudioOutputI2S::config_i2s(void)
  308. {
  309. #if defined(KINETISK) || defined(KINETISL)
  310. SIM_SCGC6 |= SIM_SCGC6_I2S;
  311. SIM_SCGC7 |= SIM_SCGC7_DMA;
  312. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  313. // if either transmitter or receiver is enabled, do nothing
  314. if (I2S0_TCSR & I2S_TCSR_TE) return;
  315. if (I2S0_RCSR & I2S_RCSR_RE) return;
  316. // enable MCLK output
  317. I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
  318. while (I2S0_MCR & I2S_MCR_DUF) ;
  319. I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
  320. // configure transmitter
  321. I2S0_TMR = 0;
  322. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  323. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  324. | I2S_TCR2_BCD | I2S_TCR2_DIV(1);
  325. I2S0_TCR3 = I2S_TCR3_TCE;
  326. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
  327. | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
  328. I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
  329. // configure receiver (sync'd to transmitter clocks)
  330. I2S0_RMR = 0;
  331. I2S0_RCR1 = I2S_RCR1_RFW(1);
  332. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  333. | I2S_RCR2_BCD | I2S_RCR2_DIV(1);
  334. I2S0_RCR3 = I2S_RCR3_RCE;
  335. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
  336. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  337. I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
  338. // configure pin mux for 3 clock signals
  339. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  340. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  341. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  342. #elif ( defined(__IMXRT1052__) || defined(__IMXRT1062__) )
  343. CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
  344. //PLL:
  345. int fs = AUDIO_SAMPLE_RATE_EXACT;
  346. // PLL between 27*24 = 648MHz und 54*24=1296MHz
  347. int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
  348. int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
  349. double C = ((double)fs * 256 * n1 * n2) / 24000000;
  350. int c0 = C;
  351. int c2 = 10000;
  352. int c1 = C * c2 - (c0 * c2);
  353. set_audioClock(c0, c1, c2);
  354. // clear SAI1_CLK register locations
  355. CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
  356. | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
  357. CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
  358. | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
  359. | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
  360. IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
  361. | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK
  362. // if either transmitter or receiver is enabled, do nothing
  363. if (I2S1_TCSR & I2S_TCSR_TE) return;
  364. if (I2S1_RCSR & I2S_RCSR_RE) return;
  365. CORE_PIN23_CONFIG = 3; //1:MCLK
  366. CORE_PIN21_CONFIG = 3; //1:RX_BCLK
  367. CORE_PIN20_CONFIG = 3; //1:RX_SYNC
  368. // CORE_PIN6_CONFIG = 3; //1:TX_DATA0
  369. // CORE_PIN7_CONFIG = 3; //1:RX_DATA0
  370. int rsync = 0;
  371. int tsync = 1;
  372. I2S1_TMR = 0;
  373. //I2S1_TCSR = (1<<25); //Reset
  374. I2S1_TCR1 = I2S_TCR1_RFW(1);
  375. I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async;
  376. | (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1));
  377. I2S1_TCR3 = I2S_TCR3_TCE;
  378. I2S1_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
  379. I2S1_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1));
  380. I2S1_RMR = 0;
  381. //I2S1_RCSR = (1<<25); //Reset
  382. I2S1_RCR1 = I2S_RCR1_RFW(1);
  383. I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP // sync=0; rx is async;
  384. | (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1));
  385. I2S1_RCR3 = I2S_RCR3_RCE;
  386. I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  387. I2S1_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1));
  388. #endif
  389. }
  390. /******************************************************************/
  391. void AudioOutputI2Sslave::begin(void)
  392. {
  393. dma.begin(true); // Allocate the DMA channel first
  394. //pinMode(2, OUTPUT);
  395. block_left_1st = NULL;
  396. block_right_1st = NULL;
  397. AudioOutputI2Sslave::config_i2s();
  398. #if defined(KINETISK)
  399. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  400. dma.TCD->SADDR = i2s_tx_buffer;
  401. dma.TCD->SOFF = 2;
  402. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  403. dma.TCD->NBYTES_MLNO = 2;
  404. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  405. dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
  406. dma.TCD->DOFF = 0;
  407. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  408. dma.TCD->DLASTSGA = 0;
  409. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  410. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  411. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  412. I2S0_TCSR = I2S_TCSR_SR;
  413. I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  414. #elif 0 && ( defined(__IMXRT1052__) || defined(__IMXRT1062__) )
  415. #if defined(SAI1)
  416. CORE_PIN6_CONFIG = 3; //1:TX_DATA0
  417. //CORE_PIN7_CONFIG = 3; //1:RX_DATA0
  418. #elif defined(SAI2)
  419. CORE_PIN2_CONFIG = 2; //2:TX_DATA0
  420. //CORE_PIN33_CONFIG = 2; //2:RX_DATA0
  421. #endif
  422. dma.TCD->SADDR = i2s_tx_buffer;
  423. dma.TCD->SOFF = 2;
  424. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  425. dma.TCD->NBYTES_MLNO = 2;
  426. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  427. dma.TCD->DADDR = (void *)&i2s->TX.DR16[1];
  428. dma.TCD->DOFF = 0;
  429. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  430. dma.TCD->DLASTSGA = 0;
  431. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  432. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
  433. #endif
  434. update_responsibility = update_setup();
  435. dma.enable();
  436. dma.attachInterrupt(isr);
  437. }
  438. void AudioOutputI2Sslave::config_i2s(void)
  439. {
  440. #if defined(KINETISK)
  441. // if either transmitter or receiver is enabled, do nothing
  442. if (I2S0_TCSR & I2S_TCSR_TE) return;
  443. if (I2S0_RCSR & I2S_RCSR_RE) return;
  444. SIM_SCGC6 |= SIM_SCGC6_I2S;
  445. SIM_SCGC7 |= SIM_SCGC7_DMA;
  446. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  447. // configure pin mux for 3 clock signals
  448. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  449. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  450. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  451. // Select input clock 0
  452. // Configure to input the bit-clock from pin, bypasses the MCLK divider
  453. I2S0_MCR = I2S_MCR_MICS(0);
  454. I2S0_MDR = 0;
  455. // configure transmitter
  456. I2S0_TMR = 0;
  457. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  458. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;
  459. I2S0_TCR3 = I2S_TCR3_TCE;
  460. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
  461. | I2S_TCR4_FSE | I2S_TCR4_FSP;
  462. I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
  463. // configure receiver (sync'd to transmitter clocks)
  464. I2S0_RMR = 0;
  465. I2S0_RCR1 = I2S_RCR1_RFW(1);
  466. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;
  467. I2S0_RCR3 = I2S_RCR3_RCE;
  468. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
  469. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  470. I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
  471. #elif 0 && (defined(__IMXRT1052__) || defined(__IMXRT1062__) )
  472. #if defined(SAI1)
  473. i2s = ((I2S_STRUCT *)0x40384000);
  474. // if either transmitter or receiver is enabled, do nothing
  475. if (i2s->TX.CSR & I2S_TCSR_TE) return;
  476. if (i2s->RX.CSR & I2S_RCSR_RE) return;
  477. CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
  478. /*
  479. CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
  480. | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
  481. CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
  482. | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
  483. | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
  484. */
  485. //TODO:
  486. IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | ((uint32_t)(1<<20)) ))
  487. | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK
  488. CORE_PIN23_CONFIG = 3; //1:MCLK
  489. CORE_PIN21_CONFIG = 3; //1:RX_BCLK
  490. CORE_PIN20_CONFIG = 3; //1:RX_SYNC
  491. int rsync = 0;
  492. int tsync = 1;
  493. #elif defined(SAI2)
  494. i2s = ((I2S_STRUCT *)0x40388000);
  495. if (i2s->TX.CSR & I2S_TCSR_TE) return;
  496. if (i2s->RX.CSR & I2S_RCSR_RE) return;
  497. CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
  498. /*
  499. CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
  500. | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
  501. CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
  502. | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
  503. */
  504. //TODO:
  505. IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | ((uint32_t)(1<<19)) ))
  506. /*| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR*/ | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0); //Select MCLK
  507. CORE_PIN5_CONFIG = 2; //2:MCLK
  508. CORE_PIN4_CONFIG = 2; //2:TX_BCLK
  509. CORE_PIN3_CONFIG = 2; //2:TX_SYNC
  510. int rsync = 1;
  511. int tsync = 0;
  512. #endif
  513. // configure transmitter
  514. i2s->TX.MR = 0;
  515. i2s->TX.CR1 = I2S_TCR1_RFW(1); // watermark at half fifo size
  516. i2s->TX.CR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP;
  517. i2s->TX.CR3 = I2S_TCR3_TCE;
  518. i2s->TX.CR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
  519. | I2S_TCR4_FSE | I2S_TCR4_FSP;
  520. i2s->TX.CR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
  521. // configure receiver
  522. i2s->RX.MR = 0;
  523. i2s->RX.CR1 = I2S_RCR1_RFW(1);
  524. i2s->RX.CR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP;
  525. i2s->RX.CR3 = I2S_RCR3_RCE;
  526. i2s->RX.CR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
  527. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  528. i2s->RX.CR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
  529. #endif
  530. }