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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include "output_pwm.h"
  27. audio_block_t * AudioOutputPWM::block_1st = NULL;
  28. audio_block_t * AudioOutputPWM::block_2nd = NULL;
  29. uint32_t AudioOutputPWM::block_offset = 0;
  30. bool AudioOutputPWM::update_responsibility = false;
  31. uint8_t AudioOutputPWM::interrupt_count = 0;
  32. DMAMEM uint32_t pwm_dma_buffer[AUDIO_BLOCK_SAMPLES*2];
  33. void AudioOutputPWM::begin(void)
  34. {
  35. //Serial.println("AudioPwmOutput constructor");
  36. block_1st = NULL;
  37. FTM1_SC = 0;
  38. FTM1_CNT = 0;
  39. FTM1_MOD = 543;
  40. FTM1_C0SC = 0x69; // send DMA request on match
  41. FTM1_C1SC = 0x28;
  42. FTM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
  43. CORE_PIN3_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
  44. CORE_PIN4_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
  45. FTM1_C0V = 120; // range 120 to 375
  46. FTM1_C1V = 0; // range 0 to 255
  47. for (int i=0; i<256; i+=2) {
  48. pwm_dma_buffer[i] = 120; // zero must not be used
  49. pwm_dma_buffer[i+1] = 0;
  50. }
  51. SIM_SCGC7 |= SIM_SCGC7_DMA;
  52. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  53. DMA_CR = 0;
  54. DMA_TCD_SADDR(AUDIO_OUT_PWM_DMA_CHANNEL) = pwm_dma_buffer;
  55. DMA_TCD_SOFF(AUDIO_OUT_PWM_DMA_CHANNEL) = 4;
  56. DMA_TCD_ATTR(AUDIO_OUT_PWM_DMA_CHANNEL) = DMA_TCD_ATTR_SSIZE(2)
  57. | DMA_TCD_ATTR_DSIZE(2) | DMA_TCD_ATTR_DMOD(4);
  58. DMA_TCD_NBYTES_MLNO(AUDIO_OUT_PWM_DMA_CHANNEL) = 8;
  59. DMA_TCD_SLAST(AUDIO_OUT_PWM_DMA_CHANNEL) = -sizeof(pwm_dma_buffer);
  60. DMA_TCD_DADDR(AUDIO_OUT_PWM_DMA_CHANNEL) = &FTM1_C0V;
  61. DMA_TCD_DOFF(AUDIO_OUT_PWM_DMA_CHANNEL) = 8;
  62. DMA_TCD_CITER_ELINKNO(AUDIO_OUT_PWM_DMA_CHANNEL) = sizeof(pwm_dma_buffer) / 8;
  63. DMA_TCD_DLASTSGA(AUDIO_OUT_PWM_DMA_CHANNEL) = 0;
  64. DMA_TCD_BITER_ELINKNO(AUDIO_OUT_PWM_DMA_CHANNEL) = sizeof(pwm_dma_buffer) / 8;
  65. DMA_TCD_CSR(AUDIO_OUT_PWM_DMA_CHANNEL) = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  66. DMAMUX0_CHCFG(AUDIO_OUT_PWM_DMA_CHANNEL) = DMAMUX_DISABLE;
  67. DMAMUX0_CHCFG(AUDIO_OUT_PWM_DMA_CHANNEL) = DMAMUX_SOURCE_FTM1_CH0 | DMAMUX_ENABLE;
  68. DMA_SERQ = AUDIO_OUT_PWM_DMA_CHANNEL;
  69. update_responsibility = update_setup();
  70. NVIC_ENABLE_IRQ(IRQ_DMA_CH(AUDIO_OUT_PWM_DMA_CHANNEL));
  71. }
  72. void AudioOutputPWM::update(void)
  73. {
  74. audio_block_t *block;
  75. block = receiveReadOnly();
  76. if (!block) return;
  77. __disable_irq();
  78. if (block_1st == NULL) {
  79. block_1st = block;
  80. block_offset = 0;
  81. __enable_irq();
  82. } else if (block_2nd == NULL) {
  83. block_2nd = block;
  84. __enable_irq();
  85. } else {
  86. audio_block_t *tmp = block_1st;
  87. block_1st = block_2nd;
  88. block_2nd = block;
  89. block_offset = 0;
  90. __enable_irq();
  91. release(tmp);
  92. }
  93. }
  94. void DMA_ISR(AUDIO_OUT_PWM_DMA_CHANNEL)(void)
  95. {
  96. int16_t *src;
  97. uint32_t *dest;
  98. audio_block_t *block;
  99. uint32_t saddr, offset;
  100. saddr = (uint32_t)(DMA_TCD_SADDR(AUDIO_OUT_PWM_DMA_CHANNEL));
  101. DMA_CINT = AUDIO_OUT_PWM_DMA_CHANNEL;
  102. if (saddr < (uint32_t)pwm_dma_buffer + sizeof(pwm_dma_buffer) / 2) {
  103. // DMA is transmitting the first half of the buffer
  104. // so we must fill the second half
  105. dest = &pwm_dma_buffer[AUDIO_BLOCK_SAMPLES];
  106. } else {
  107. // DMA is transmitting the second half of the buffer
  108. // so we must fill the first half
  109. dest = pwm_dma_buffer;
  110. }
  111. block = AudioOutputPWM::block_1st;
  112. offset = AudioOutputPWM::block_offset;
  113. if (block) {
  114. src = &block->data[offset];
  115. for (int i=0; i < AUDIO_BLOCK_SAMPLES/4; i++) {
  116. uint16_t sample = *src++ + 0x8000;
  117. uint32_t msb = ((sample >> 8) & 255) + 120;
  118. uint32_t lsb = sample & 255;
  119. *dest++ = msb;
  120. *dest++ = lsb;
  121. *dest++ = msb;
  122. *dest++ = lsb;
  123. }
  124. offset += AUDIO_BLOCK_SAMPLES/4;
  125. if (offset < AUDIO_BLOCK_SAMPLES) {
  126. AudioOutputPWM::block_offset = offset;
  127. } else {
  128. AudioOutputPWM::block_offset = 0;
  129. AudioStream::release(block);
  130. AudioOutputPWM::block_1st = AudioOutputPWM::block_2nd;
  131. AudioOutputPWM::block_2nd = NULL;
  132. }
  133. } else {
  134. // fill with silence when no data available
  135. for (int i=0; i < AUDIO_BLOCK_SAMPLES/4; i++) {
  136. *dest++ = 248;
  137. *dest++ = 0;
  138. *dest++ = 248;
  139. *dest++ = 0;
  140. }
  141. }
  142. if (AudioOutputPWM::update_responsibility) {
  143. if (++AudioOutputPWM::interrupt_count >= 4) {
  144. AudioOutputPWM::interrupt_count = 0;
  145. AudioStream::update_all();
  146. }
  147. }
  148. }
  149. // DMA target is: (registers require 32 bit writes)
  150. // 40039010 Channel 0 Value (FTM1_C0V)
  151. // 40039018 Channel 1 Value (FTM1_C1V)
  152. // TCD:
  153. // source address = buffer address
  154. // source offset = 4 bytes
  155. // attr = no src mod, ssize = 32 bit, dest mod = 16 bytes (4), dsize = 32 bit
  156. // minor loop byte count = 8
  157. // source last adjust = -sizeof(buffer)
  158. // dest address = FTM1_C0V
  159. // dest address offset = 8
  160. // citer = sizeof(buffer) / 8 (no minor loop linking)
  161. // dest last adjust = 0 (dest modulo keeps it ready for more)
  162. // control:
  163. // throttling = 0
  164. // major link to same channel
  165. // done = 0
  166. // active = 0
  167. // majorlink = 1
  168. // scatter/gather = 0
  169. // disable request = 0
  170. // inthalf = 1
  171. // intmajor = 1
  172. // start = 0
  173. // biter = sizeof(buffer) / 8 (no minor loop linking)