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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include <Arduino.h>
  27. #include "input_i2s.h"
  28. #include "output_i2s.h"
  29. static uint32_t i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  30. audio_block_t * AudioInputI2S::block_left = NULL;
  31. audio_block_t * AudioInputI2S::block_right = NULL;
  32. uint16_t AudioInputI2S::block_offset = 0;
  33. bool AudioInputI2S::update_responsibility = false;
  34. DMAChannel AudioInputI2S::dma(false);
  35. void AudioInputI2S::begin(void)
  36. {
  37. dma.begin(true); // Allocate the DMA channel first
  38. //block_left_1st = NULL;
  39. //block_right_1st = NULL;
  40. // TODO: should we set & clear the I2S_RCSR_SR bit here?
  41. AudioOutputI2S::config_i2s();
  42. #if defined(KINETISK)
  43. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  44. dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2);
  45. dma.TCD->SOFF = 0;
  46. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  47. dma.TCD->NBYTES_MLNO = 2;
  48. dma.TCD->SLAST = 0;
  49. dma.TCD->DADDR = i2s_rx_buffer;
  50. dma.TCD->DOFF = 2;
  51. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  52. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  53. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  54. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  55. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
  56. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  57. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
  58. #elif defined(__IMXRT1052__) || defined(__IMXRT1062__)
  59. CORE_PIN7_CONFIG = 3; //1:RX_DATA0
  60. dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0+2);
  61. dma.TCD->SOFF = 0;
  62. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  63. dma.TCD->NBYTES_MLNO = 2;
  64. dma.TCD->SLAST = 0;
  65. dma.TCD->DADDR = i2s_rx_buffer;
  66. dma.TCD->DOFF = 2;
  67. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  68. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  69. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  70. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  71. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);
  72. // I2S1_RCSR = 0;
  73. // I2S1_TCSR = 0;
  74. // I2S1_RCSR = (1<<25); //Reset
  75. // I2S1_TCSR = (1<<25); //Reset
  76. I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE;
  77. I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE;
  78. /*
  79. I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  80. I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
  81. */
  82. #endif
  83. update_responsibility = update_setup();
  84. dma.enable();
  85. dma.attachInterrupt(isr);
  86. pinMode(13, OUTPUT);
  87. }
  88. void AudioInputI2S::isr(void)
  89. {
  90. uint32_t daddr, offset;
  91. const int16_t *src, *end;
  92. int16_t *dest_left, *dest_right;
  93. audio_block_t *left, *right;
  94. digitalWriteFast(13, HIGH);
  95. #if defined(KINETISK) || defined(__IMXRT1052__) || defined(__IMXRT1062__)
  96. daddr = (uint32_t)(dma.TCD->DADDR);
  97. #endif
  98. dma.clearInterrupt();
  99. if (daddr < (uint32_t)i2s_rx_buffer + sizeof(i2s_rx_buffer) / 2) {
  100. // DMA is receiving to the first half of the buffer
  101. // need to remove data from the second half
  102. src = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  103. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  104. if (AudioInputI2S::update_responsibility) AudioStream::update_all();
  105. } else {
  106. // DMA is receiving to the second half of the buffer
  107. // need to remove data from the first half
  108. src = (int16_t *)&i2s_rx_buffer[0];
  109. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  110. }
  111. left = AudioInputI2S::block_left;
  112. right = AudioInputI2S::block_right;
  113. if (left != NULL && right != NULL) {
  114. offset = AudioInputI2S::block_offset;
  115. if (offset <= AUDIO_BLOCK_SAMPLES/2) {
  116. dest_left = &(left->data[offset]);
  117. dest_right = &(right->data[offset]);
  118. AudioInputI2S::block_offset = offset + AUDIO_BLOCK_SAMPLES/2;
  119. do {
  120. //Serial.println(*src);
  121. //n = *src++;
  122. //*dest_left++ = (int16_t)n;
  123. //*dest_right++ = (int16_t)(n >> 16);
  124. *dest_left++ = *src++;
  125. *dest_right++ = *src++;
  126. } while (src < end);
  127. }
  128. }
  129. digitalWriteFast(13, LOW);
  130. }
  131. void AudioInputI2S::update(void)
  132. {
  133. audio_block_t *new_left=NULL, *new_right=NULL, *out_left=NULL, *out_right=NULL;
  134. // allocate 2 new blocks, but if one fails, allocate neither
  135. new_left = allocate();
  136. if (new_left != NULL) {
  137. new_right = allocate();
  138. if (new_right == NULL) {
  139. release(new_left);
  140. new_left = NULL;
  141. }
  142. }
  143. __disable_irq();
  144. if (block_offset >= AUDIO_BLOCK_SAMPLES) {
  145. // the DMA filled 2 blocks, so grab them and get the
  146. // 2 new blocks to the DMA, as quickly as possible
  147. out_left = block_left;
  148. block_left = new_left;
  149. out_right = block_right;
  150. block_right = new_right;
  151. block_offset = 0;
  152. __enable_irq();
  153. // then transmit the DMA's former blocks
  154. transmit(out_left, 0);
  155. release(out_left);
  156. transmit(out_right, 1);
  157. release(out_right);
  158. //Serial.print(".");
  159. } else if (new_left != NULL) {
  160. // the DMA didn't fill blocks, but we allocated blocks
  161. if (block_left == NULL) {
  162. // the DMA doesn't have any blocks to fill, so
  163. // give it the ones we just allocated
  164. block_left = new_left;
  165. block_right = new_right;
  166. block_offset = 0;
  167. __enable_irq();
  168. } else {
  169. // the DMA already has blocks, doesn't need these
  170. __enable_irq();
  171. release(new_left);
  172. release(new_right);
  173. }
  174. } else {
  175. // The DMA didn't fill blocks, and we could not allocate
  176. // memory... the system is likely starving for memory!
  177. // Sadly, there's nothing we can do.
  178. __enable_irq();
  179. }
  180. }
  181. /******************************************************************/
  182. void AudioInputI2Sslave::begin(void)
  183. {
  184. #if 0
  185. dma.begin(true); // Allocate the DMA channel first
  186. //block_left_1st = NULL;
  187. //block_right_1st = NULL;
  188. AudioOutputI2Sslave::config_i2s();
  189. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  190. #if defined(KINETISK)
  191. dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2);
  192. dma.TCD->SOFF = 0;
  193. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  194. dma.TCD->NBYTES_MLNO = 2;
  195. dma.TCD->SLAST = 0;
  196. dma.TCD->DADDR = i2s_rx_buffer;
  197. dma.TCD->DOFF = 2;
  198. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  199. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  200. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  201. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  202. #endif
  203. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
  204. update_responsibility = update_setup();
  205. dma.enable();
  206. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  207. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
  208. dma.attachInterrupt(isr);
  209. #endif
  210. }