visus
/
teensy-audio


			
				
					
						
						
							
							
	<h3>Summary</h3>
	<p>Transmit 16 bit stereo audio to an I2S device using I2S slave mode.</p>
	<h3>Audio Connections</h3>
	<table class=doc align=center cellpadding=3>
		<tr class=top><th>Port</th><th>Purpose</th></tr>
		<tr class=odd><td align=center>In 0</td><td>Left Channel</td></tr>
		<tr class=odd><td align=center>In 1</td><td>Right Channel</td></tr>
	</table>
	<h3>Functions</h3>
	<p>This object has no functions to call from the Arduino sketch.  It
		simply streams data from its 2 input ports to the I2S hardware.</p>
	<h3>Hardware</h3>
	<p>The I2S signals are used in "slave" mode, where the I2S device controls
		data timing.</p>
	<table class=doc align=center cellpadding=3>
		<tr class=top><th>Pin</th><th>Signal</th><th>Direction</th></tr>
		<tr class=odd><td align=center>9</td><td>BCLK</td><td>Input</td></tr>
		<tr class=odd><td align=center>22</td><td>TX</td><td>Output</td></tr>
		<tr class=odd><td align=center>23</td><td>LRCLK</td><td>Input</td></tr>
	</table>
	<h3>Examples</h3>
	<p class=exam>File &gt; Examples &gt; Audio &gt; HardwareTesting &gt; WM8731MikroSine
	</p>
	<h3>Notes</h3>
	<p>Slave mode I2S <b>should not used in the same project as ADC, DAC and
		PWM</b> signals.  Differences in timing between the I2S device and
		Teensy's clock can cause occasional audio glitches when I2S slave mode
		is used together with other input or output objects based on Teensy's
		timing.</p>
	<p>Only one I2S input and one I2S output object may be used.  Master
		and slave modes may not be mixed (both must be of the same type).
	</p>