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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include "output_i2s.h"
  27. audio_block_t * AudioOutputI2S::block_left_1st = NULL;
  28. audio_block_t * AudioOutputI2S::block_right_1st = NULL;
  29. audio_block_t * AudioOutputI2S::block_left_2nd = NULL;
  30. audio_block_t * AudioOutputI2S::block_right_2nd = NULL;
  31. uint16_t AudioOutputI2S::block_left_offset = 0;
  32. uint16_t AudioOutputI2S::block_right_offset = 0;
  33. bool AudioOutputI2S::update_responsibility = false;
  34. DMAMEM static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  35. DMAChannel AudioOutputI2S::dma(false);
  36. void AudioOutputI2S::begin(void)
  37. {
  38. dma.begin(true); // Allocate the DMA channel first
  39. block_left_1st = NULL;
  40. block_right_1st = NULL;
  41. // TODO: should we set & clear the I2S_TCSR_SR bit here?
  42. config_i2s();
  43. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  44. #if defined(KINETISK)
  45. dma.TCD->SADDR = i2s_tx_buffer;
  46. dma.TCD->SOFF = 2;
  47. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  48. dma.TCD->NBYTES_MLNO = 2;
  49. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  50. dma.TCD->DADDR = &I2S0_TDR0;
  51. dma.TCD->DOFF = 0;
  52. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  53. dma.TCD->DLASTSGA = 0;
  54. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  55. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  56. #endif
  57. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  58. update_responsibility = update_setup();
  59. dma.enable();
  60. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
  61. dma.attachInterrupt(isr);
  62. }
  63. void AudioOutputI2S::isr(void)
  64. {
  65. const int16_t *src, *end;
  66. int16_t *dest;
  67. audio_block_t *block;
  68. uint32_t saddr, offset;
  69. #if defined(KINETISK)
  70. saddr = (uint32_t)(dma.TCD->SADDR);
  71. #endif
  72. dma.clearInterrupt();
  73. if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
  74. // DMA is transmitting the first half of the buffer
  75. // so we must fill the second half
  76. dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  77. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
  78. if (AudioOutputI2S::update_responsibility) AudioStream::update_all();
  79. } else {
  80. // DMA is transmitting the second half of the buffer
  81. // so we must fill the first half
  82. dest = (int16_t *)i2s_tx_buffer;
  83. end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  84. }
  85. // TODO: these copy routines could be merged and optimized, maybe in assembly?
  86. block = AudioOutputI2S::block_left_1st;
  87. if (block) {
  88. offset = AudioOutputI2S::block_left_offset;
  89. src = &block->data[offset];
  90. do {
  91. *dest = *src++;
  92. dest += 2;
  93. } while (dest < end);
  94. offset += AUDIO_BLOCK_SAMPLES/2;
  95. if (offset < AUDIO_BLOCK_SAMPLES) {
  96. AudioOutputI2S::block_left_offset = offset;
  97. } else {
  98. AudioOutputI2S::block_left_offset = 0;
  99. AudioStream::release(block);
  100. AudioOutputI2S::block_left_1st = AudioOutputI2S::block_left_2nd;
  101. AudioOutputI2S::block_left_2nd = NULL;
  102. }
  103. } else {
  104. do {
  105. *dest = 0;
  106. dest += 2;
  107. } while (dest < end);
  108. }
  109. dest -= AUDIO_BLOCK_SAMPLES - 1;
  110. block = AudioOutputI2S::block_right_1st;
  111. if (block) {
  112. offset = AudioOutputI2S::block_right_offset;
  113. src = &block->data[offset];
  114. do {
  115. *dest = *src++;
  116. dest += 2;
  117. } while (dest < end);
  118. offset += AUDIO_BLOCK_SAMPLES/2;
  119. if (offset < AUDIO_BLOCK_SAMPLES) {
  120. AudioOutputI2S::block_right_offset = offset;
  121. } else {
  122. AudioOutputI2S::block_right_offset = 0;
  123. AudioStream::release(block);
  124. AudioOutputI2S::block_right_1st = AudioOutputI2S::block_right_2nd;
  125. AudioOutputI2S::block_right_2nd = NULL;
  126. }
  127. } else {
  128. do {
  129. *dest = 0;
  130. dest += 2;
  131. } while (dest < end);
  132. }
  133. }
  134. void AudioOutputI2S::update(void)
  135. {
  136. // null audio device: discard all incoming data
  137. //if (!active) return;
  138. //audio_block_t *block = receiveReadOnly();
  139. //if (block) release(block);
  140. audio_block_t *block;
  141. block = receiveReadOnly(0); // input 0 = left channel
  142. if (block) {
  143. __disable_irq();
  144. if (block_left_1st == NULL) {
  145. block_left_1st = block;
  146. block_left_offset = 0;
  147. __enable_irq();
  148. } else if (block_left_2nd == NULL) {
  149. block_left_2nd = block;
  150. __enable_irq();
  151. } else {
  152. audio_block_t *tmp = block_left_1st;
  153. block_left_1st = block_left_2nd;
  154. block_left_2nd = block;
  155. block_left_offset = 0;
  156. __enable_irq();
  157. release(tmp);
  158. }
  159. }
  160. block = receiveReadOnly(1); // input 1 = right channel
  161. if (block) {
  162. __disable_irq();
  163. if (block_right_1st == NULL) {
  164. block_right_1st = block;
  165. block_right_offset = 0;
  166. __enable_irq();
  167. } else if (block_right_2nd == NULL) {
  168. block_right_2nd = block;
  169. __enable_irq();
  170. } else {
  171. audio_block_t *tmp = block_right_1st;
  172. block_right_1st = block_right_2nd;
  173. block_right_2nd = block;
  174. block_right_offset = 0;
  175. __enable_irq();
  176. release(tmp);
  177. }
  178. }
  179. }
  180. // MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
  181. //
  182. #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
  183. // PLL is at 96 MHz in these modes
  184. #define MCLK_MULT 2
  185. #define MCLK_DIV 17
  186. #elif F_CPU == 72000000
  187. #define MCLK_MULT 8
  188. #define MCLK_DIV 51
  189. #elif F_CPU == 120000000
  190. #define MCLK_MULT 8
  191. #define MCLK_DIV 85
  192. #elif F_CPU == 144000000
  193. #define MCLK_MULT 4
  194. #define MCLK_DIV 51
  195. #elif F_CPU == 168000000
  196. #define MCLK_MULT 8
  197. #define MCLK_DIV 119
  198. #elif F_CPU == 16000000
  199. #define MCLK_MULT 12
  200. #define MCLK_DIV 17
  201. #else
  202. #error "This CPU Clock Speed is not supported by the Audio library";
  203. #endif
  204. #if F_CPU >= 20000000
  205. #define MCLK_SRC 3 // the PLL
  206. #else
  207. #define MCLK_SRC 0 // system clock
  208. #endif
  209. void AudioOutputI2S::config_i2s(void)
  210. {
  211. SIM_SCGC6 |= SIM_SCGC6_I2S;
  212. SIM_SCGC7 |= SIM_SCGC7_DMA;
  213. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  214. // if either transmitter or receiver is enabled, do nothing
  215. if (I2S0_TCSR & I2S_TCSR_TE) return;
  216. if (I2S0_RCSR & I2S_RCSR_RE) return;
  217. // enable MCLK output
  218. I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
  219. I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
  220. // configure transmitter
  221. I2S0_TMR = 0;
  222. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  223. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  224. | I2S_TCR2_BCD | I2S_TCR2_DIV(3);
  225. I2S0_TCR3 = I2S_TCR3_TCE;
  226. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
  227. | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
  228. I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
  229. // configure receiver (sync'd to transmitter clocks)
  230. I2S0_RMR = 0;
  231. I2S0_RCR1 = I2S_RCR1_RFW(1);
  232. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  233. | I2S_RCR2_BCD | I2S_RCR2_DIV(3);
  234. I2S0_RCR3 = I2S_RCR3_RCE;
  235. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
  236. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  237. I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
  238. // configure pin mux for 3 clock signals
  239. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  240. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  241. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  242. }
  243. /******************************************************************/
  244. void AudioOutputI2Sslave::begin(void)
  245. {
  246. dma.begin(true); // Allocate the DMA channel first
  247. //pinMode(2, OUTPUT);
  248. block_left_1st = NULL;
  249. block_right_1st = NULL;
  250. AudioOutputI2Sslave::config_i2s();
  251. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  252. #if defined(KINETISK)
  253. dma.TCD->SADDR = i2s_tx_buffer;
  254. dma.TCD->SOFF = 2;
  255. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  256. dma.TCD->NBYTES_MLNO = 2;
  257. dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
  258. dma.TCD->DADDR = &I2S0_TDR0;
  259. dma.TCD->DOFF = 0;
  260. dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  261. dma.TCD->DLASTSGA = 0;
  262. dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  263. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  264. #endif
  265. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  266. update_responsibility = update_setup();
  267. dma.enable();
  268. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
  269. dma.attachInterrupt(isr);
  270. }
  271. void AudioOutputI2Sslave::config_i2s(void)
  272. {
  273. SIM_SCGC6 |= SIM_SCGC6_I2S;
  274. SIM_SCGC7 |= SIM_SCGC7_DMA;
  275. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  276. // if either transmitter or receiver is enabled, do nothing
  277. if (I2S0_TCSR & I2S_TCSR_TE) return;
  278. if (I2S0_RCSR & I2S_RCSR_RE) return;
  279. // Select input clock 0
  280. // Configure to input the bit-clock from pin, bypasses the MCLK divider
  281. I2S0_MCR = I2S_MCR_MICS(0);
  282. I2S0_MDR = 0;
  283. // configure transmitter
  284. I2S0_TMR = 0;
  285. I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
  286. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;
  287. I2S0_TCR3 = I2S_TCR3_TCE;
  288. I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
  289. | I2S_TCR4_FSE | I2S_TCR4_FSP;
  290. I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
  291. // configure receiver (sync'd to transmitter clocks)
  292. I2S0_RMR = 0;
  293. I2S0_RCR1 = I2S_RCR1_RFW(1);
  294. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;
  295. I2S0_RCR3 = I2S_RCR3_RCE;
  296. I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
  297. | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
  298. I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
  299. // configure pin mux for 3 clock signals
  300. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
  301. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
  302. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
  303. }