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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2017, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include <Arduino.h>
  27. #include "output_tdm.h"
  28. #include "memcpy_audio.h"
  29. #include "utility/imxrt_hw.h"
  30. audio_block_t * AudioOutputTDM::block_input[16] = {
  31. nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
  32. nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr
  33. };
  34. bool AudioOutputTDM::update_responsibility = false;
  35. DMAChannel AudioOutputTDM::dma(false);
  36. DMAMEM __attribute__((aligned(32)))
  37. static uint32_t zeros[AUDIO_BLOCK_SAMPLES/2];
  38. DMAMEM __attribute__((aligned(32)))
  39. static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16];
  40. void AudioOutputTDM::begin(void)
  41. {
  42. dma.begin(true); // Allocate the DMA channel first
  43. for (int i=0; i < 16; i++) {
  44. block_input[i] = nullptr;
  45. }
  46. memset(zeros, 0, sizeof(zeros));
  47. memset(tdm_tx_buffer, 0, sizeof(tdm_tx_buffer));
  48. // TODO: should we set & clear the I2S_TCSR_SR bit here?
  49. config_tdm();
  50. #if defined(KINETISK)
  51. CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
  52. dma.TCD->SADDR = tdm_tx_buffer;
  53. dma.TCD->SOFF = 4;
  54. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
  55. dma.TCD->NBYTES_MLNO = 4;
  56. dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
  57. dma.TCD->DADDR = &I2S0_TDR0;
  58. dma.TCD->DOFF = 0;
  59. dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
  60. dma.TCD->DLASTSGA = 0;
  61. dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
  62. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  63. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
  64. update_responsibility = update_setup();
  65. dma.enable();
  66. I2S0_TCSR = I2S_TCSR_SR;
  67. I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  68. #elif defined(__IMXRT1062__)
  69. CORE_PIN7_CONFIG = 3; //1:TX_DATA0
  70. dma.TCD->SADDR = tdm_tx_buffer;
  71. dma.TCD->SOFF = 4;
  72. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
  73. dma.TCD->NBYTES_MLNO = 4;
  74. dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
  75. dma.TCD->DADDR = &I2S1_TDR0;
  76. dma.TCD->DOFF = 0;
  77. dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
  78. dma.TCD->DLASTSGA = 0;
  79. dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
  80. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  81. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
  82. update_responsibility = update_setup();
  83. dma.enable();
  84. I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
  85. I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  86. #endif
  87. dma.attachInterrupt(isr);
  88. }
  89. // TODO: needs optimization...
  90. static void memcpy_tdm_tx(uint32_t *dest, const uint32_t *src1, const uint32_t *src2)
  91. {
  92. uint32_t i, in1, in2, out1, out2;
  93. for (i=0; i < AUDIO_BLOCK_SAMPLES/4; i++) {
  94. in1 = *src1++;
  95. in2 = *src2++;
  96. out1 = (in1 << 16) | (in2 & 0xFFFF);
  97. out2 = (in1 & 0xFFFF0000) | (in2 >> 16);
  98. *dest = out1;
  99. *(dest + 8) = out2;
  100. in1 = *src1++;
  101. in2 = *src2++;
  102. out1 = (in1 << 16) | (in2 & 0xFFFF);
  103. out2 = (in1 & 0xFFFF0000) | (in2 >> 16);
  104. *(dest + 16)= out1;
  105. *(dest + 24) = out2;
  106. dest += 32;
  107. }
  108. }
  109. void AudioOutputTDM::isr(void)
  110. {
  111. uint32_t *dest;
  112. const uint32_t *src1, *src2;
  113. uint32_t i, saddr;
  114. #if defined(KINETISK) || defined(__IMXRT1062__)
  115. saddr = (uint32_t)(dma.TCD->SADDR);
  116. #endif
  117. dma.clearInterrupt();
  118. if (saddr < (uint32_t)tdm_tx_buffer + sizeof(tdm_tx_buffer) / 2) {
  119. // DMA is transmitting the first half of the buffer
  120. // so we must fill the second half
  121. dest = tdm_tx_buffer + AUDIO_BLOCK_SAMPLES*8;
  122. } else {
  123. // DMA is transmitting the second half of the buffer
  124. // so we must fill the first half
  125. dest = tdm_tx_buffer;
  126. }
  127. if (update_responsibility) AudioStream::update_all();
  128. #if IMXRT_CACHE_ENABLED >= 2
  129. uint32_t *dc = dest;
  130. #endif
  131. for (i=0; i < 16; i += 2) {
  132. src1 = block_input[i] ? (uint32_t *)(block_input[i]->data) : zeros;
  133. src2 = block_input[i+1] ? (uint32_t *)(block_input[i+1]->data) : zeros;
  134. memcpy_tdm_tx(dest, src1, src2);
  135. dest++;
  136. }
  137. #if IMXRT_CACHE_ENABLED >= 2
  138. arm_dcache_flush_delete(dc, sizeof(tdm_tx_buffer) / 2 );
  139. #endif
  140. for (i=0; i < 16; i++) {
  141. if (block_input[i]) {
  142. release(block_input[i]);
  143. block_input[i] = nullptr;
  144. }
  145. }
  146. }
  147. void AudioOutputTDM::update(void)
  148. {
  149. audio_block_t *prev[16];
  150. unsigned int i;
  151. __disable_irq();
  152. for (i=0; i < 16; i++) {
  153. prev[i] = block_input[i];
  154. block_input[i] = receiveReadOnly(i);
  155. }
  156. __enable_irq();
  157. for (i=0; i < 16; i++) {
  158. if (prev[i]) release(prev[i]);
  159. }
  160. }
  161. #if defined(KINETISK)
  162. // MCLK needs to be 48e6 / 1088 * 512 = 22.588235 MHz -> 44.117647 kHz sample rate
  163. //
  164. #if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
  165. // PLL is at 96 MHz in these modes
  166. #define MCLK_MULT 4
  167. #define MCLK_DIV 17
  168. #elif F_CPU == 72000000
  169. #define MCLK_MULT 16
  170. #define MCLK_DIV 51
  171. #elif F_CPU == 120000000
  172. #define MCLK_MULT 16
  173. #define MCLK_DIV 85
  174. #elif F_CPU == 144000000
  175. #define MCLK_MULT 8
  176. #define MCLK_DIV 51
  177. #elif F_CPU == 168000000
  178. #define MCLK_MULT 16
  179. #define MCLK_DIV 119
  180. #elif F_CPU == 180000000
  181. #define MCLK_MULT 32
  182. #define MCLK_DIV 255
  183. #define MCLK_SRC 0
  184. #elif F_CPU == 192000000
  185. #define MCLK_MULT 2
  186. #define MCLK_DIV 17
  187. #elif F_CPU == 216000000
  188. #define MCLK_MULT 12
  189. #define MCLK_DIV 17
  190. #define MCLK_SRC 1
  191. #elif F_CPU == 240000000
  192. #define MCLK_MULT 2
  193. #define MCLK_DIV 85
  194. #define MCLK_SRC 0
  195. #elif F_CPU == 256000000
  196. #define MCLK_MULT 12
  197. #define MCLK_DIV 17
  198. #define MCLK_SRC 1
  199. #else
  200. #error "This CPU Clock Speed is not supported by the Audio library";
  201. #endif
  202. #ifndef MCLK_SRC
  203. #if F_CPU >= 20000000
  204. #define MCLK_SRC 3 // the PLL
  205. #else
  206. #define MCLK_SRC 0 // system clock
  207. #endif
  208. #endif
  209. #endif
  210. void AudioOutputTDM::config_tdm(void)
  211. {
  212. #if defined(KINETISK)
  213. SIM_SCGC6 |= SIM_SCGC6_I2S;
  214. SIM_SCGC7 |= SIM_SCGC7_DMA;
  215. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  216. // if either transmitter or receiver is enabled, do nothing
  217. if (I2S0_TCSR & I2S_TCSR_TE) return;
  218. if (I2S0_RCSR & I2S_RCSR_RE) return;
  219. // enable MCLK output
  220. I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
  221. while (I2S0_MCR & I2S_MCR_DUF) ;
  222. I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
  223. // configure transmitter
  224. I2S0_TMR = 0;
  225. I2S0_TCR1 = I2S_TCR1_TFW(4);
  226. I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  227. | I2S_TCR2_BCD | I2S_TCR2_DIV(0);
  228. I2S0_TCR3 = I2S_TCR3_TCE;
  229. I2S0_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
  230. | I2S_TCR4_FSE | I2S_TCR4_FSD;
  231. I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
  232. // configure receiver (sync'd to transmitter clocks)
  233. I2S0_RMR = 0;
  234. I2S0_RCR1 = I2S_RCR1_RFW(4);
  235. I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  236. | I2S_RCR2_BCD | I2S_RCR2_DIV(0);
  237. I2S0_RCR3 = I2S_RCR3_RCE;
  238. I2S0_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
  239. | I2S_RCR4_FSE | I2S_RCR4_FSD;
  240. I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
  241. // configure pin mux for 3 clock signals
  242. CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) - 44.1kHz
  243. CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK - 11.2 MHz
  244. CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK - 22.5 MHz
  245. #elif defined(__IMXRT1062__)
  246. CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
  247. // if either transmitter or receiver is enabled, do nothing
  248. if (I2S1_TCSR & I2S_TCSR_TE) return;
  249. if (I2S1_RCSR & I2S_RCSR_RE) return;
  250. //PLL:
  251. int fs = AUDIO_SAMPLE_RATE_EXACT;
  252. // PLL between 27*24 = 648MHz und 54*24=1296MHz
  253. int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
  254. int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
  255. double C = ((double)fs * 256 * n1 * n2) / 24000000;
  256. int c0 = C;
  257. int c2 = 10000;
  258. int c1 = C * c2 - (c0 * c2);
  259. set_audioClock(c0, c1, c2);
  260. // clear SAI1_CLK register locations
  261. CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
  262. | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
  263. n1 = n1 / 2; //Double Speed for TDM
  264. CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
  265. | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
  266. | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
  267. IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
  268. | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK
  269. // configure transmitter
  270. int rsync = 0;
  271. int tsync = 1;
  272. I2S1_TMR = 0;
  273. I2S1_TCR1 = I2S_TCR1_RFW(4);
  274. I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
  275. | I2S_TCR2_BCD | I2S_TCR2_DIV(0);
  276. I2S1_TCR3 = I2S_TCR3_TCE;
  277. I2S1_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
  278. | I2S_TCR4_FSE | I2S_TCR4_FSD;
  279. I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
  280. I2S1_RMR = 0;
  281. I2S1_RCR1 = I2S_RCR1_RFW(4);
  282. I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
  283. | I2S_RCR2_BCD | I2S_RCR2_DIV(0);
  284. I2S1_RCR3 = I2S_RCR3_RCE;
  285. I2S1_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
  286. | I2S_RCR4_FSE | I2S_RCR4_FSD;
  287. I2S1_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
  288. CORE_PIN23_CONFIG = 3; //1:MCLK
  289. CORE_PIN21_CONFIG = 3; //1:RX_BCLK
  290. CORE_PIN20_CONFIG = 3; //1:RX_SYNC
  291. #endif
  292. }