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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. // Frank B
  27. #if defined(__IMXRT1052__) || defined(__IMXRT1062__)
  28. #include <Arduino.h>
  29. #include "output_mqs.h"
  30. #include "memcpy_audio.h"
  31. #include "utility/imxrt_hw.h"
  32. audio_block_t * AudioOutputMQS::block_left_1st = NULL;
  33. audio_block_t * AudioOutputMQS::block_right_1st = NULL;
  34. audio_block_t * AudioOutputMQS::block_left_2nd = NULL;
  35. audio_block_t * AudioOutputMQS::block_right_2nd = NULL;
  36. uint16_t AudioOutputMQS::block_left_offset = 0;
  37. uint16_t AudioOutputMQS::block_right_offset = 0;
  38. bool AudioOutputMQS::update_responsibility = false;
  39. DMAChannel AudioOutputMQS::dma(false);
  40. DMAMEM __attribute__((aligned(32)))
  41. static uint32_t I2S3_tx_buffer[AUDIO_BLOCK_SAMPLES];
  42. void AudioOutputMQS::begin(void)
  43. {
  44. dma.begin(true); // Allocate the DMA channel first
  45. block_left_1st = NULL;
  46. block_right_1st = NULL;
  47. config_i2s();
  48. CORE_PIN10_CONFIG = 2;//B0_00 MQS_RIGHT
  49. CORE_PIN12_CONFIG = 2;//B0_01 MQS_LEFT
  50. dma.TCD->SADDR = I2S3_tx_buffer;
  51. dma.TCD->SOFF = 2;
  52. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  53. dma.TCD->NBYTES_MLNO = 2;
  54. dma.TCD->SLAST = -sizeof(I2S3_tx_buffer);
  55. dma.TCD->DOFF = 0;
  56. dma.TCD->CITER_ELINKNO = sizeof(I2S3_tx_buffer) / 2;
  57. dma.TCD->DLASTSGA = 0;
  58. dma.TCD->BITER_ELINKNO = sizeof(I2S3_tx_buffer) / 2;
  59. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  60. dma.TCD->DADDR = (void *)((uint32_t)&I2S3_TDR0 + 0);
  61. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI3_TX);
  62. I2S3_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
  63. update_responsibility = update_setup();
  64. dma.attachInterrupt(isr);
  65. dma.enable();
  66. }
  67. void AudioOutputMQS::isr(void)
  68. {
  69. int16_t *dest;
  70. audio_block_t *blockL, *blockR;
  71. uint32_t saddr, offsetL, offsetR;
  72. saddr = (uint32_t)(dma.TCD->SADDR);
  73. dma.clearInterrupt();
  74. if (saddr < (uint32_t)I2S3_tx_buffer + sizeof(I2S3_tx_buffer) / 2) {
  75. // DMA is transmitting the first half of the buffer
  76. // so we must fill the second half
  77. dest = (int16_t *)&I2S3_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
  78. if (AudioOutputMQS::update_responsibility) AudioStream::update_all();
  79. } else {
  80. // DMA is transmitting the second half of the buffer
  81. // so we must fill the first half
  82. dest = (int16_t *)I2S3_tx_buffer;
  83. }
  84. blockL = AudioOutputMQS::block_left_1st;
  85. blockR = AudioOutputMQS::block_right_1st;
  86. offsetL = AudioOutputMQS::block_left_offset;
  87. offsetR = AudioOutputMQS::block_right_offset;
  88. if (blockL && blockR) {
  89. memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR);
  90. offsetL += AUDIO_BLOCK_SAMPLES / 2;
  91. offsetR += AUDIO_BLOCK_SAMPLES / 2;
  92. } else if (blockL) {
  93. memcpy_tointerleaveL(dest, blockL->data + offsetL);
  94. offsetL += AUDIO_BLOCK_SAMPLES / 2;
  95. } else if (blockR) {
  96. memcpy_tointerleaveR(dest, blockR->data + offsetR);
  97. offsetR += AUDIO_BLOCK_SAMPLES / 2;
  98. } else {
  99. memset(dest,0, sizeof(I2S3_tx_buffer) / 2);
  100. }
  101. #if IMXRT_CACHE_ENABLED >= 2
  102. arm_dcache_flush_delete(dest, sizeof(I2S3_tx_buffer) / 2 );
  103. #endif
  104. if (offsetL < AUDIO_BLOCK_SAMPLES) {
  105. AudioOutputMQS::block_left_offset = offsetL;
  106. } else {
  107. AudioOutputMQS::block_left_offset = 0;
  108. AudioStream::release(blockL);
  109. AudioOutputMQS::block_left_1st = AudioOutputMQS::block_left_2nd;
  110. AudioOutputMQS::block_left_2nd = NULL;
  111. }
  112. if (offsetR < AUDIO_BLOCK_SAMPLES) {
  113. AudioOutputMQS::block_right_offset = offsetR;
  114. } else {
  115. AudioOutputMQS::block_right_offset = 0;
  116. AudioStream::release(blockR);
  117. AudioOutputMQS::block_right_1st = AudioOutputMQS::block_right_2nd;
  118. AudioOutputMQS::block_right_2nd = NULL;
  119. }
  120. }
  121. void AudioOutputMQS::update(void)
  122. {
  123. // null audio device: discard all incoming data
  124. //if (!active) return;
  125. //audio_block_t *block = receiveReadOnly();
  126. //if (block) release(block);
  127. //digitalWriteFast(13, LOW);
  128. audio_block_t *block;
  129. block = receiveReadOnly(0); // input 0 = left channel
  130. if (block) {
  131. __disable_irq();
  132. if (block_left_1st == NULL) {
  133. block_left_1st = block;
  134. block_left_offset = 0;
  135. __enable_irq();
  136. } else if (block_left_2nd == NULL) {
  137. block_left_2nd = block;
  138. __enable_irq();
  139. } else {
  140. audio_block_t *tmp = block_left_1st;
  141. block_left_1st = block_left_2nd;
  142. block_left_2nd = block;
  143. block_left_offset = 0;
  144. __enable_irq();
  145. release(tmp);
  146. }
  147. }
  148. block = receiveReadOnly(1); // input 1 = right channel
  149. if (block) {
  150. __disable_irq();
  151. if (block_right_1st == NULL) {
  152. block_right_1st = block;
  153. block_right_offset = 0;
  154. __enable_irq();
  155. } else if (block_right_2nd == NULL) {
  156. block_right_2nd = block;
  157. __enable_irq();
  158. } else {
  159. audio_block_t *tmp = block_right_1st;
  160. block_right_1st = block_right_2nd;
  161. block_right_2nd = block;
  162. block_right_offset = 0;
  163. __enable_irq();
  164. release(tmp);
  165. }
  166. }
  167. }
  168. void AudioOutputMQS::config_i2s(void)
  169. {
  170. CCM_CCGR5 |= CCM_CCGR5_SAI3(CCM_CCGR_ON);
  171. CCM_CCGR0 |= CCM_CCGR0_MQS_HMCLK(CCM_CCGR_ON);
  172. //PLL:
  173. //TODO: Check if frequencies are correct!
  174. int fs = AUDIO_SAMPLE_RATE_EXACT;
  175. // PLL between 27*24 = 648MHz und 54*24=1296MHz
  176. int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
  177. int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
  178. double C = ((double)fs * 256 * n1 * n2) / 24000000;
  179. int c0 = C;
  180. int c2 = 10000;
  181. int c1 = C * c2 - (c0 * c2);
  182. set_audioClock(c0, c1, c2);
  183. CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI3_CLK_SEL_MASK))
  184. | CCM_CSCMR1_SAI3_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
  185. CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI3_CLK_PRED_MASK | CCM_CS1CDR_SAI3_CLK_PODF_MASK))
  186. | CCM_CS1CDR_SAI3_CLK_PRED(n1-1)
  187. | CCM_CS1CDR_SAI3_CLK_PODF(n2-1);
  188. IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK))
  189. | (IOMUXC_GPR_GPR1_SAI3_MCLK_DIR | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(0)); //Select MCLK
  190. IOMUXC_GPR_GPR2 = (IOMUXC_GPR_GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK))
  191. | IOMUXC_GPR_GPR2_MQS_EN /*| IOMUXC_GPR_GPR2_MQS_OVERSAMPLE */| IOMUXC_GPR_GPR2_MQS_CLK_DIV(0);
  192. if (I2S3_TCSR & I2S_TCSR_TE) return;
  193. I2S3_TMR = 0;
  194. // I2S3_TCSR = (1<<25); //Reset
  195. I2S3_TCR1 = I2S_TCR1_RFW(1);
  196. I2S3_TCR2 = I2S_TCR2_SYNC(0) /*| I2S_TCR2_BCP*/ // sync=0; tx is async;
  197. | (I2S_TCR2_BCD | I2S_TCR2_DIV((3)) | I2S_TCR2_MSEL(1));
  198. I2S3_TCR3 = I2S_TCR3_TCE;
  199. I2S3_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((16-1)) | I2S_TCR4_MF | I2S_TCR4_FSD /*| I2S_TCR4_FSE*/ /* | I2S_TCR4_FSP */;
  200. I2S3_TCR5 = I2S_TCR5_WNW((16-1)) | I2S_TCR5_W0W((16-1)) | I2S_TCR5_FBT((16-1));
  201. }
  202. #endif //defined(__IMXRT1062__)