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  1. /* Audio Library for Teensy 3.X
  2. * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
  3. *
  4. * Development of this audio library was funded by PJRC.COM, LLC by sales of
  5. * Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
  6. * open source software by purchasing Teensy or other PJRC products.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice, development funding notice, and this permission
  16. * notice shall be included in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include <Arduino.h>
  27. #include "input_i2s.h"
  28. #include "output_i2s.h"
  29. DMAMEM __attribute__((aligned(32))) static uint32_t i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  30. audio_block_t * AudioInputI2S::block_left = NULL;
  31. audio_block_t * AudioInputI2S::block_right = NULL;
  32. uint16_t AudioInputI2S::block_offset = 0;
  33. bool AudioInputI2S::update_responsibility = false;
  34. DMAChannel AudioInputI2S::dma(false);
  35. void AudioInputI2S::begin(void)
  36. {
  37. dma.begin(true); // Allocate the DMA channel first
  38. //block_left_1st = NULL;
  39. //block_right_1st = NULL;
  40. // TODO: should we set & clear the I2S_RCSR_SR bit here?
  41. AudioOutputI2S::config_i2s();
  42. #if defined(KINETISK)
  43. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  44. dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2);
  45. dma.TCD->SOFF = 0;
  46. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  47. dma.TCD->NBYTES_MLNO = 2;
  48. dma.TCD->SLAST = 0;
  49. dma.TCD->DADDR = i2s_rx_buffer;
  50. dma.TCD->DOFF = 2;
  51. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  52. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  53. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  54. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  55. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
  56. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  57. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
  58. #elif defined(__IMXRT1062__)
  59. CORE_PIN8_CONFIG = 3; //1:RX_DATA0
  60. IOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 2;
  61. dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0 + 2);
  62. dma.TCD->SOFF = 0;
  63. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  64. dma.TCD->NBYTES_MLNO = 2;
  65. dma.TCD->SLAST = 0;
  66. dma.TCD->DADDR = i2s_rx_buffer;
  67. dma.TCD->DOFF = 2;
  68. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  69. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  70. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  71. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  72. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);
  73. I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  74. #endif
  75. update_responsibility = update_setup();
  76. dma.enable();
  77. dma.attachInterrupt(isr);
  78. }
  79. void AudioInputI2S::isr(void)
  80. {
  81. uint32_t daddr, offset;
  82. const int16_t *src, *end;
  83. int16_t *dest_left, *dest_right;
  84. audio_block_t *left, *right;
  85. #if defined(KINETISK) || defined(__IMXRT1062__)
  86. daddr = (uint32_t)(dma.TCD->DADDR);
  87. dma.clearInterrupt();
  88. //Serial.println("isr");
  89. if (daddr < (uint32_t)i2s_rx_buffer + sizeof(i2s_rx_buffer) / 2) {
  90. // DMA is receiving to the first half of the buffer
  91. // need to remove data from the second half
  92. src = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  93. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES];
  94. if (AudioInputI2S::update_responsibility) AudioStream::update_all();
  95. } else {
  96. // DMA is receiving to the second half of the buffer
  97. // need to remove data from the first half
  98. src = (int16_t *)&i2s_rx_buffer[0];
  99. end = (int16_t *)&i2s_rx_buffer[AUDIO_BLOCK_SAMPLES/2];
  100. }
  101. left = AudioInputI2S::block_left;
  102. right = AudioInputI2S::block_right;
  103. if (left != NULL && right != NULL) {
  104. offset = AudioInputI2S::block_offset;
  105. if (offset <= AUDIO_BLOCK_SAMPLES/2) {
  106. dest_left = &(left->data[offset]);
  107. dest_right = &(right->data[offset]);
  108. AudioInputI2S::block_offset = offset + AUDIO_BLOCK_SAMPLES/2;
  109. arm_dcache_delete(src, sizeof(i2s_rx_buffer) / 2);
  110. do {
  111. *dest_left++ = *src++;
  112. *dest_right++ = *src++;
  113. } while (src < end);
  114. }
  115. }
  116. #endif
  117. }
  118. void AudioInputI2S::update(void)
  119. {
  120. audio_block_t *new_left=NULL, *new_right=NULL, *out_left=NULL, *out_right=NULL;
  121. // allocate 2 new blocks, but if one fails, allocate neither
  122. new_left = allocate();
  123. if (new_left != NULL) {
  124. new_right = allocate();
  125. if (new_right == NULL) {
  126. release(new_left);
  127. new_left = NULL;
  128. }
  129. }
  130. __disable_irq();
  131. if (block_offset >= AUDIO_BLOCK_SAMPLES) {
  132. // the DMA filled 2 blocks, so grab them and get the
  133. // 2 new blocks to the DMA, as quickly as possible
  134. out_left = block_left;
  135. block_left = new_left;
  136. out_right = block_right;
  137. block_right = new_right;
  138. block_offset = 0;
  139. __enable_irq();
  140. // then transmit the DMA's former blocks
  141. transmit(out_left, 0);
  142. release(out_left);
  143. transmit(out_right, 1);
  144. release(out_right);
  145. //Serial.print(".");
  146. } else if (new_left != NULL) {
  147. // the DMA didn't fill blocks, but we allocated blocks
  148. if (block_left == NULL) {
  149. // the DMA doesn't have any blocks to fill, so
  150. // give it the ones we just allocated
  151. block_left = new_left;
  152. block_right = new_right;
  153. block_offset = 0;
  154. __enable_irq();
  155. } else {
  156. // the DMA already has blocks, doesn't need these
  157. __enable_irq();
  158. release(new_left);
  159. release(new_right);
  160. }
  161. } else {
  162. // The DMA didn't fill blocks, and we could not allocate
  163. // memory... the system is likely starving for memory!
  164. // Sadly, there's nothing we can do.
  165. __enable_irq();
  166. }
  167. }
  168. /******************************************************************/
  169. void AudioInputI2Sslave::begin(void)
  170. {
  171. dma.begin(true); // Allocate the DMA channel first
  172. //block_left_1st = NULL;
  173. //block_right_1st = NULL;
  174. AudioOutputI2Sslave::config_i2s();
  175. #if defined(KINETISK)
  176. CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
  177. dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0 + 2);
  178. dma.TCD->SOFF = 0;
  179. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  180. dma.TCD->NBYTES_MLNO = 2;
  181. dma.TCD->SLAST = 0;
  182. dma.TCD->DADDR = i2s_rx_buffer;
  183. dma.TCD->DOFF = 2;
  184. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  185. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  186. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  187. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  188. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
  189. update_responsibility = update_setup();
  190. dma.enable();
  191. I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  192. I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
  193. dma.attachInterrupt(isr);
  194. #elif defined(__IMXRT1062__)
  195. CORE_PIN8_CONFIG = 3; //1:RX_DATA0
  196. IOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 2;
  197. dma.TCD->SADDR = (void *)((uint32_t)&I2S1_RDR0 + 2);
  198. dma.TCD->SOFF = 0;
  199. dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  200. dma.TCD->NBYTES_MLNO = 2;
  201. dma.TCD->SLAST = 0;
  202. dma.TCD->DADDR = i2s_rx_buffer;
  203. dma.TCD->DOFF = 2;
  204. dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  205. dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
  206. dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
  207. dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  208. dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_RX);
  209. dma.enable();
  210. I2S1_RCSR = 0;
  211. I2S1_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
  212. update_responsibility = update_setup();
  213. dma.attachInterrupt(isr);
  214. #endif
  215. }