Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2017 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. ////////////////////////////////////////////////////////////////
  34. // Tunable parameters (relatively safe to edit these numbers)
  35. ////////////////////////////////////////////////////////////////
  36. #ifndef SERIAL3_TX_BUFFER_SIZE
  37. #define SERIAL3_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer
  38. #endif
  39. #ifndef SERIAL3_RX_BUFFER_SIZE
  40. #define SERIAL3_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  41. #endif
  42. #define RTS_HIGH_WATERMARK (SERIAL3_RX_BUFFER_SIZE-24) // RTS requests sender to pause
  43. #define RTS_LOW_WATERMARK (SERIAL3_RX_BUFFER_SIZE-38) // RTS allows sender to resume
  44. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  45. ////////////////////////////////////////////////////////////////
  46. // changes not recommended below this point....
  47. ////////////////////////////////////////////////////////////////
  48. #ifdef SERIAL_9BIT_SUPPORT
  49. static uint8_t use9Bits = 0;
  50. #define BUFTYPE uint16_t
  51. #else
  52. #define BUFTYPE uint8_t
  53. #define use9Bits 0
  54. #endif
  55. static volatile BUFTYPE tx_buffer[SERIAL3_TX_BUFFER_SIZE];
  56. static volatile BUFTYPE rx_buffer[SERIAL3_RX_BUFFER_SIZE];
  57. static volatile uint8_t transmitting = 0;
  58. #if defined(KINETISK)
  59. static volatile uint8_t *transmit_pin=NULL;
  60. #define transmit_assert() *transmit_pin = 1
  61. #define transmit_deassert() *transmit_pin = 0
  62. static volatile uint8_t *rts_pin=NULL;
  63. #define rts_assert() *rts_pin = 0
  64. #define rts_deassert() *rts_pin = 1
  65. #elif defined(KINETISL)
  66. static volatile uint8_t *transmit_pin=NULL;
  67. static uint8_t transmit_mask=0;
  68. #define transmit_assert() *(transmit_pin+4) = transmit_mask;
  69. #define transmit_deassert() *(transmit_pin+8) = transmit_mask;
  70. static volatile uint8_t *rts_pin=NULL;
  71. static uint8_t rts_mask=0;
  72. #define rts_assert() *(rts_pin+8) = rts_mask;
  73. #define rts_deassert() *(rts_pin+4) = rts_mask;
  74. #endif
  75. #if SERIAL3_TX_BUFFER_SIZE > 255
  76. static volatile uint16_t tx_buffer_head = 0;
  77. static volatile uint16_t tx_buffer_tail = 0;
  78. #else
  79. static volatile uint8_t tx_buffer_head = 0;
  80. static volatile uint8_t tx_buffer_tail = 0;
  81. #endif
  82. #if SERIAL3_RX_BUFFER_SIZE > 255
  83. static volatile uint16_t rx_buffer_head = 0;
  84. static volatile uint16_t rx_buffer_tail = 0;
  85. #else
  86. static volatile uint8_t rx_buffer_head = 0;
  87. static volatile uint8_t rx_buffer_tail = 0;
  88. #endif
  89. #if defined(KINETISL)
  90. static uint8_t rx_pin_num = 7;
  91. #endif
  92. static uint8_t tx_pin_num = 8;
  93. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  94. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  95. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE
  96. #define C2_TX_ACTIVE C2_ENABLE | UART_C2_TIE
  97. #define C2_TX_COMPLETING C2_ENABLE | UART_C2_TCIE
  98. #define C2_TX_INACTIVE C2_ENABLE
  99. void serial3_begin(uint32_t divisor)
  100. {
  101. SIM_SCGC4 |= SIM_SCGC4_UART2; // turn on clock, TODO: use bitband
  102. rx_buffer_head = 0;
  103. rx_buffer_tail = 0;
  104. tx_buffer_head = 0;
  105. tx_buffer_tail = 0;
  106. transmitting = 0;
  107. #if defined(KINETISK)
  108. CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
  109. CORE_PIN8_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
  110. #elif defined(KINETISL)
  111. switch (rx_pin_num) {
  112. case 7: CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  113. case 6: CORE_PIN6_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  114. }
  115. switch (tx_pin_num) {
  116. case 8: CORE_PIN8_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  117. case 20: CORE_PIN20_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  118. }
  119. #endif
  120. #if defined(HAS_KINETISK_UART2)
  121. UART2_BDH = (divisor >> 13) & 0x1F;
  122. UART2_BDL = (divisor >> 5) & 0xFF;
  123. UART2_C4 = divisor & 0x1F;
  124. UART2_C1 = 0;
  125. UART2_PFIFO = 0;
  126. #elif defined(HAS_KINETISL_UART2)
  127. UART2_BDH = (divisor >> 8) & 0x1F;
  128. UART2_BDL = divisor & 0xFF;
  129. UART2_C1 = 0;
  130. #endif
  131. UART2_C2 = C2_TX_INACTIVE;
  132. NVIC_SET_PRIORITY(IRQ_UART2_STATUS, IRQ_PRIORITY);
  133. NVIC_ENABLE_IRQ(IRQ_UART2_STATUS);
  134. }
  135. void serial3_format(uint32_t format)
  136. {
  137. uint8_t c;
  138. c = UART2_C1;
  139. c = (c & ~0x13) | (format & 0x03); // configure parity
  140. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  141. UART2_C1 = c;
  142. if ((format & 0x0F) == 0x04) UART2_C3 |= 0x40; // 8N2 is 9 bit with 9th bit always 1
  143. c = UART2_S2 & ~0x10;
  144. if (format & 0x10) c |= 0x10; // rx invert
  145. UART2_S2 = c;
  146. c = UART2_C3 & ~0x10;
  147. if (format & 0x20) c |= 0x10; // tx invert
  148. UART2_C3 = c;
  149. #if defined(SERIAL_9BIT_SUPPORT) && !defined(KINETISL)
  150. c = UART2_C4 & 0x1F;
  151. if (format & 0x08) c |= 0x20; // 9 bit mode with parity (requires 10 bits)
  152. UART2_C4 = c;
  153. use9Bits = format & 0x80;
  154. #endif
  155. #if defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(KINETISL)
  156. // For T3.5/T3.6/TLC See about turning on 2 stop bit mode
  157. if ( format & 0x100) {
  158. uint8_t bdl = UART2_BDL;
  159. UART2_BDH |= UART_BDH_SBNS; // Turn on 2 stop bits - was turned off by set baud
  160. UART2_BDL = bdl; // Says BDH not acted on until BDL is written
  161. }
  162. #endif
  163. }
  164. void serial3_end(void)
  165. {
  166. if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return;
  167. while (transmitting) yield(); // wait for buffered data to send
  168. NVIC_DISABLE_IRQ(IRQ_UART2_STATUS);
  169. UART2_C2 = 0;
  170. #if defined(KINETISK)
  171. CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  172. CORE_PIN8_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  173. #elif defined(KINETISL)
  174. switch (rx_pin_num) {
  175. case 7: CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break;
  176. case 6: CORE_PIN6_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break;
  177. }
  178. switch (tx_pin_num & 127) {
  179. case 8: CORE_PIN8_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break;
  180. case 20: CORE_PIN20_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break;
  181. }
  182. #endif
  183. rx_buffer_head = 0;
  184. rx_buffer_tail = 0;
  185. if (rts_pin) rts_deassert();
  186. }
  187. void serial3_set_transmit_pin(uint8_t pin)
  188. {
  189. while (transmitting) ;
  190. pinMode(pin, OUTPUT);
  191. digitalWrite(pin, LOW);
  192. transmit_pin = portOutputRegister(pin);
  193. #if defined(KINETISL)
  194. transmit_mask = digitalPinToBitMask(pin);
  195. #endif
  196. }
  197. void serial3_set_tx(uint8_t pin, uint8_t opendrain)
  198. {
  199. uint32_t cfg;
  200. if (opendrain) pin |= 128;
  201. if (pin == tx_pin_num) return;
  202. if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
  203. switch (tx_pin_num & 127) {
  204. case 8: CORE_PIN8_CONFIG = 0; break; // PTD3
  205. #if defined(KINETISL)
  206. case 20: CORE_PIN20_CONFIG = 0; break; // PTD5
  207. #endif
  208. }
  209. if (opendrain) {
  210. cfg = PORT_PCR_DSE | PORT_PCR_ODE;
  211. } else {
  212. cfg = PORT_PCR_DSE | PORT_PCR_SRE;
  213. }
  214. switch (pin & 127) {
  215. case 8: CORE_PIN8_CONFIG = cfg | PORT_PCR_MUX(3); break;
  216. #if defined(KINETISL)
  217. case 20: CORE_PIN20_CONFIG = cfg | PORT_PCR_MUX(3); break;
  218. #endif
  219. }
  220. }
  221. tx_pin_num = pin;
  222. }
  223. void serial3_set_rx(uint8_t pin)
  224. {
  225. #if defined(KINETISL)
  226. if (pin == rx_pin_num) return;
  227. if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
  228. switch (rx_pin_num) {
  229. case 7: CORE_PIN7_CONFIG = 0; break; // PTD2
  230. case 6: CORE_PIN6_CONFIG = 0; break; // PTD4
  231. }
  232. switch (pin) {
  233. case 7: CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  234. case 6: CORE_PIN6_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  235. }
  236. }
  237. rx_pin_num = pin;
  238. #endif
  239. }
  240. int serial3_set_rts(uint8_t pin)
  241. {
  242. if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return 0;
  243. if (pin < CORE_NUM_DIGITAL) {
  244. rts_pin = portOutputRegister(pin);
  245. #if defined(KINETISL)
  246. rts_mask = digitalPinToBitMask(pin);
  247. #endif
  248. pinMode(pin, OUTPUT);
  249. rts_assert();
  250. } else {
  251. rts_pin = NULL;
  252. return 0;
  253. }
  254. /*
  255. if (pin == 2) {
  256. CORE_PIN2_CONFIG = PORT_PCR_MUX(3);
  257. } else {
  258. UART2_MODEM &= ~UART_MODEM_RXRTSE;
  259. return 0;
  260. }
  261. UART2_MODEM |= UART_MODEM_RXRTSE;
  262. */
  263. return 1;
  264. }
  265. int serial3_set_cts(uint8_t pin)
  266. {
  267. #if defined(KINETISK)
  268. if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return 0;
  269. if (pin == 14) {
  270. CORE_PIN14_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
  271. } else {
  272. UART2_MODEM &= ~UART_MODEM_TXCTSE;
  273. return 0;
  274. }
  275. UART2_MODEM |= UART_MODEM_TXCTSE;
  276. return 1;
  277. #else
  278. return 0;
  279. #endif
  280. }
  281. void serial3_putchar(uint32_t c)
  282. {
  283. uint32_t head, n;
  284. if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return;
  285. if (transmit_pin) transmit_assert();
  286. head = tx_buffer_head;
  287. if (++head >= SERIAL3_TX_BUFFER_SIZE) head = 0;
  288. while (tx_buffer_tail == head) {
  289. int priority = nvic_execution_priority();
  290. if (priority <= IRQ_PRIORITY) {
  291. if ((UART2_S1 & UART_S1_TDRE)) {
  292. uint32_t tail = tx_buffer_tail;
  293. if (++tail >= SERIAL3_TX_BUFFER_SIZE) tail = 0;
  294. n = tx_buffer[tail];
  295. if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2);
  296. UART2_D = n;
  297. tx_buffer_tail = tail;
  298. }
  299. } else if (priority >= 256) {
  300. yield(); // wait
  301. }
  302. }
  303. tx_buffer[head] = c;
  304. transmitting = 1;
  305. tx_buffer_head = head;
  306. UART2_C2 = C2_TX_ACTIVE;
  307. }
  308. void serial3_write(const void *buf, unsigned int count)
  309. {
  310. const uint8_t *p = (const uint8_t *)buf;
  311. while (count-- > 0) serial3_putchar(*p++);
  312. }
  313. void serial3_flush(void)
  314. {
  315. while (transmitting) yield(); // wait
  316. }
  317. int serial3_write_buffer_free(void)
  318. {
  319. uint32_t head, tail;
  320. head = tx_buffer_head;
  321. tail = tx_buffer_tail;
  322. if (head >= tail) return SERIAL3_TX_BUFFER_SIZE - 1 - head + tail;
  323. return tail - head - 1;
  324. }
  325. int serial3_available(void)
  326. {
  327. uint32_t head, tail;
  328. head = rx_buffer_head;
  329. tail = rx_buffer_tail;
  330. if (head >= tail) return head - tail;
  331. return SERIAL3_RX_BUFFER_SIZE + head - tail;
  332. }
  333. int serial3_getchar(void)
  334. {
  335. uint32_t head, tail;
  336. int c;
  337. head = rx_buffer_head;
  338. tail = rx_buffer_tail;
  339. if (head == tail) return -1;
  340. if (++tail >= SERIAL3_RX_BUFFER_SIZE) tail = 0;
  341. c = rx_buffer[tail];
  342. rx_buffer_tail = tail;
  343. if (rts_pin) {
  344. int avail;
  345. if (head >= tail) avail = head - tail;
  346. else avail = SERIAL3_RX_BUFFER_SIZE + head - tail;
  347. if (avail <= RTS_LOW_WATERMARK) rts_assert();
  348. }
  349. return c;
  350. }
  351. int serial3_peek(void)
  352. {
  353. uint32_t head, tail;
  354. head = rx_buffer_head;
  355. tail = rx_buffer_tail;
  356. if (head == tail) return -1;
  357. if (++tail >= SERIAL3_RX_BUFFER_SIZE) tail = 0;
  358. return rx_buffer[tail];
  359. }
  360. void serial3_clear(void)
  361. {
  362. rx_buffer_head = rx_buffer_tail;
  363. if (rts_pin) rts_assert();
  364. }
  365. // status interrupt combines
  366. // Transmit data below watermark UART_S1_TDRE
  367. // Transmit complete UART_S1_TC
  368. // Idle line UART_S1_IDLE
  369. // Receive data above watermark UART_S1_RDRF
  370. // LIN break detect UART_S2_LBKDIF
  371. // RxD pin active edge UART_S2_RXEDGIF
  372. void uart2_status_isr(void)
  373. {
  374. uint32_t head, tail, n;
  375. uint8_t c;
  376. if (UART2_S1 & UART_S1_RDRF) {
  377. if (use9Bits && (UART2_C3 & 0x80)) {
  378. n = UART2_D | 0x100;
  379. } else {
  380. n = UART2_D;
  381. }
  382. head = rx_buffer_head + 1;
  383. if (head >= SERIAL3_RX_BUFFER_SIZE) head = 0;
  384. if (head != rx_buffer_tail) {
  385. rx_buffer[head] = n;
  386. rx_buffer_head = head;
  387. }
  388. if (rts_pin) {
  389. int avail;
  390. tail = tx_buffer_tail;
  391. if (head >= tail) avail = head - tail;
  392. else avail = SERIAL3_RX_BUFFER_SIZE + head - tail;
  393. if (avail >= RTS_HIGH_WATERMARK) rts_deassert();
  394. }
  395. }
  396. c = UART2_C2;
  397. if ((c & UART_C2_TIE) && (UART2_S1 & UART_S1_TDRE)) {
  398. head = tx_buffer_head;
  399. tail = tx_buffer_tail;
  400. if (head == tail) {
  401. UART2_C2 = C2_TX_COMPLETING;
  402. } else {
  403. if (++tail >= SERIAL3_TX_BUFFER_SIZE) tail = 0;
  404. n = tx_buffer[tail];
  405. if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2);
  406. UART2_D = n;
  407. tx_buffer_tail = tail;
  408. }
  409. }
  410. if ((c & UART_C2_TCIE) && (UART2_S1 & UART_S1_TC)) {
  411. transmitting = 0;
  412. if (transmit_pin) transmit_deassert();
  413. UART2_C2 = C2_TX_INACTIVE;
  414. }
  415. }