Teensy 4.1 core updated for C++20
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8 лет назад
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. #ifdef HAS_KINETISK_LPUART0
  34. #define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)
  35. #define GPIO_BITBAND_PTR(reg, bit) ((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)))
  36. #define BITBAND_SET_BIT(reg, bit) (*GPIO_BITBAND_PTR((reg), (bit)) = 1)
  37. #define BITBAND_CLR_BIT(reg, bit) (*GPIO_BITBAND_PTR((reg), (bit)) = 0)
  38. #define TCIE_BIT 22
  39. #define TIE_BIT 23
  40. ////////////////////////////////////////////////////////////////
  41. // Tunable parameters (relatively safe to edit these numbers)
  42. ////////////////////////////////////////////////////////////////
  43. #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer
  44. #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  45. #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause
  46. #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume
  47. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  48. ////////////////////////////////////////////////////////////////
  49. // changes not recommended below this point....
  50. ////////////////////////////////////////////////////////////////
  51. #ifdef SERIAL_9BIT_SUPPORT
  52. static uint8_t use9Bits = 0;
  53. #define BUFTYPE uint16_t
  54. #else
  55. #define BUFTYPE uint8_t
  56. #define use9Bits 0
  57. #endif
  58. static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE];
  59. static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE];
  60. static volatile uint8_t transmitting = 0;
  61. static volatile uint8_t *transmit_pin=NULL;
  62. #define transmit_assert() *transmit_pin = 1
  63. #define transmit_deassert() *transmit_pin = 0
  64. static volatile uint8_t *rts_pin=NULL;
  65. #define rts_assert() *rts_pin = 0
  66. #define rts_deassert() *rts_pin = 1
  67. #if TX_BUFFER_SIZE > 255
  68. static volatile uint16_t tx_buffer_head = 0;
  69. static volatile uint16_t tx_buffer_tail = 0;
  70. #else
  71. static volatile uint8_t tx_buffer_head = 0;
  72. static volatile uint8_t tx_buffer_tail = 0;
  73. #endif
  74. #if RX_BUFFER_SIZE > 255
  75. static volatile uint16_t rx_buffer_head = 0;
  76. static volatile uint16_t rx_buffer_tail = 0;
  77. #else
  78. static volatile uint8_t rx_buffer_head = 0;
  79. static volatile uint8_t rx_buffer_tail = 0;
  80. #endif
  81. static uint8_t tx_pin_num = 34;
  82. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  83. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  84. void serial6_begin(uint32_t desiredBaudRate)
  85. {
  86. #define F_LPUART_CLOCK_SPEED 48000000 //F_BUS
  87. // Make sure the clock for this uart is enabled, else the registers are not
  88. // vailable.
  89. SIM_SCGC2 |= SIM_SCGC2_LPUART0; // Turn on the clock
  90. // Convert the baud rate to best divisor and OSR, based off of code I found in posting
  91. // try to find an OSR > 4 with the minimum difference from the actual disired baud rate.
  92. uint16_t sbr, sbrTemp, osrCheck;
  93. uint32_t osr, baudDiffCheck, calculatedBaud, baudDiff;
  94. uint32_t clockSpeed;
  95. // First lets figure out what the LPUART Clock speed is.
  96. uint32_t PLLFLLSEL = SIM_SOPT2 & SIM_SOPT2_IRC48SEL; // Note: Bot bits on here
  97. if (PLLFLLSEL == SIM_SOPT2_IRC48SEL)
  98. clockSpeed = 48000000; // Fixed to 48mhz
  99. else if (PLLFLLSEL == SIM_SOPT2_PLLFLLSEL)
  100. clockSpeed = F_PLL; // Using PLL clock
  101. else
  102. clockSpeed = F_CPU/4; // FLL clock, guessing
  103. osr = 4;
  104. sbr = (clockSpeed/(desiredBaudRate * osr));
  105. /*set sbr to 1 if the clockSpeed can not satisfy the desired baud rate*/
  106. if(sbr == 0) {
  107. // Maybe print something.
  108. return; // can not initialize
  109. }
  110. // With integer math the divide*muliply implies the calculated baud will be >= desired baud
  111. calculatedBaud = (clockSpeed / (osr * sbr));
  112. baudDiff = calculatedBaud - desiredBaudRate;
  113. // Check if better off with sbr+1
  114. if (baudDiff != 0) {
  115. calculatedBaud = (clockSpeed / (osr * (sbr + 1)));
  116. baudDiffCheck = desiredBaudRate - calculatedBaud ;
  117. if (baudDiffCheck < baudDiff) {
  118. sbr++; // use the higher sbr
  119. baudDiff = baudDiffCheck;
  120. }
  121. }
  122. // loop to find the best osr value possible, one that generates minimum baudDiff
  123. for (osrCheck = 5; osrCheck <= 32; osrCheck++) {
  124. sbrTemp = (clockSpeed/(desiredBaudRate * osrCheck));
  125. if(sbrTemp == 0)
  126. break; // higher divisor returns 0 so can not use...
  127. // Remember integer math so (X/Y)*Y will always be <=X
  128. calculatedBaud = (clockSpeed / (osrCheck * sbrTemp));
  129. baudDiffCheck = calculatedBaud - desiredBaudRate;
  130. if (baudDiffCheck <= baudDiff) {
  131. baudDiff = baudDiffCheck;
  132. osr = osrCheck;
  133. sbr = sbrTemp;
  134. }
  135. // Lets try the rounded up one as well
  136. if (baudDiffCheck) {
  137. calculatedBaud = (clockSpeed / (osrCheck * ++sbrTemp));
  138. baudDiffCheck = desiredBaudRate - calculatedBaud;
  139. if (baudDiffCheck <= baudDiff) {
  140. baudDiff = baudDiffCheck;
  141. osr = osrCheck;
  142. sbr = sbrTemp;
  143. }
  144. }
  145. }
  146. // for lower OSR <= 7x turn on both edge sampling
  147. uint32_t lpb = LPUART_BAUD_OSR(osr-1) | LPUART_BAUD_SBR(sbr);
  148. if (osr < 8) {
  149. lpb |= LPUART_BAUD_BOTHEDGE;
  150. }
  151. LPUART0_BAUD = lpb;
  152. SIM_SOPT2 |= SIM_SOPT2_LPUARTSRC(1); // Lets use PLL?
  153. rx_buffer_head = 0;
  154. rx_buffer_tail = 0;
  155. tx_buffer_head = 0;
  156. tx_buffer_tail = 0;
  157. transmitting = 0;
  158. CORE_PIN47_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(5);
  159. CORE_PIN48_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(5);
  160. LPUART0_CTRL = 0;
  161. LPUART0_MATCH = 0;
  162. LPUART0_STAT = 0;
  163. // Enable the transmitter, receiver and enable receiver interrupt
  164. LPUART0_CTRL |= LPUART_CTRL_RIE | LPUART_CTRL_TE | LPUART_CTRL_RE;
  165. NVIC_SET_PRIORITY(IRQ_LPUART0, IRQ_PRIORITY);
  166. NVIC_ENABLE_IRQ(IRQ_LPUART0);
  167. }
  168. void serial6_format(uint32_t format)
  169. {
  170. uint32_t c;
  171. // Bits 0-2 - Parity plus 9 bit.
  172. c = LPUART0_CTRL;
  173. //c = (c & ~(LPUART_CTRL_M | LPUART_CTRL_PE | LPUART_CTRL_PT)) | (format & (LPUART_CTRL_PE | LPUART_CTRL_PT)); // configure parity
  174. //if (format & 0x04) c |= LPUART_CTRL_M; // 9 bits (might include parity)
  175. c = (c & ~0x13) | (format & 0x03); // configure parity
  176. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  177. LPUART0_CTRL = c;
  178. if ((format & 0x0F) == 0x04) LPUART0_CTRL |= LPUART_CTRL_T8; // 8N2 is 9 bit with 9th bit always 1
  179. // Bit 3 10 bit - Will assume that begin already cleared it.
  180. if (format & 0x08)
  181. LPUART0_BAUD |= LPUART_BAUD_M10;
  182. // Bit 4 RXINVERT
  183. c = LPUART0_STAT & ~LPUART_STAT_RXINV;
  184. if (format & 0x10) c |= LPUART_STAT_RXINV; // rx invert
  185. LPUART0_STAT = c;
  186. // Bit 5 TXINVERT
  187. c = LPUART0_CTRL & ~LPUART_CTRL_TXINV;
  188. if (format & 0x20) c |= LPUART_CTRL_TXINV; // tx invert
  189. LPUART0_CTRL = c;
  190. // For T3.6 See about turning on 2 stop bit mode
  191. if ( format & 0x100) LPUART0_BAUD |= LPUART_BAUD_SBNS;
  192. }
  193. void serial6_end(void)
  194. {
  195. if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return;
  196. while (transmitting) yield(); // wait for buffered data to send
  197. NVIC_DISABLE_IRQ(IRQ_LPUART0);
  198. LPUART0_CTRL = 0;
  199. CORE_PIN47_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  200. CORE_PIN48_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  201. rx_buffer_head = 0;
  202. rx_buffer_tail = 0;
  203. if (rts_pin) rts_deassert();
  204. }
  205. void serial6_set_transmit_pin(uint8_t pin)
  206. {
  207. while (transmitting) ;
  208. pinMode(pin, OUTPUT);
  209. digitalWrite(pin, LOW);
  210. transmit_pin = portOutputRegister(pin);
  211. }
  212. void serial6_set_tx(uint8_t pin, uint8_t opendrain)
  213. {
  214. uint32_t cfg;
  215. if (opendrain) pin |= 128;
  216. if (pin == tx_pin_num) return;
  217. if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
  218. switch (tx_pin_num & 127) {
  219. case 48: CORE_PIN48_CONFIG = 0; break; // PTE24
  220. }
  221. if (opendrain) {
  222. cfg = PORT_PCR_DSE | PORT_PCR_ODE;
  223. } else {
  224. cfg = PORT_PCR_DSE | PORT_PCR_SRE;
  225. }
  226. switch (pin & 127) {
  227. case 48: CORE_PIN48_CONFIG = cfg | PORT_PCR_MUX(3); break;
  228. }
  229. }
  230. tx_pin_num = pin;
  231. }
  232. void serial6_set_rx(uint8_t pin)
  233. {
  234. }
  235. int serial6_set_rts(uint8_t pin)
  236. {
  237. if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return 0;
  238. if (pin < CORE_NUM_DIGITAL) {
  239. rts_pin = portOutputRegister(pin);
  240. pinMode(pin, OUTPUT);
  241. rts_assert();
  242. } else {
  243. rts_pin = NULL;
  244. return 0;
  245. }
  246. return 1;
  247. }
  248. int serial6_set_cts(uint8_t pin)
  249. {
  250. if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return 0;
  251. if (pin == 56) {
  252. CORE_PIN56_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
  253. } else {
  254. UART5_MODEM &= ~UART_MODEM_TXCTSE;
  255. return 0;
  256. }
  257. UART5_MODEM |= UART_MODEM_TXCTSE;
  258. return 1;
  259. }
  260. void serial6_putchar(uint32_t c)
  261. {
  262. uint32_t head, n;
  263. if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return;
  264. if (transmit_pin) transmit_assert();
  265. head = tx_buffer_head;
  266. if (++head >= TX_BUFFER_SIZE) head = 0;
  267. while (tx_buffer_tail == head) {
  268. int priority = nvic_execution_priority();
  269. if (priority <= IRQ_PRIORITY) {
  270. if ((LPUART0_STAT & LPUART_STAT_TDRE)) {
  271. uint32_t tail = tx_buffer_tail;
  272. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  273. n = tx_buffer[tail];
  274. //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2);
  275. LPUART0_DATA = n;
  276. tx_buffer_tail = tail;
  277. }
  278. } else if (priority >= 256) {
  279. yield(); // wait
  280. }
  281. }
  282. tx_buffer[head] = c;
  283. transmitting = 1;
  284. tx_buffer_head = head;
  285. //LPUART0_CTRL |= LPUART_CTRL_TIE; // enable the transmit interrupt
  286. BITBAND_SET_BIT(LPUART0_CTRL, TIE_BIT);
  287. }
  288. void serial6_write(const void *buf, unsigned int count)
  289. {
  290. const uint8_t *p = (const uint8_t *)buf;
  291. while (count-- > 0) serial6_putchar(*p++);
  292. }
  293. void serial6_flush(void)
  294. {
  295. while (transmitting) yield(); // wait
  296. }
  297. int serial6_write_buffer_free(void)
  298. {
  299. uint32_t head, tail;
  300. head = tx_buffer_head;
  301. tail = tx_buffer_tail;
  302. if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail;
  303. return tail - head - 1;
  304. }
  305. int serial6_available(void)
  306. {
  307. uint32_t head, tail;
  308. head = rx_buffer_head;
  309. tail = rx_buffer_tail;
  310. if (head >= tail) return head - tail;
  311. return RX_BUFFER_SIZE + head - tail;
  312. }
  313. int serial6_getchar(void)
  314. {
  315. uint32_t head, tail;
  316. int c;
  317. head = rx_buffer_head;
  318. tail = rx_buffer_tail;
  319. if (head == tail) return -1;
  320. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  321. c = rx_buffer[tail];
  322. rx_buffer_tail = tail;
  323. if (rts_pin) {
  324. int avail;
  325. if (head >= tail) avail = head - tail;
  326. else avail = RX_BUFFER_SIZE + head - tail;
  327. if (avail <= RTS_LOW_WATERMARK) rts_assert();
  328. }
  329. return c;
  330. }
  331. int serial6_peek(void)
  332. {
  333. uint32_t head, tail;
  334. head = rx_buffer_head;
  335. tail = rx_buffer_tail;
  336. if (head == tail) return -1;
  337. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  338. return rx_buffer[tail];
  339. }
  340. void serial6_clear(void)
  341. {
  342. rx_buffer_head = rx_buffer_tail;
  343. if (rts_pin) rts_assert();
  344. }
  345. // status interrupt combines
  346. // Transmit data below watermark LPUART_STAT_TDRE
  347. // Transmit complete LPUART_STAT_TC
  348. // Idle line LPUART_STAT_IDLE
  349. // Receive data above watermark LPUART_STAT_RDRF
  350. // LIN break detect UART_S2_LBKDIF
  351. // RxD pin active edge UART_S2_RXEDGIF
  352. void lpuart0_status_isr(void)
  353. {
  354. uint32_t head, tail, n;
  355. uint32_t c;
  356. if (LPUART0_STAT & LPUART_STAT_RDRF) {
  357. // if (use9Bits && (UART5_C3 & 0x80)) {
  358. // n = UART5_D | 0x100;
  359. // } else {
  360. // n = UART5_D;
  361. // }
  362. n = LPUART0_DATA & 0x3ff; // use only the 10 data bits
  363. head = rx_buffer_head + 1;
  364. if (head >= RX_BUFFER_SIZE) head = 0;
  365. if (head != rx_buffer_tail) {
  366. rx_buffer[head] = n;
  367. rx_buffer_head = head;
  368. }
  369. if (rts_pin) {
  370. int avail;
  371. tail = tx_buffer_tail;
  372. if (head >= tail) avail = head - tail;
  373. else avail = RX_BUFFER_SIZE + head - tail;
  374. if (avail >= RTS_HIGH_WATERMARK) rts_deassert();
  375. }
  376. }
  377. c = LPUART0_CTRL;
  378. if ((c & LPUART_CTRL_TIE) && (LPUART0_STAT & LPUART_STAT_TDRE)) {
  379. head = tx_buffer_head;
  380. tail = tx_buffer_tail;
  381. if (head == tail) {
  382. BITBAND_CLR_BIT(LPUART0_CTRL, TIE_BIT);
  383. BITBAND_SET_BIT(LPUART0_CTRL, TCIE_BIT);
  384. //LPUART0_CTRL &= ~LPUART_CTRL_TIE;
  385. //LPUART0_CTRL |= LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on...
  386. } else {
  387. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  388. n = tx_buffer[tail];
  389. //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2);
  390. LPUART0_DATA = n;
  391. tx_buffer_tail = tail;
  392. }
  393. }
  394. if ((c & LPUART_CTRL_TCIE) && (LPUART0_STAT & LPUART_STAT_TC)) {
  395. transmitting = 0;
  396. if (transmit_pin) transmit_deassert();
  397. BITBAND_CLR_BIT(LPUART0_CTRL, TCIE_BIT);
  398. // LPUART0_CTRL &= ~LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on...
  399. }
  400. }
  401. #endif // HAS_KINETISK_UART4