Teensy 4.1 core updated for C++20
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  1. #include "imxrt.h"
  2. #include "wiring.h"
  3. #include "usb_dev.h"
  4. #include "debug/printf.h"
  5. // from the linker
  6. extern unsigned long _stextload;
  7. extern unsigned long _stext;
  8. extern unsigned long _etext;
  9. extern unsigned long _sdataload;
  10. extern unsigned long _sdata;
  11. extern unsigned long _edata;
  12. extern unsigned long _sbss;
  13. extern unsigned long _ebss;
  14. __attribute__ ((used, aligned(1024)))
  15. void (* _VectorsRam[160+16])(void);
  16. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end);
  17. static void memory_clear(uint32_t *dest, uint32_t *dest_end);
  18. static void configure_systick(void);
  19. extern void systick_isr(void);
  20. void configure_cache(void);
  21. void unused_interrupt_vector(void);
  22. void usb_pll_start();
  23. extern void analog_init(void);
  24. extern void pwm_init(void);
  25. __attribute__((section(".startup")))
  26. void ResetHandler(void)
  27. {
  28. unsigned int i;
  29. //force the stack to begin at some arbitrary location
  30. //__asm__ volatile("mov sp, %0" : : "r" (0x20010000) : );
  31. // pin 13 - if startup crashes, use this to turn on the LED early for troubleshooting
  32. IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5;
  33. IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);
  34. GPIO2_GDIR |= (1<<3);
  35. GPIO2_DR_SET = (1<<3);
  36. // Initialize memory
  37. memory_copy(&_stext, &_stextload, &_etext);
  38. memory_copy(&_sdata, &_sdataload, &_edata);
  39. memory_clear(&_sbss, &_ebss);
  40. // enable FPU
  41. SCB_CPACR = 0x00F00000;
  42. // set up blank interrupt & exception vector table
  43. for (i=0; i < 176; i++) _VectorsRam[i] = &unused_interrupt_vector;
  44. SCB_VTOR = (uint32_t)_VectorsRam;
  45. // PIT & GPT timers to run from 24 MHz clock (independent of CPU speed)
  46. CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_PERCLK_PODF(0x3F)) | CCM_CSCMR1_PERCLK_CLK_SEL;
  47. // must enable PRINT_DEBUG_STUFF in debug/print.h
  48. printf_init();
  49. printf("\n***********IMXRT Startup**********\n");
  50. printf("test %d %d %d\n", 1, -1234567, 3);
  51. configure_cache();
  52. configure_systick();
  53. usb_pll_start();
  54. #if 1
  55. //uint32_t pll1;
  56. //uint32_t n =
  57. //pll = CCM_ANALOG_PLL_ARM;
  58. printf("ARM PLL = %08lX\n", CCM_ANALOG_PLL_ARM);
  59. uint32_t cdcdr = CCM_CBCDR;
  60. uint32_t cbcmr = CCM_CBCMR;
  61. printf("AHB divisor = %ld\n", ((cdcdr >> 10) & 7) + 1);
  62. printf("IPG divisor = %ld\n", ((cdcdr >> 8) & 3) + 1);
  63. if (cdcdr & CCM_CBCDR_PERIPH_CLK_SEL) {
  64. printf("using periph_clk2_clk_divided\n");
  65. } else {
  66. printf("using pre_periph_clk_sel\n");
  67. uint32_t n = (cbcmr >> 19) & 3;
  68. if (n == 0) {
  69. printf("using PLL2\n");
  70. } else if (n == 1) {
  71. printf("using PLL2 PFD2\n");
  72. } else if (n == 2) {
  73. printf("using PLL2 PFD0\n");
  74. } else {
  75. printf("using PLL1\n");
  76. }
  77. }
  78. //set_arm_clock(300000000);
  79. #endif
  80. // TODO: wait at least 20ms before starting USB
  81. usb_init();
  82. analog_init();
  83. pwm_init();
  84. // TODO: wait tat least 300ms before calling setup
  85. printf("before setup\n");
  86. setup();
  87. printf("after setup\n");
  88. while (1) {
  89. printf("loop\n");
  90. loop();
  91. }
  92. }
  93. // ARM SysTick is used for most Ardiuno timing functions, delay(), millis(),
  94. // micros(). SysTick can run from either the ARM core clock, or from an
  95. // "external" clock. NXP documents it as "24 MHz XTALOSC can be the external
  96. // clock source of SYSTICK" (RT1052 ref manual, rev 1, page 411). However,
  97. // NXP actually hid an undocumented divide-by-240 circuit in the hardware, so
  98. // the external clock is really 100 kHz. We use this clock rather than the
  99. // ARM clock, to allow SysTick to maintain correct timing even when we change
  100. // the ARM clock to run at different speeds.
  101. #define SYSTICK_EXT_FREQ 100000
  102. static void configure_systick(void)
  103. {
  104. _VectorsRam[15] = systick_isr;
  105. SYST_RVR = (SYSTICK_EXT_FREQ / 1000) - 1;
  106. SYST_CVR = 0;
  107. SYST_CSR = SYST_CSR_TICKINT | SYST_CSR_ENABLE;
  108. ARM_DEMCR |= ARM_DEMCR_TRCENA;
  109. ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA; // turn on cycle counter
  110. }
  111. // concise defines for SCB_MPU_RASR and SCB_MPU_RBAR, ARM DDI0403E, pg 696
  112. #define NOEXEC SCB_MPU_RASR_XN
  113. #define READONLY SCB_MPU_RASR_AP(7)
  114. #define READWRITE SCB_MPU_RASR_AP(3)
  115. #define NOACCESS SCB_MPU_RASR_AP(0)
  116. #define MEM_CACHE_WT SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C
  117. #define MEM_CACHE_WB SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C | SCB_MPU_RASR_B
  118. #define MEM_CACHE_WBWA SCB_MPU_RASR_TEX(1) | SCB_MPU_RASR_C | SCB_MPU_RASR_B
  119. #define MEM_NOCACHE SCB_MPU_RASR_TEX(1)
  120. #define DEV_NOCACHE SCB_MPU_RASR_TEX(2)
  121. #define SIZE_128K (SCB_MPU_RASR_SIZE(16) | SCB_MPU_RASR_ENABLE)
  122. #define SIZE_256K (SCB_MPU_RASR_SIZE(17) | SCB_MPU_RASR_ENABLE)
  123. #define SIZE_512K (SCB_MPU_RASR_SIZE(18) | SCB_MPU_RASR_ENABLE)
  124. #define SIZE_1M (SCB_MPU_RASR_SIZE(19) | SCB_MPU_RASR_ENABLE)
  125. #define SIZE_2M (SCB_MPU_RASR_SIZE(20) | SCB_MPU_RASR_ENABLE)
  126. #define SIZE_4M (SCB_MPU_RASR_SIZE(21) | SCB_MPU_RASR_ENABLE)
  127. #define SIZE_8M (SCB_MPU_RASR_SIZE(22) | SCB_MPU_RASR_ENABLE)
  128. #define SIZE_16M (SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE)
  129. #define SIZE_32M (SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE)
  130. #define SIZE_64M (SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE)
  131. #define REGION(n) (SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID)
  132. __attribute__((section(".progmem")))
  133. void configure_cache(void)
  134. {
  135. //printf("MPU_TYPE = %08lX\n", SCB_MPU_TYPE);
  136. //printf("CCR = %08lX\n", SCB_CCR);
  137. // TODO: check if caches already active - skip?
  138. SCB_MPU_CTRL = 0; // turn off MPU
  139. SCB_MPU_RBAR = 0x00000000 | REGION(0); // ITCM
  140. SCB_MPU_RASR = MEM_NOCACHE | READWRITE | SIZE_512K;
  141. SCB_MPU_RBAR = 0x00200000 | REGION(1); // Boot ROM
  142. SCB_MPU_RASR = MEM_CACHE_WT | READONLY | SIZE_128K;
  143. SCB_MPU_RBAR = 0x20000000 | REGION(2); // DTCM
  144. SCB_MPU_RASR = MEM_NOCACHE | READWRITE | NOEXEC | SIZE_512K;
  145. SCB_MPU_RBAR = 0x20200000 | REGION(3); // RAM (AXI bus)
  146. SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_1M;
  147. SCB_MPU_RBAR = 0x40000000 | REGION(4); // Peripherals
  148. SCB_MPU_RASR = DEV_NOCACHE | READWRITE | NOEXEC | SIZE_64M;
  149. SCB_MPU_RBAR = 0x60000000 | REGION(5); // QSPI Flash
  150. SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;
  151. // TODO: 32 byte sub-region at 0x00000000 with NOACCESS, to trap NULL pointer deref
  152. // TODO: protect access to power supply config
  153. // TODO: 32 byte sub-region at end of .bss section with NOACCESS, to trap stack overflow
  154. SCB_MPU_CTRL = SCB_MPU_CTRL_ENABLE;
  155. // cache enable, ARM DDI0403E, pg 628
  156. asm("dsb");
  157. asm("isb");
  158. SCB_CACHE_ICIALLU = 0;
  159. asm("dsb");
  160. asm("isb");
  161. SCB_CCR |= (SCB_CCR_IC | SCB_CCR_DC);
  162. }
  163. uint32_t set_arm_clock(uint32_t frequency)
  164. {
  165. if (!(CCM_CBCDR & CCM_CBCDR_PERIPH_CLK_SEL)) {
  166. //print("need to switch to stable clock while reconfigure of ARM PLL\n");
  167. const uint32_t need1s = CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_POWER |
  168. CCM_ANALOG_PLL_USB1_LOCK | CCM_ANALOG_PLL_USB1_EN_USB_CLKS;
  169. if ((CCM_ANALOG_PLL_USB1 & need1s) == need1s) {
  170. //print(" run temporarily from USB/4 (120 MHz)\n");
  171. } else {
  172. //print(" run temporarily from crystal (24 MHz)\n");
  173. }
  174. } else {
  175. //print("already running from an alternate clock, ok to mess with ARM PLL\n");
  176. }
  177. // if SYS PLL running at 528 MHz
  178. // if frequency == 528
  179. // if frequency == 396
  180. // if frequency == 352
  181. //
  182. return frequency;
  183. }
  184. __attribute__((section(".progmem")))
  185. void usb_pll_start()
  186. {
  187. while (1) {
  188. uint32_t n = CCM_ANALOG_PLL_USB1; // pg 759
  189. printf("CCM_ANALOG_PLL_USB1=%08lX\n", n);
  190. if (n & CCM_ANALOG_PLL_USB1_DIV_SELECT) {
  191. printf(" ERROR, 528 MHz mode!\n"); // never supposed to use this mode!
  192. CCM_ANALOG_PLL_USB1_CLR = 0xC000; // bypass 24 MHz
  193. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS; // bypass
  194. CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER | // power down
  195. CCM_ANALOG_PLL_USB1_DIV_SELECT | // use 480 MHz
  196. CCM_ANALOG_PLL_USB1_ENABLE | // disable
  197. CCM_ANALOG_PLL_USB1_EN_USB_CLKS; // disable usb
  198. continue;
  199. }
  200. if (!(n & CCM_ANALOG_PLL_USB1_ENABLE)) {
  201. printf(" enable PLL\n");
  202. // TODO: should this be done so early, or later??
  203. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE;
  204. continue;
  205. }
  206. if (!(n & CCM_ANALOG_PLL_USB1_POWER)) {
  207. printf(" power up PLL\n");
  208. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_POWER;
  209. continue;
  210. }
  211. if (!(n & CCM_ANALOG_PLL_USB1_LOCK)) {
  212. printf(" wait for lock\n");
  213. continue;
  214. }
  215. if (n & CCM_ANALOG_PLL_USB1_BYPASS) {
  216. printf(" turn off bypass\n");
  217. CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_BYPASS;
  218. continue;
  219. }
  220. if (!(n & CCM_ANALOG_PLL_USB1_EN_USB_CLKS)) {
  221. printf(" enable USB clocks\n");
  222. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_EN_USB_CLKS;
  223. continue;
  224. }
  225. return; // everything is as it should be :-)
  226. }
  227. }
  228. // Stack frame
  229. // xPSR
  230. // ReturnAddress
  231. // LR (R14) - typically FFFFFFF9 for IRQ or Exception
  232. // R12
  233. // R3
  234. // R2
  235. // R1
  236. // R0
  237. void unused_interrupt_vector(void)
  238. {
  239. // TODO: polling Serial to complete buffered transmits
  240. #ifdef PRINT_DEBUG_STUFF
  241. uint32_t addr;
  242. asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);
  243. printf("\nirq %d\n", addr & 0x1FF);
  244. asm("ldr %0, [sp, #52]" : "=r" (addr) ::);
  245. printf(" %x\n", addr);
  246. asm("ldr %0, [sp, #48]" : "=r" (addr) ::);
  247. printf(" %x\n", addr);
  248. asm("ldr %0, [sp, #44]" : "=r" (addr) ::);
  249. printf(" %x\n", addr);
  250. asm("ldr %0, [sp, #40]" : "=r" (addr) ::);
  251. printf(" %x\n", addr);
  252. asm("ldr %0, [sp, #36]" : "=r" (addr) ::);
  253. printf(" %x\n", addr);
  254. asm("ldr %0, [sp, #33]" : "=r" (addr) ::);
  255. printf(" %x\n", addr);
  256. asm("ldr %0, [sp, #34]" : "=r" (addr) ::);
  257. printf(" %x\n", addr);
  258. asm("ldr %0, [sp, #28]" : "=r" (addr) ::);
  259. printf(" %x\n", addr);
  260. asm("ldr %0, [sp, #24]" : "=r" (addr) ::);
  261. printf(" %x\n", addr);
  262. asm("ldr %0, [sp, #20]" : "=r" (addr) ::);
  263. printf(" %x\n", addr);
  264. asm("ldr %0, [sp, #16]" : "=r" (addr) ::);
  265. printf(" %x\n", addr);
  266. asm("ldr %0, [sp, #12]" : "=r" (addr) ::);
  267. printf(" %x\n", addr);
  268. asm("ldr %0, [sp, #8]" : "=r" (addr) ::);
  269. printf(" %x\n", addr);
  270. asm("ldr %0, [sp, #4]" : "=r" (addr) ::);
  271. printf(" %x\n", addr);
  272. asm("ldr %0, [sp, #0]" : "=r" (addr) ::);
  273. printf(" %x\n", addr);
  274. #endif
  275. #if 1
  276. IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13
  277. IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);
  278. GPIO2_GDIR |= (1<<3);
  279. GPIO2_DR_SET = (1<<3);
  280. while (1) {
  281. volatile uint32_t n;
  282. GPIO2_DR_SET = (1<<3); //digitalWrite(13, HIGH);
  283. for (n=0; n < 2000000; n++) ;
  284. GPIO2_DR_CLEAR = (1<<3); //digitalWrite(13, LOW);
  285. for (n=0; n < 1500000; n++) ;
  286. }
  287. #else
  288. while (1) {
  289. }
  290. #endif
  291. }
  292. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end)
  293. {
  294. if (dest == src) return;
  295. while (dest < dest_end) {
  296. *dest++ = *src++;
  297. }
  298. }
  299. static void memory_clear(uint32_t *dest, uint32_t *dest_end)
  300. {
  301. while (dest < dest_end) {
  302. *dest++ = 0;
  303. }
  304. }