Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #ifndef _kinetis_h_
  31. #define _kinetis_h_
  32. #include <stdint.h>
  33. // Teensy 3.0
  34. #if defined(__MK20DX128__)
  35. enum IRQ_NUMBER_t {
  36. IRQ_DMA_CH0 = 0,
  37. IRQ_DMA_CH1 = 1,
  38. IRQ_DMA_CH2 = 2,
  39. IRQ_DMA_CH3 = 3,
  40. IRQ_DMA_ERROR = 4,
  41. IRQ_FTFL_COMPLETE = 6,
  42. IRQ_FTFL_COLLISION = 7,
  43. IRQ_LOW_VOLTAGE = 8,
  44. IRQ_LLWU = 9,
  45. IRQ_WDOG = 10,
  46. IRQ_I2C0 = 11,
  47. IRQ_SPI0 = 12,
  48. IRQ_I2S0_TX = 13,
  49. IRQ_I2S0_RX = 14,
  50. IRQ_UART0_LON = 15,
  51. IRQ_UART0_STATUS = 16,
  52. IRQ_UART0_ERROR = 17,
  53. IRQ_UART1_STATUS = 18,
  54. IRQ_UART1_ERROR = 19,
  55. IRQ_UART2_STATUS = 20,
  56. IRQ_UART2_ERROR = 21,
  57. IRQ_ADC0 = 22,
  58. IRQ_CMP0 = 23,
  59. IRQ_CMP1 = 24,
  60. IRQ_FTM0 = 25,
  61. IRQ_FTM1 = 26,
  62. IRQ_CMT = 27,
  63. IRQ_RTC_ALARM = 28,
  64. IRQ_RTC_SECOND = 29,
  65. IRQ_PIT_CH0 = 30,
  66. IRQ_PIT_CH1 = 31,
  67. IRQ_PIT_CH2 = 32,
  68. IRQ_PIT_CH3 = 33,
  69. IRQ_PDB = 34,
  70. IRQ_USBOTG = 35,
  71. IRQ_USBDCD = 36,
  72. IRQ_TSI = 37,
  73. IRQ_MCG = 38,
  74. IRQ_LPTMR = 39,
  75. IRQ_PORTA = 40,
  76. IRQ_PORTB = 41,
  77. IRQ_PORTC = 42,
  78. IRQ_PORTD = 43,
  79. IRQ_PORTE = 44,
  80. IRQ_SOFTWARE = 45
  81. };
  82. #define NVIC_NUM_INTERRUPTS 46
  83. #define DMA_NUM_CHANNELS 4
  84. #define KINETISK
  85. #define HAS_KINETISK_UART0
  86. #define HAS_KINETISK_UART0_FIFO
  87. #define HAS_KINETISK_UART1
  88. #define HAS_KINETISK_UART2
  89. #define HAS_KINETIS_I2C0
  90. // Teensy 3.1
  91. #elif defined(__MK20DX256__)
  92. enum IRQ_NUMBER_t {
  93. IRQ_DMA_CH0 = 0,
  94. IRQ_DMA_CH1 = 1,
  95. IRQ_DMA_CH2 = 2,
  96. IRQ_DMA_CH3 = 3,
  97. IRQ_DMA_CH4 = 4,
  98. IRQ_DMA_CH5 = 5,
  99. IRQ_DMA_CH6 = 6,
  100. IRQ_DMA_CH7 = 7,
  101. IRQ_DMA_CH8 = 8,
  102. IRQ_DMA_CH9 = 9,
  103. IRQ_DMA_CH10 = 10,
  104. IRQ_DMA_CH11 = 11,
  105. IRQ_DMA_CH12 = 12,
  106. IRQ_DMA_CH13 = 13,
  107. IRQ_DMA_CH14 = 14,
  108. IRQ_DMA_CH15 = 15,
  109. IRQ_DMA_ERROR = 16,
  110. IRQ_FTFL_COMPLETE = 18,
  111. IRQ_FTFL_COLLISION = 19,
  112. IRQ_LOW_VOLTAGE = 20,
  113. IRQ_LLWU = 21,
  114. IRQ_WDOG = 22,
  115. IRQ_I2C0 = 24,
  116. IRQ_I2C1 = 25,
  117. IRQ_SPI0 = 26,
  118. IRQ_SPI1 = 27,
  119. IRQ_CAN_MESSAGE = 29,
  120. IRQ_CAN_BUS_OFF = 30,
  121. IRQ_CAN_ERROR = 31,
  122. IRQ_CAN_TX_WARN = 32,
  123. IRQ_CAN_RX_WARN = 33,
  124. IRQ_CAN_WAKEUP = 34,
  125. IRQ_I2S0_TX = 35,
  126. IRQ_I2S0_RX = 36,
  127. IRQ_UART0_LON = 44,
  128. IRQ_UART0_STATUS = 45,
  129. IRQ_UART0_ERROR = 46,
  130. IRQ_UART1_STATUS = 47,
  131. IRQ_UART1_ERROR = 48,
  132. IRQ_UART2_STATUS = 49,
  133. IRQ_UART2_ERROR = 50,
  134. IRQ_ADC0 = 57,
  135. IRQ_ADC1 = 58,
  136. IRQ_CMP0 = 59,
  137. IRQ_CMP1 = 60,
  138. IRQ_CMP2 = 61,
  139. IRQ_FTM0 = 62,
  140. IRQ_FTM1 = 63,
  141. IRQ_FTM2 = 64,
  142. IRQ_CMT = 65,
  143. IRQ_RTC_ALARM = 66,
  144. IRQ_RTC_SECOND = 67,
  145. IRQ_PIT_CH0 = 68,
  146. IRQ_PIT_CH1 = 69,
  147. IRQ_PIT_CH2 = 70,
  148. IRQ_PIT_CH3 = 71,
  149. IRQ_PDB = 72,
  150. IRQ_USBOTG = 73,
  151. IRQ_USBDCD = 74,
  152. IRQ_DAC0 = 81,
  153. IRQ_TSI = 83,
  154. IRQ_MCG = 84,
  155. IRQ_LPTMR = 85,
  156. IRQ_PORTA = 87,
  157. IRQ_PORTB = 88,
  158. IRQ_PORTC = 89,
  159. IRQ_PORTD = 90,
  160. IRQ_PORTE = 91,
  161. IRQ_SOFTWARE = 94
  162. };
  163. #define NVIC_NUM_INTERRUPTS 95
  164. #define DMA_NUM_CHANNELS 16
  165. #define KINETISK
  166. #define HAS_KINETISK_UART0
  167. #define HAS_KINETISK_UART0_FIFO
  168. #define HAS_KINETISK_UART1
  169. #define HAS_KINETISK_UART1_FIFO
  170. #define HAS_KINETISK_UART2
  171. #define HAS_KINETIS_I2C0
  172. #define HAS_KINETIS_I2C1
  173. #elif defined(__MKL26Z64__)
  174. enum IRQ_NUMBER_t {
  175. IRQ_DMA_CH0 = 0,
  176. IRQ_DMA_CH1 = 1,
  177. IRQ_DMA_CH2 = 2,
  178. IRQ_DMA_CH3 = 3,
  179. IRQ_FTFA = 5,
  180. IRQ_LOW_VOLTAGE = 6,
  181. IRQ_LLWU = 7,
  182. IRQ_I2C0 = 8,
  183. IRQ_I2C1 = 9,
  184. IRQ_SPI0 = 10,
  185. IRQ_SPI1 = 11,
  186. IRQ_UART0_STATUS = 12,
  187. IRQ_UART1_STATUS = 13,
  188. IRQ_UART2_STATUS = 14,
  189. IRQ_ADC0 = 15,
  190. IRQ_CMP0 = 16,
  191. IRQ_FTM0 = 17,
  192. IRQ_FTM1 = 18,
  193. IRQ_FTM2 = 19,
  194. IRQ_RTC_ALARM = 20,
  195. IRQ_RTC_SECOND = 21,
  196. IRQ_PIT = 22,
  197. IRQ_I2S0 = 23,
  198. IRQ_USBOTG = 24,
  199. IRQ_DAC0 = 25,
  200. IRQ_TSI = 26,
  201. IRQ_MCG = 27,
  202. IRQ_LPTMR = 28,
  203. IRQ_SOFTWARE = 29, // TODO: verify this works
  204. IRQ_PORTA = 30,
  205. IRQ_PORTCD = 31
  206. };
  207. #define NVIC_NUM_INTERRUPTS 32
  208. #define DMA_NUM_CHANNELS 4
  209. #define KINETISL
  210. #define HAS_KINETISL_UART0
  211. #define HAS_KINETISL_UART1
  212. #define HAS_KINETISL_UART2
  213. #define HAS_KINETIS_I2C0
  214. #define HAS_KINETIS_I2C0_STOPF
  215. #define HAS_KINETIS_I2C1
  216. #define HAS_KINETIS_I2C1_STOPF
  217. #endif // end of board-specific definitions
  218. #if (F_CPU == 168000000)
  219. #define F_PLL 168000000
  220. #define F_BUS 56000000
  221. #define F_MEM 33600000
  222. #elif (F_CPU == 144000000)
  223. #define F_PLL 144000000
  224. #define F_BUS 48000000
  225. #define F_MEM 28800000
  226. #elif (F_CPU == 120000000)
  227. #define F_PLL 120000000
  228. #define F_BUS 60000000
  229. #define F_MEM 24000000
  230. #elif (F_CPU == 96000000)
  231. #define F_PLL 96000000
  232. #define F_BUS 48000000
  233. #define F_MEM 24000000
  234. #elif (F_CPU == 72000000)
  235. #define F_PLL 72000000
  236. #define F_BUS 36000000
  237. #define F_MEM 24000000
  238. #elif (F_CPU == 48000000)
  239. #define F_PLL 96000000
  240. #if defined(KINETISK)
  241. #define F_BUS 48000000
  242. #elif defined(KINETISL)
  243. #define F_BUS 24000000
  244. #endif
  245. #define F_MEM 24000000
  246. #elif (F_CPU == 24000000)
  247. #define F_PLL 96000000
  248. #define F_BUS 24000000
  249. #define F_MEM 24000000
  250. #elif (F_CPU == 16000000)
  251. #define F_PLL 16000000
  252. #define F_BUS 16000000
  253. #define F_MEM 16000000
  254. #elif (F_CPU == 8000000)
  255. #define F_PLL 8000000
  256. #define F_BUS 8000000
  257. #define F_MEM 8000000
  258. #elif (F_CPU == 4000000)
  259. #define F_PLL 4000000
  260. #define F_BUS 4000000
  261. #define F_MEM 4000000
  262. #elif (F_CPU == 2000000)
  263. #define F_PLL 2000000
  264. #define F_BUS 2000000
  265. #define F_MEM 1000000
  266. #endif
  267. #ifndef NULL
  268. #define NULL ((void *)0)
  269. #endif
  270. // chapter 11: Port control and interrupts (PORT)
  271. #define PORTA_PCR0 (*(volatile uint32_t *)0x40049000) // Pin Control Register n
  272. #define PORT_PCR_ISF ((uint32_t)0x01000000) // Interrupt Status Flag
  273. #define PORT_PCR_IRQC(n) ((uint32_t)(((n) & 15) << 16)) // Interrupt Configuration
  274. #define PORT_PCR_IRQC_MASK ((uint32_t)0x000F0000)
  275. #define PORT_PCR_LK ((uint32_t)0x00008000) // Lock Register
  276. #define PORT_PCR_MUX(n) ((uint32_t)(((n) & 7) << 8)) // Pin Mux Control
  277. #define PORT_PCR_MUX_MASK ((uint32_t)0x00000700)
  278. #define PORT_PCR_DSE ((uint32_t)0x00000040) // Drive Strength Enable
  279. #define PORT_PCR_ODE ((uint32_t)0x00000020) // Open Drain Enable
  280. #define PORT_PCR_PFE ((uint32_t)0x00000010) // Passive Filter Enable
  281. #define PORT_PCR_SRE ((uint32_t)0x00000004) // Slew Rate Enable
  282. #define PORT_PCR_PE ((uint32_t)0x00000002) // Pull Enable
  283. #define PORT_PCR_PS ((uint32_t)0x00000001) // Pull Select
  284. #define PORTA_PCR1 (*(volatile uint32_t *)0x40049004) // Pin Control Register n
  285. #define PORTA_PCR2 (*(volatile uint32_t *)0x40049008) // Pin Control Register n
  286. #define PORTA_PCR3 (*(volatile uint32_t *)0x4004900C) // Pin Control Register n
  287. #define PORTA_PCR4 (*(volatile uint32_t *)0x40049010) // Pin Control Register n
  288. #define PORTA_PCR5 (*(volatile uint32_t *)0x40049014) // Pin Control Register n
  289. #define PORTA_PCR6 (*(volatile uint32_t *)0x40049018) // Pin Control Register n
  290. #define PORTA_PCR7 (*(volatile uint32_t *)0x4004901C) // Pin Control Register n
  291. #define PORTA_PCR8 (*(volatile uint32_t *)0x40049020) // Pin Control Register n
  292. #define PORTA_PCR9 (*(volatile uint32_t *)0x40049024) // Pin Control Register n
  293. #define PORTA_PCR10 (*(volatile uint32_t *)0x40049028) // Pin Control Register n
  294. #define PORTA_PCR11 (*(volatile uint32_t *)0x4004902C) // Pin Control Register n
  295. #define PORTA_PCR12 (*(volatile uint32_t *)0x40049030) // Pin Control Register n
  296. #define PORTA_PCR13 (*(volatile uint32_t *)0x40049034) // Pin Control Register n
  297. #define PORTA_PCR14 (*(volatile uint32_t *)0x40049038) // Pin Control Register n
  298. #define PORTA_PCR15 (*(volatile uint32_t *)0x4004903C) // Pin Control Register n
  299. #define PORTA_PCR16 (*(volatile uint32_t *)0x40049040) // Pin Control Register n
  300. #define PORTA_PCR17 (*(volatile uint32_t *)0x40049044) // Pin Control Register n
  301. #define PORTA_PCR18 (*(volatile uint32_t *)0x40049048) // Pin Control Register n
  302. #define PORTA_PCR19 (*(volatile uint32_t *)0x4004904C) // Pin Control Register n
  303. #define PORTA_PCR20 (*(volatile uint32_t *)0x40049050) // Pin Control Register n
  304. #define PORTA_PCR21 (*(volatile uint32_t *)0x40049054) // Pin Control Register n
  305. #define PORTA_PCR22 (*(volatile uint32_t *)0x40049058) // Pin Control Register n
  306. #define PORTA_PCR23 (*(volatile uint32_t *)0x4004905C) // Pin Control Register n
  307. #define PORTA_PCR24 (*(volatile uint32_t *)0x40049060) // Pin Control Register n
  308. #define PORTA_PCR25 (*(volatile uint32_t *)0x40049064) // Pin Control Register n
  309. #define PORTA_PCR26 (*(volatile uint32_t *)0x40049068) // Pin Control Register n
  310. #define PORTA_PCR27 (*(volatile uint32_t *)0x4004906C) // Pin Control Register n
  311. #define PORTA_PCR28 (*(volatile uint32_t *)0x40049070) // Pin Control Register n
  312. #define PORTA_PCR29 (*(volatile uint32_t *)0x40049074) // Pin Control Register n
  313. #define PORTA_PCR30 (*(volatile uint32_t *)0x40049078) // Pin Control Register n
  314. #define PORTA_PCR31 (*(volatile uint32_t *)0x4004907C) // Pin Control Register n
  315. #define PORTA_GPCLR (*(volatile uint32_t *)0x40049080) // Global Pin Control Low Register
  316. #define PORTA_GPCHR (*(volatile uint32_t *)0x40049084) // Global Pin Control High Register
  317. #define PORTA_ISFR (*(volatile uint32_t *)0x400490A0) // Interrupt Status Flag Register
  318. #define PORTB_PCR0 (*(volatile uint32_t *)0x4004A000) // Pin Control Register n
  319. #define PORTB_PCR1 (*(volatile uint32_t *)0x4004A004) // Pin Control Register n
  320. #define PORTB_PCR2 (*(volatile uint32_t *)0x4004A008) // Pin Control Register n
  321. #define PORTB_PCR3 (*(volatile uint32_t *)0x4004A00C) // Pin Control Register n
  322. #define PORTB_PCR4 (*(volatile uint32_t *)0x4004A010) // Pin Control Register n
  323. #define PORTB_PCR5 (*(volatile uint32_t *)0x4004A014) // Pin Control Register n
  324. #define PORTB_PCR6 (*(volatile uint32_t *)0x4004A018) // Pin Control Register n
  325. #define PORTB_PCR7 (*(volatile uint32_t *)0x4004A01C) // Pin Control Register n
  326. #define PORTB_PCR8 (*(volatile uint32_t *)0x4004A020) // Pin Control Register n
  327. #define PORTB_PCR9 (*(volatile uint32_t *)0x4004A024) // Pin Control Register n
  328. #define PORTB_PCR10 (*(volatile uint32_t *)0x4004A028) // Pin Control Register n
  329. #define PORTB_PCR11 (*(volatile uint32_t *)0x4004A02C) // Pin Control Register n
  330. #define PORTB_PCR12 (*(volatile uint32_t *)0x4004A030) // Pin Control Register n
  331. #define PORTB_PCR13 (*(volatile uint32_t *)0x4004A034) // Pin Control Register n
  332. #define PORTB_PCR14 (*(volatile uint32_t *)0x4004A038) // Pin Control Register n
  333. #define PORTB_PCR15 (*(volatile uint32_t *)0x4004A03C) // Pin Control Register n
  334. #define PORTB_PCR16 (*(volatile uint32_t *)0x4004A040) // Pin Control Register n
  335. #define PORTB_PCR17 (*(volatile uint32_t *)0x4004A044) // Pin Control Register n
  336. #define PORTB_PCR18 (*(volatile uint32_t *)0x4004A048) // Pin Control Register n
  337. #define PORTB_PCR19 (*(volatile uint32_t *)0x4004A04C) // Pin Control Register n
  338. #define PORTB_PCR20 (*(volatile uint32_t *)0x4004A050) // Pin Control Register n
  339. #define PORTB_PCR21 (*(volatile uint32_t *)0x4004A054) // Pin Control Register n
  340. #define PORTB_PCR22 (*(volatile uint32_t *)0x4004A058) // Pin Control Register n
  341. #define PORTB_PCR23 (*(volatile uint32_t *)0x4004A05C) // Pin Control Register n
  342. #define PORTB_PCR24 (*(volatile uint32_t *)0x4004A060) // Pin Control Register n
  343. #define PORTB_PCR25 (*(volatile uint32_t *)0x4004A064) // Pin Control Register n
  344. #define PORTB_PCR26 (*(volatile uint32_t *)0x4004A068) // Pin Control Register n
  345. #define PORTB_PCR27 (*(volatile uint32_t *)0x4004A06C) // Pin Control Register n
  346. #define PORTB_PCR28 (*(volatile uint32_t *)0x4004A070) // Pin Control Register n
  347. #define PORTB_PCR29 (*(volatile uint32_t *)0x4004A074) // Pin Control Register n
  348. #define PORTB_PCR30 (*(volatile uint32_t *)0x4004A078) // Pin Control Register n
  349. #define PORTB_PCR31 (*(volatile uint32_t *)0x4004A07C) // Pin Control Register n
  350. #define PORTB_GPCLR (*(volatile uint32_t *)0x4004A080) // Global Pin Control Low Register
  351. #define PORTB_GPCHR (*(volatile uint32_t *)0x4004A084) // Global Pin Control High Register
  352. #define PORTB_ISFR (*(volatile uint32_t *)0x4004A0A0) // Interrupt Status Flag Register
  353. #define PORTC_PCR0 (*(volatile uint32_t *)0x4004B000) // Pin Control Register n
  354. #define PORTC_PCR1 (*(volatile uint32_t *)0x4004B004) // Pin Control Register n
  355. #define PORTC_PCR2 (*(volatile uint32_t *)0x4004B008) // Pin Control Register n
  356. #define PORTC_PCR3 (*(volatile uint32_t *)0x4004B00C) // Pin Control Register n
  357. #define PORTC_PCR4 (*(volatile uint32_t *)0x4004B010) // Pin Control Register n
  358. #define PORTC_PCR5 (*(volatile uint32_t *)0x4004B014) // Pin Control Register n
  359. #define PORTC_PCR6 (*(volatile uint32_t *)0x4004B018) // Pin Control Register n
  360. #define PORTC_PCR7 (*(volatile uint32_t *)0x4004B01C) // Pin Control Register n
  361. #define PORTC_PCR8 (*(volatile uint32_t *)0x4004B020) // Pin Control Register n
  362. #define PORTC_PCR9 (*(volatile uint32_t *)0x4004B024) // Pin Control Register n
  363. #define PORTC_PCR10 (*(volatile uint32_t *)0x4004B028) // Pin Control Register n
  364. #define PORTC_PCR11 (*(volatile uint32_t *)0x4004B02C) // Pin Control Register n
  365. #define PORTC_PCR12 (*(volatile uint32_t *)0x4004B030) // Pin Control Register n
  366. #define PORTC_PCR13 (*(volatile uint32_t *)0x4004B034) // Pin Control Register n
  367. #define PORTC_PCR14 (*(volatile uint32_t *)0x4004B038) // Pin Control Register n
  368. #define PORTC_PCR15 (*(volatile uint32_t *)0x4004B03C) // Pin Control Register n
  369. #define PORTC_PCR16 (*(volatile uint32_t *)0x4004B040) // Pin Control Register n
  370. #define PORTC_PCR17 (*(volatile uint32_t *)0x4004B044) // Pin Control Register n
  371. #define PORTC_PCR18 (*(volatile uint32_t *)0x4004B048) // Pin Control Register n
  372. #define PORTC_PCR19 (*(volatile uint32_t *)0x4004B04C) // Pin Control Register n
  373. #define PORTC_PCR20 (*(volatile uint32_t *)0x4004B050) // Pin Control Register n
  374. #define PORTC_PCR21 (*(volatile uint32_t *)0x4004B054) // Pin Control Register n
  375. #define PORTC_PCR22 (*(volatile uint32_t *)0x4004B058) // Pin Control Register n
  376. #define PORTC_PCR23 (*(volatile uint32_t *)0x4004B05C) // Pin Control Register n
  377. #define PORTC_PCR24 (*(volatile uint32_t *)0x4004B060) // Pin Control Register n
  378. #define PORTC_PCR25 (*(volatile uint32_t *)0x4004B064) // Pin Control Register n
  379. #define PORTC_PCR26 (*(volatile uint32_t *)0x4004B068) // Pin Control Register n
  380. #define PORTC_PCR27 (*(volatile uint32_t *)0x4004B06C) // Pin Control Register n
  381. #define PORTC_PCR28 (*(volatile uint32_t *)0x4004B070) // Pin Control Register n
  382. #define PORTC_PCR29 (*(volatile uint32_t *)0x4004B074) // Pin Control Register n
  383. #define PORTC_PCR30 (*(volatile uint32_t *)0x4004B078) // Pin Control Register n
  384. #define PORTC_PCR31 (*(volatile uint32_t *)0x4004B07C) // Pin Control Register n
  385. #define PORTC_GPCLR (*(volatile uint32_t *)0x4004B080) // Global Pin Control Low Register
  386. #define PORTC_GPCHR (*(volatile uint32_t *)0x4004B084) // Global Pin Control High Register
  387. #define PORTC_ISFR (*(volatile uint32_t *)0x4004B0A0) // Interrupt Status Flag Register
  388. #define PORTD_PCR0 (*(volatile uint32_t *)0x4004C000) // Pin Control Register n
  389. #define PORTD_PCR1 (*(volatile uint32_t *)0x4004C004) // Pin Control Register n
  390. #define PORTD_PCR2 (*(volatile uint32_t *)0x4004C008) // Pin Control Register n
  391. #define PORTD_PCR3 (*(volatile uint32_t *)0x4004C00C) // Pin Control Register n
  392. #define PORTD_PCR4 (*(volatile uint32_t *)0x4004C010) // Pin Control Register n
  393. #define PORTD_PCR5 (*(volatile uint32_t *)0x4004C014) // Pin Control Register n
  394. #define PORTD_PCR6 (*(volatile uint32_t *)0x4004C018) // Pin Control Register n
  395. #define PORTD_PCR7 (*(volatile uint32_t *)0x4004C01C) // Pin Control Register n
  396. #define PORTD_PCR8 (*(volatile uint32_t *)0x4004C020) // Pin Control Register n
  397. #define PORTD_PCR9 (*(volatile uint32_t *)0x4004C024) // Pin Control Register n
  398. #define PORTD_PCR10 (*(volatile uint32_t *)0x4004C028) // Pin Control Register n
  399. #define PORTD_PCR11 (*(volatile uint32_t *)0x4004C02C) // Pin Control Register n
  400. #define PORTD_PCR12 (*(volatile uint32_t *)0x4004C030) // Pin Control Register n
  401. #define PORTD_PCR13 (*(volatile uint32_t *)0x4004C034) // Pin Control Register n
  402. #define PORTD_PCR14 (*(volatile uint32_t *)0x4004C038) // Pin Control Register n
  403. #define PORTD_PCR15 (*(volatile uint32_t *)0x4004C03C) // Pin Control Register n
  404. #define PORTD_PCR16 (*(volatile uint32_t *)0x4004C040) // Pin Control Register n
  405. #define PORTD_PCR17 (*(volatile uint32_t *)0x4004C044) // Pin Control Register n
  406. #define PORTD_PCR18 (*(volatile uint32_t *)0x4004C048) // Pin Control Register n
  407. #define PORTD_PCR19 (*(volatile uint32_t *)0x4004C04C) // Pin Control Register n
  408. #define PORTD_PCR20 (*(volatile uint32_t *)0x4004C050) // Pin Control Register n
  409. #define PORTD_PCR21 (*(volatile uint32_t *)0x4004C054) // Pin Control Register n
  410. #define PORTD_PCR22 (*(volatile uint32_t *)0x4004C058) // Pin Control Register n
  411. #define PORTD_PCR23 (*(volatile uint32_t *)0x4004C05C) // Pin Control Register n
  412. #define PORTD_PCR24 (*(volatile uint32_t *)0x4004C060) // Pin Control Register n
  413. #define PORTD_PCR25 (*(volatile uint32_t *)0x4004C064) // Pin Control Register n
  414. #define PORTD_PCR26 (*(volatile uint32_t *)0x4004C068) // Pin Control Register n
  415. #define PORTD_PCR27 (*(volatile uint32_t *)0x4004C06C) // Pin Control Register n
  416. #define PORTD_PCR28 (*(volatile uint32_t *)0x4004C070) // Pin Control Register n
  417. #define PORTD_PCR29 (*(volatile uint32_t *)0x4004C074) // Pin Control Register n
  418. #define PORTD_PCR30 (*(volatile uint32_t *)0x4004C078) // Pin Control Register n
  419. #define PORTD_PCR31 (*(volatile uint32_t *)0x4004C07C) // Pin Control Register n
  420. #define PORTD_GPCLR (*(volatile uint32_t *)0x4004C080) // Global Pin Control Low Register
  421. #define PORTD_GPCHR (*(volatile uint32_t *)0x4004C084) // Global Pin Control High Register
  422. #define PORTD_ISFR (*(volatile uint32_t *)0x4004C0A0) // Interrupt Status Flag Register
  423. #define PORTE_PCR0 (*(volatile uint32_t *)0x4004D000) // Pin Control Register n
  424. #define PORTE_PCR1 (*(volatile uint32_t *)0x4004D004) // Pin Control Register n
  425. #define PORTE_PCR2 (*(volatile uint32_t *)0x4004D008) // Pin Control Register n
  426. #define PORTE_PCR3 (*(volatile uint32_t *)0x4004D00C) // Pin Control Register n
  427. #define PORTE_PCR4 (*(volatile uint32_t *)0x4004D010) // Pin Control Register n
  428. #define PORTE_PCR5 (*(volatile uint32_t *)0x4004D014) // Pin Control Register n
  429. #define PORTE_PCR6 (*(volatile uint32_t *)0x4004D018) // Pin Control Register n
  430. #define PORTE_PCR7 (*(volatile uint32_t *)0x4004D01C) // Pin Control Register n
  431. #define PORTE_PCR8 (*(volatile uint32_t *)0x4004D020) // Pin Control Register n
  432. #define PORTE_PCR9 (*(volatile uint32_t *)0x4004D024) // Pin Control Register n
  433. #define PORTE_PCR10 (*(volatile uint32_t *)0x4004D028) // Pin Control Register n
  434. #define PORTE_PCR11 (*(volatile uint32_t *)0x4004D02C) // Pin Control Register n
  435. #define PORTE_PCR12 (*(volatile uint32_t *)0x4004D030) // Pin Control Register n
  436. #define PORTE_PCR13 (*(volatile uint32_t *)0x4004D034) // Pin Control Register n
  437. #define PORTE_PCR14 (*(volatile uint32_t *)0x4004D038) // Pin Control Register n
  438. #define PORTE_PCR15 (*(volatile uint32_t *)0x4004D03C) // Pin Control Register n
  439. #define PORTE_PCR16 (*(volatile uint32_t *)0x4004D040) // Pin Control Register n
  440. #define PORTE_PCR17 (*(volatile uint32_t *)0x4004D044) // Pin Control Register n
  441. #define PORTE_PCR18 (*(volatile uint32_t *)0x4004D048) // Pin Control Register n
  442. #define PORTE_PCR19 (*(volatile uint32_t *)0x4004D04C) // Pin Control Register n
  443. #define PORTE_PCR20 (*(volatile uint32_t *)0x4004D050) // Pin Control Register n
  444. #define PORTE_PCR21 (*(volatile uint32_t *)0x4004D054) // Pin Control Register n
  445. #define PORTE_PCR22 (*(volatile uint32_t *)0x4004D058) // Pin Control Register n
  446. #define PORTE_PCR23 (*(volatile uint32_t *)0x4004D05C) // Pin Control Register n
  447. #define PORTE_PCR24 (*(volatile uint32_t *)0x4004D060) // Pin Control Register n
  448. #define PORTE_PCR25 (*(volatile uint32_t *)0x4004D064) // Pin Control Register n
  449. #define PORTE_PCR26 (*(volatile uint32_t *)0x4004D068) // Pin Control Register n
  450. #define PORTE_PCR27 (*(volatile uint32_t *)0x4004D06C) // Pin Control Register n
  451. #define PORTE_PCR28 (*(volatile uint32_t *)0x4004D070) // Pin Control Register n
  452. #define PORTE_PCR29 (*(volatile uint32_t *)0x4004D074) // Pin Control Register n
  453. #define PORTE_PCR30 (*(volatile uint32_t *)0x4004D078) // Pin Control Register n
  454. #define PORTE_PCR31 (*(volatile uint32_t *)0x4004D07C) // Pin Control Register n
  455. #define PORTE_GPCLR (*(volatile uint32_t *)0x4004D080) // Global Pin Control Low Register
  456. #define PORTE_GPCHR (*(volatile uint32_t *)0x4004D084) // Global Pin Control High Register
  457. #define PORTE_ISFR (*(volatile uint32_t *)0x4004D0A0) // Interrupt Status Flag Register
  458. // Chapter 12: System Integration Module (SIM)
  459. #define SIM_SOPT1 (*(volatile uint32_t *)0x40047000) // System Options Register 1
  460. #define SIM_SOPT1CFG (*(volatile uint32_t *)0x40047004) // SOPT1 Configuration Register
  461. #define SIM_SOPT2 (*(volatile uint32_t *)0x40048004) // System Options Register 2
  462. #define SIM_SOPT2_UART0SRC(n) (uint32_t)(((n) & 3) << 26) // UART0 Clock Source, 0=off, 1=FLL/PLL, 2=OSCERCLK, 3=MCGIRCLK
  463. #define SIM_SOPT2_TPMSRC(n) (uint32_t)(((n) & 3) << 24) // TPM Clock Source, 0=off, 1=FLL/PLL, 2=OSCERCLK, 3=MCGIRCLK
  464. #define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) // 0=USB_CLKIN, 1=FFL/PLL
  465. #define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) // 0=FLL, 1=PLL
  466. #define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) // 0=MCGOUTCLK, 1=CPU
  467. #define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) // 0=normal, 1=double drive PTD7
  468. #define SIM_SOPT2_CLKOUTSEL(n) ((uint32_t)(((n) & 7) << 5)) // Selects the clock to output on the CLKOUT pin.
  469. #define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) // RTC clock out select
  470. #define SIM_SOPT4 (*(volatile uint32_t *)0x4004800C) // System Options Register 4
  471. #define SIM_SOPT5 (*(volatile uint32_t *)0x40048010) // System Options Register 5
  472. #define SIM_SOPT7 (*(volatile uint32_t *)0x40048018) // System Options Register 7
  473. #define SIM_SDID (*(const uint32_t *)0x40048024) // System Device Identification Register
  474. #define SIM_SCGC2 (*(volatile uint32_t *)0x4004802C) // System Clock Gating Control Register 2
  475. #define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) // DAC0 Clock Gate Control
  476. #define SIM_SCGC3 (*(volatile uint32_t *)0x40048030) // System Clock Gating Control Register 3
  477. #define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) // ADC1 Clock Gate Control
  478. #define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) // FTM2 Clock Gate Control
  479. #define SIM_SCGC4 (*(volatile uint32_t *)0x40048034) // System Clock Gating Control Register 4
  480. #define SIM_SCGC4_VREF ((uint32_t)0x00100000) // VREF Clock Gate Control
  481. #define SIM_SCGC4_CMP ((uint32_t)0x00080000) // Comparator Clock Gate Control
  482. #define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) // USB Clock Gate Control
  483. #define SIM_SCGC4_UART2 ((uint32_t)0x00001000) // UART2 Clock Gate Control
  484. #define SIM_SCGC4_UART1 ((uint32_t)0x00000800) // UART1 Clock Gate Control
  485. #define SIM_SCGC4_UART0 ((uint32_t)0x00000400) // UART0 Clock Gate Control
  486. #define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) // I2C1 Clock Gate Control
  487. #define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) // I2C0 Clock Gate Control
  488. #define SIM_SCGC4_CMT ((uint32_t)0x00000004) // CMT Clock Gate Control
  489. #define SIM_SCGC4_EWM ((uint32_t)0x00000002) // EWM Clock Gate Control
  490. #ifdef KINETISL
  491. #define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) //
  492. #define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) //
  493. #endif
  494. #define SIM_SCGC5 (*(volatile uint32_t *)0x40048038) // System Clock Gating Control Register 5
  495. #define SIM_SCGC5_PORTE ((uint32_t)0x00002000) // Port E Clock Gate Control
  496. #define SIM_SCGC5_PORTD ((uint32_t)0x00001000) // Port D Clock Gate Control
  497. #define SIM_SCGC5_PORTC ((uint32_t)0x00000800) // Port C Clock Gate Control
  498. #define SIM_SCGC5_PORTB ((uint32_t)0x00000400) // Port B Clock Gate Control
  499. #define SIM_SCGC5_PORTA ((uint32_t)0x00000200) // Port A Clock Gate Control
  500. #define SIM_SCGC5_TSI ((uint32_t)0x00000020) // Touch Sense Input TSI Clock Gate Control
  501. #define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) // Low Power Timer Access Control
  502. #define SIM_SCGC6 (*(volatile uint32_t *)0x4004803C) // System Clock Gating Control Register 6
  503. #define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) // DAC on Kinetis-L
  504. #define SIM_SCGC6_RTC ((uint32_t)0x20000000) // RTC Access
  505. #define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) // ADC0 Clock Gate Control
  506. #define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) // FTM1 Clock Gate Control
  507. #define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) // FTM0 Clock Gate Control
  508. #define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) // FTM1 Clock Gate Control
  509. #define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) // FTM1 Clock Gate Control
  510. #define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) // FTM0 Clock Gate Control
  511. #define SIM_SCGC6_PIT ((uint32_t)0x00800000) // PIT Clock Gate Control
  512. #define SIM_SCGC6_PDB ((uint32_t)0x00400000) // PDB Clock Gate Control
  513. #define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) // USB DCD Clock Gate Control
  514. #define SIM_SCGC6_CRC ((uint32_t)0x00040000) // CRC Clock Gate Control
  515. #define SIM_SCGC6_I2S ((uint32_t)0x00008000) // I2S Clock Gate Control
  516. #ifdef KINETISK
  517. #define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) // SPI1 Clock Gate Control
  518. #define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) // SPI0 Clock Gate Control
  519. #endif
  520. #define SIM_SCGC6_FLEXCAN0 ((uint32_t)0x00000010) // FlexCAN0 Clock Gate Control
  521. #define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) // DMA Mux Clock Gate Control
  522. #define SIM_SCGC6_FTFL ((uint32_t)0x00000001) // Flash Memory Clock Gate Control
  523. #define SIM_SCGC7 (*(volatile uint32_t *)0x40048040) // System Clock Gating Control Register 7
  524. #if defined(KINETISK)
  525. #define SIM_SCGC7_DMA ((uint32_t)0x00000002) // DMA Clock Gate Control
  526. #elif defined(KINETISL)
  527. #define SIM_SCGC7_DMA ((uint32_t)0x00000100) // DMA Clock Gate Control
  528. #endif
  529. #define SIM_CLKDIV1 (*(volatile uint32_t *)0x40048044) // System Clock Divider Register 1
  530. #define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)(((n) & 0x0F) << 28)) // divide value for the core/system clock
  531. #define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)(((n) & 0x0F) << 24)) // divide value for the peripheral clock
  532. #define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)(((n) & 0x0F) << 16)) // divide value for the flash clock
  533. #define SIM_CLKDIV2 (*(volatile uint32_t *)0x40048048) // System Clock Divider Register 2
  534. #define SIM_CLKDIV2_USBDIV(n) ((uint32_t)(((n) & 0x07) << 1))
  535. #define SIM_CLKDIV2_USBFRAC ((uint32_t)0x01)
  536. #define SIM_FCFG1 (*(const uint32_t *)0x4004804C) // Flash Configuration Register 1
  537. #define SIM_FCFG2 (*(const uint32_t *)0x40048050) // Flash Configuration Register 2
  538. #define SIM_UIDH (*(const uint32_t *)0x40048054) // Unique Identification Register High
  539. #define SIM_UIDMH (*(const uint32_t *)0x40048058) // Unique Identification Register Mid-High
  540. #define SIM_UIDML (*(const uint32_t *)0x4004805C) // Unique Identification Register Mid Low
  541. #define SIM_UIDL (*(const uint32_t *)0x40048060) // Unique Identification Register Low
  542. #define SIM_COPC (*(volatile uint32_t *)0x40048100) // COP Control Register (SIM_COPC)
  543. #define SIM_SRVCOP (*(volatile uint32_t *)0x40048104) // Service COP Register (SIM_SRVCOP)
  544. // Chapter 13: Reset Control Module (RCM)
  545. #define RCM_SRS0 (*(volatile uint8_t *)0x4007F000) // System Reset Status Register 0
  546. #define RCM_SRS0_POR ((uint8_t)0x80)
  547. #define RCM_SRS0_PIN ((uint8_t)0x40)
  548. #define RCM_SRS0_WDOG ((uint8_t)0x20)
  549. #define RCM_SRS0_LOL ((uint8_t)0x08)
  550. #define RCM_SRS0_LOC ((uint8_t)0x04)
  551. #define RCM_SRS0_LVD ((uint8_t)0x02)
  552. #define RCM_SRS0_WAKEUP ((uint8_t)0x01)
  553. #define RCM_SRS1 (*(volatile uint8_t *)0x4007F001) // System Reset Status Register 1
  554. #define RCM_SRS1_SACKERR ((uint8_t)0x20)
  555. #define RCM_SRS1_EZPT ((uint8_t)0x10)
  556. #define RCM_SRS1_MDM_AP ((uint8_t)0x08)
  557. #define RCM_SRS1_SW ((uint8_t)0x04)
  558. #define RCM_SRS1_LOCKUP ((uint8_t)0x02)
  559. #define RCM_SRS1_JTAG ((uint8_t)0x01)
  560. #define RCM_RPFC (*(volatile uint8_t *)0x4007F004) // Reset Pin Filter Control Register
  561. #define RCM_RPFW (*(volatile uint8_t *)0x4007F005) // Reset Pin Filter Width Register
  562. #define RCM_MR (*(volatile uint8_t *)0x4007F007) // Mode Register
  563. // Chapter 14: System Mode Controller
  564. #define SMC_PMPROT (*(volatile uint8_t *)0x4007E000) // Power Mode Protection Register
  565. #define SMC_PMPROT_AVLP ((uint8_t)0x20) // Allow very low power modes
  566. #define SMC_PMPROT_ALLS ((uint8_t)0x08) // Allow low leakage stop mode
  567. #define SMC_PMPROT_AVLLS ((uint8_t)0x02) // Allow very low leakage stop mode
  568. #define SMC_PMCTRL (*(volatile uint8_t *)0x4007E001) // Power Mode Control Register
  569. #define SMC_PMCTRL_LPWUI ((uint8_t)0x80) // Low Power Wake Up on Interrupt
  570. #define SMC_PMCTRL_RUNM(n) ((uint8_t)(((n) & 0x03) << 5)) // Run Mode Control
  571. #define SMC_PMCTRL_STOPA ((uint8_t)0x08) // Stop Aborted
  572. #define SMC_PMCTRL_STOPM(n) ((uint8_t)((n) & 0x07)) // Stop Mode Control
  573. #define SMC_VLLSCTRL (*(volatile uint8_t *)0x4007E002) // VLLS Control Register
  574. #define SMC_VLLSCTRL_PORPO ((uint8_t)0x20) // POR Power Option
  575. #define SMC_VLLSCTRL_VLLSM(n) ((uint8_t)((n) & 0x07)) // VLLS Mode Control
  576. #define SMC_PMSTAT (*(volatile uint8_t *)0x4007E003) // Power Mode Status Register
  577. #define SMC_PMSTAT_RUN ((uint8_t)0x01) // Current power mode is RUN
  578. #define SMC_PMSTAT_STOP ((uint8_t)0x02) // Current power mode is STOP
  579. #define SMC_PMSTAT_VLPR ((uint8_t)0x04) // Current power mode is VLPR
  580. #define SMC_PMSTAT_VLPW ((uint8_t)0x08) // Current power mode is VLPW
  581. #define SMC_PMSTAT_VLPS ((uint8_t)0x10) // Current power mode is VLPS
  582. #define SMC_PMSTAT_LLS ((uint8_t)0x20) // Current power mode is LLS
  583. #define SMC_PMSTAT_VLLS ((uint8_t)0x40) // Current power mode is VLLS
  584. // Chapter 15: Power Management Controller
  585. #define PMC_LVDSC1 (*(volatile uint8_t *)0x4007D000) // Low Voltage Detect Status And Control 1 register
  586. #define PMC_LVDSC1_LVDF ((uint8_t)0x80) // Low-Voltage Detect Flag
  587. #define PMC_LVDSC1_LVDACK ((uint8_t)0x40) // Low-Voltage Detect Acknowledge
  588. #define PMC_LVDSC1_LVDIE ((uint8_t)0x20) // Low-Voltage Detect Interrupt Enable
  589. #define PMC_LVDSC1_LVDRE ((uint8_t)0x10) // Low-Voltage Detect Reset Enable
  590. #define PMC_LVDSC1_LVDV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Detect Voltage Select
  591. #define PMC_LVDSC2 (*(volatile uint8_t *)0x4007D001) // Low Voltage Detect Status And Control 2 register
  592. #define PMC_LVDSC2_LVWF ((uint8_t)0x80) // Low-Voltage Warning Flag
  593. #define PMC_LVDSC2_LVWACK ((uint8_t)0x40) // Low-Voltage Warning Acknowledge
  594. #define PMC_LVDSC2_LVWIE ((uint8_t)0x20) // Low-Voltage Warning Interrupt Enable
  595. #define PMC_LVDSC2_LVWV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Warning Voltage Select
  596. #define PMC_REGSC (*(volatile uint8_t *)0x4007D002) // Regulator Status And Control register
  597. #define PMC_REGSC_BGEN ((uint8_t)0x10) // Bandgap Enable In VLPx Operation
  598. #define PMC_REGSC_ACKISO ((uint8_t)0x08) // Acknowledge Isolation
  599. #define PMC_REGSC_REGONS ((uint8_t)0x04) // Regulator In Run Regulation Status
  600. #define PMC_REGSC_BGBE ((uint8_t)0x01) // Bandgap Buffer Enable
  601. // Chapter 16: Low-Leakage Wakeup Unit (LLWU)
  602. #define LLWU_PE1 (*(volatile uint8_t *)0x4007C000) // LLWU Pin Enable 1 register
  603. #define LLWU_PE2 (*(volatile uint8_t *)0x4007C001) // LLWU Pin Enable 2 register
  604. #define LLWU_PE3 (*(volatile uint8_t *)0x4007C002) // LLWU Pin Enable 3 register
  605. #define LLWU_PE4 (*(volatile uint8_t *)0x4007C003) // LLWU Pin Enable 4 register
  606. #define LLWU_ME (*(volatile uint8_t *)0x4007C004) // LLWU Module Enable register
  607. #define LLWU_F1 (*(volatile uint8_t *)0x4007C005) // LLWU Flag 1 register
  608. #define LLWU_F2 (*(volatile uint8_t *)0x4007C006) // LLWU Flag 2 register
  609. #define LLWU_F3 (*(volatile uint8_t *)0x4007C007) // LLWU Flag 3 register
  610. #define LLWU_FILT1 (*(volatile uint8_t *)0x4007C008) // LLWU Pin Filter 1 register
  611. #define LLWU_FILT2 (*(volatile uint8_t *)0x4007C009) // LLWU Pin Filter 2 register
  612. #define LLWU_RST (*(volatile uint8_t *)0x4007C00A) // LLWU Reset Enable register
  613. // Chapter 17: Miscellaneous Control Module (MCM)
  614. #if defined(KINETISK)
  615. #define MCM_PLASC (*(volatile uint16_t *)0xE0080008) // Crossbar Switch (AXBS) Slave Configuration
  616. #define MCM_PLAMC (*(volatile uint16_t *)0xE008000A) // Crossbar Switch (AXBS) Master Configuration
  617. #define MCM_PLACR (*(volatile uint32_t *)0xE008000C) // Crossbar Switch (AXBS) Control Register (MK20DX128)
  618. #define MCM_PLACR_ARG ((uint32_t)0x00000200) // Arbitration select, 0=fixed, 1=round-robin
  619. #define MCM_CR (*(volatile uint32_t *)0xE008000C) // RAM arbitration control register (MK20DX256)
  620. #define MCM_CR_SRAMLWP ((uint32_t)0x40000000) // SRAM_L write protect
  621. #define MCM_CR_SRAMLAP(n) ((uint32_t)(((n) & 0x03) << 28)) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
  622. #define MCM_CR_SRAMUWP ((uint32_t)0x04000000) // SRAM_U write protect
  623. #define MCM_CR_SRAMUAP(n) ((uint32_t)(((n) & 0x03) << 24)) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
  624. #elif defined(KINETISL)
  625. #define MCM_PLASC (*(volatile uint16_t *)0xF0003008) // Crossbar Switch (AXBS) Slave Configuration
  626. #define MCM_PLAMC (*(volatile uint16_t *)0xF000300A) // Crossbar Switch (AXBS) Master Configuration
  627. #define MCM_PLACR (*(volatile uint32_t *)0xF000300C) // Platform Control Register
  628. #define MCM_PLACR_ESFC ((uint32_t)0x00010000) // Enable Stalling Flash Controller
  629. #define MCM_PLACR_DFCS ((uint32_t)0x00008000) // Disable Flash Controller Speculation
  630. #define MCM_PLACR_EFDS ((uint32_t)0x00004000) // Enable Flash Data Speculation
  631. #define MCM_PLACR_DFCC ((uint32_t)0x00002000) // Disable Flash Controller Cache
  632. #define MCM_PLACR_DFCIC ((uint32_t)0x00001000) // Disable Flash Controller Instruction Caching
  633. #define MCM_PLACR_DFCDA ((uint32_t)0x00000800) // Disable Flash Controller Data Caching
  634. #define MCM_PLACR_CFCC ((uint32_t)0x00000400) // Clear Flash Controller Cache
  635. #define MCM_PLACR_ARB ((uint32_t)0x00000200) // Arbitration select
  636. #define MCM_CPO (*(volatile uint32_t *)0xF0003040) // Compute Operation Control Register
  637. #endif
  638. // Crossbar Switch (AXBS) - only programmable on MK20DX256
  639. #define AXBS_PRS0 (*(volatile uint32_t *)0x40004000) // Priority Registers Slave 0
  640. #define AXBS_CRS0 (*(volatile uint32_t *)0x40004010) // Control Register 0
  641. #define AXBS_PRS1 (*(volatile uint32_t *)0x40004100) // Priority Registers Slave 1
  642. #define AXBS_CRS1 (*(volatile uint32_t *)0x40004110) // Control Register 1
  643. #define AXBS_PRS2 (*(volatile uint32_t *)0x40004200) // Priority Registers Slave 2
  644. #define AXBS_CRS2 (*(volatile uint32_t *)0x40004210) // Control Register 2
  645. #define AXBS_PRS3 (*(volatile uint32_t *)0x40004300) // Priority Registers Slave 3
  646. #define AXBS_CRS3 (*(volatile uint32_t *)0x40004310) // Control Register 3
  647. #define AXBS_PRS4 (*(volatile uint32_t *)0x40004400) // Priority Registers Slave 4
  648. #define AXBS_CRS4 (*(volatile uint32_t *)0x40004410) // Control Register 4
  649. #define AXBS_PRS5 (*(volatile uint32_t *)0x40004500) // Priority Registers Slave 5
  650. #define AXBS_CRS5 (*(volatile uint32_t *)0x40004510) // Control Register 5
  651. #define AXBS_PRS6 (*(volatile uint32_t *)0x40004600) // Priority Registers Slave 6
  652. #define AXBS_CRS6 (*(volatile uint32_t *)0x40004610) // Control Register 6
  653. #define AXBS_PRS7 (*(volatile uint32_t *)0x40004700) // Priority Registers Slave 7
  654. #define AXBS_CRS7 (*(volatile uint32_t *)0x40004710) // Control Register 7
  655. #define AXBS_MGPCR0 (*(volatile uint32_t *)0x40004800) // Master 0 General Purpose Control Register
  656. #define AXBS_MGPCR1 (*(volatile uint32_t *)0x40004900) // Master 1 General Purpose Control Register
  657. #define AXBS_MGPCR2 (*(volatile uint32_t *)0x40004A00) // Master 2 General Purpose Control Register
  658. #define AXBS_MGPCR3 (*(volatile uint32_t *)0x40004B00) // Master 3 General Purpose Control Register
  659. #define AXBS_MGPCR4 (*(volatile uint32_t *)0x40004C00) // Master 4 General Purpose Control Register
  660. #define AXBS_MGPCR5 (*(volatile uint32_t *)0x40004D00) // Master 5 General Purpose Control Register
  661. #define AXBS_MGPCR6 (*(volatile uint32_t *)0x40004E00) // Master 6 General Purpose Control Register
  662. #define AXBS_MGPCR7 (*(volatile uint32_t *)0x40004F00) // Master 7 General Purpose Control Register
  663. #define AXBS_CRS_READONLY ((uint32_t)0x80000000)
  664. #define AXBS_CRS_HALTLOWPRIORITY ((uint32_t)0x40000000)
  665. #define AXBS_CRS_ARB_FIXED ((uint32_t)0x00000000)
  666. #define AXBS_CRS_ARB_ROUNDROBIN ((uint32_t)0x00010000)
  667. #define AXBS_CRS_PARK_FIXED ((uint32_t)0x00000000)
  668. #define AXBS_CRS_PARK_PREVIOUS ((uint32_t)0x00000010)
  669. #define AXBS_CRS_PARK_NONE ((uint32_t)0x00000020)
  670. #define AXBS_CRS_PARK(n) ((uint32_t)(((n) & 7) << 0))
  671. // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
  672. #define DMAMUX0_CHCFG0 (*(volatile uint8_t *)0x40021000) // Channel Configuration register
  673. #define DMAMUX0_CHCFG1 (*(volatile uint8_t *)0x40021001) // Channel Configuration register
  674. #define DMAMUX0_CHCFG2 (*(volatile uint8_t *)0x40021002) // Channel Configuration register
  675. #define DMAMUX0_CHCFG3 (*(volatile uint8_t *)0x40021003) // Channel Configuration register
  676. #define DMAMUX0_CHCFG4 (*(volatile uint8_t *)0x40021004) // Channel Configuration register
  677. #define DMAMUX0_CHCFG5 (*(volatile uint8_t *)0x40021005) // Channel Configuration register
  678. #define DMAMUX0_CHCFG6 (*(volatile uint8_t *)0x40021006) // Channel Configuration register
  679. #define DMAMUX0_CHCFG7 (*(volatile uint8_t *)0x40021007) // Channel Configuration register
  680. #define DMAMUX0_CHCFG8 (*(volatile uint8_t *)0x40021008) // Channel Configuration register
  681. #define DMAMUX0_CHCFG9 (*(volatile uint8_t *)0x40021009) // Channel Configuration register
  682. #define DMAMUX0_CHCFG10 (*(volatile uint8_t *)0x4002100A) // Channel Configuration register
  683. #define DMAMUX0_CHCFG11 (*(volatile uint8_t *)0x4002100B) // Channel Configuration register
  684. #define DMAMUX0_CHCFG12 (*(volatile uint8_t *)0x4002100C) // Channel Configuration register
  685. #define DMAMUX0_CHCFG13 (*(volatile uint8_t *)0x4002100D) // Channel Configuration register
  686. #define DMAMUX0_CHCFG14 (*(volatile uint8_t *)0x4002100E) // Channel Configuration register
  687. #define DMAMUX0_CHCFG15 (*(volatile uint8_t *)0x4002100F) // Channel Configuration register
  688. #define DMAMUX_DISABLE 0
  689. #define DMAMUX_TRIG 64
  690. #define DMAMUX_ENABLE 128
  691. #define DMAMUX_SOURCE_UART0_RX 2
  692. #define DMAMUX_SOURCE_UART0_TX 3
  693. #define DMAMUX_SOURCE_UART1_RX 4
  694. #define DMAMUX_SOURCE_UART1_TX 5
  695. #define DMAMUX_SOURCE_UART2_RX 6
  696. #define DMAMUX_SOURCE_UART2_TX 7
  697. #define DMAMUX_SOURCE_I2S0_RX 14
  698. #define DMAMUX_SOURCE_I2S0_TX 15
  699. #define DMAMUX_SOURCE_SPI0_RX 16
  700. #define DMAMUX_SOURCE_SPI0_TX 17
  701. #define DMAMUX_SOURCE_SPI1_RX 18
  702. #define DMAMUX_SOURCE_SPI1_TX 19
  703. #define DMAMUX_SOURCE_I2C0 22
  704. #define DMAMUX_SOURCE_I2C1 23
  705. #define DMAMUX_SOURCE_FTM0_CH0 24
  706. #define DMAMUX_SOURCE_FTM0_CH1 25
  707. #define DMAMUX_SOURCE_FTM0_CH2 26
  708. #define DMAMUX_SOURCE_FTM0_CH3 27
  709. #define DMAMUX_SOURCE_FTM0_CH4 28
  710. #define DMAMUX_SOURCE_FTM0_CH5 29
  711. #define DMAMUX_SOURCE_FTM0_CH6 30
  712. #define DMAMUX_SOURCE_FTM0_CH7 31
  713. #define DMAMUX_SOURCE_FTM1_CH0 32
  714. #define DMAMUX_SOURCE_FTM1_CH1 33
  715. #define DMAMUX_SOURCE_FTM2_CH0 34
  716. #define DMAMUX_SOURCE_FTM2_CH1 35
  717. #define DMAMUX_SOURCE_ADC0 40
  718. #define DMAMUX_SOURCE_ADC1 41
  719. #define DMAMUX_SOURCE_CMP0 42
  720. #define DMAMUX_SOURCE_CMP1 43
  721. #define DMAMUX_SOURCE_CMP2 44
  722. #define DMAMUX_SOURCE_DAC0 45
  723. #define DMAMUX_SOURCE_CMT 47
  724. #define DMAMUX_SOURCE_PDB 48
  725. #define DMAMUX_SOURCE_PORTA 49
  726. #define DMAMUX_SOURCE_PORTB 50
  727. #define DMAMUX_SOURCE_PORTC 51
  728. #define DMAMUX_SOURCE_PORTD 52
  729. #define DMAMUX_SOURCE_PORTE 53
  730. #if defined(KINETISK)
  731. #define DMAMUX_SOURCE_ALWAYS0 54
  732. #define DMAMUX_SOURCE_ALWAYS1 55
  733. #define DMAMUX_SOURCE_ALWAYS2 56
  734. #define DMAMUX_SOURCE_ALWAYS3 57
  735. #define DMAMUX_SOURCE_ALWAYS4 58
  736. #define DMAMUX_SOURCE_ALWAYS5 59
  737. #define DMAMUX_SOURCE_ALWAYS6 60
  738. #define DMAMUX_SOURCE_ALWAYS7 61
  739. #define DMAMUX_SOURCE_ALWAYS8 62
  740. #define DMAMUX_SOURCE_ALWAYS9 63
  741. #define DMAMUX_NUM_SOURCE_ALWAYS 10
  742. #elif defined(KINETISL)
  743. #define DMAMUX_SOURCE_FTM0_OV 54
  744. #define DMAMUX_SOURCE_FTM1_OV 55
  745. #define DMAMUX_SOURCE_FTM2_OV 56
  746. #define DMAMUX_SOURCE_TSI 57
  747. #define DMAMUX_SOURCE_ALWAYS0 60
  748. #define DMAMUX_SOURCE_ALWAYS1 61
  749. #define DMAMUX_SOURCE_ALWAYS2 62
  750. #define DMAMUX_SOURCE_ALWAYS3 63
  751. #define DMAMUX_NUM_SOURCE_ALWAYS 4
  752. #endif
  753. // Chapter 21: Direct Memory Access Controller (eDMA)
  754. #if defined(KINETISK)
  755. #define DMA_CR (*(volatile uint32_t *)0x40008000) // Control Register
  756. #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
  757. #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
  758. #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
  759. #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
  760. #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
  761. #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
  762. #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
  763. #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
  764. #define DMA_ES (*(volatile uint32_t *)0x40008004) // Error Status Register
  765. #define DMA_ERQ (*(volatile uint32_t *)0x4000800C) // Enable Request Register
  766. #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
  767. #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
  768. #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
  769. #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
  770. #define DMA_ERQ_ERQ4 ((uint32_t)1<<4) // Enable DMA Request 4
  771. #define DMA_ERQ_ERQ5 ((uint32_t)1<<5) // Enable DMA Request 5
  772. #define DMA_ERQ_ERQ6 ((uint32_t)1<<6) // Enable DMA Request 6
  773. #define DMA_ERQ_ERQ7 ((uint32_t)1<<7) // Enable DMA Request 7
  774. #define DMA_ERQ_ERQ8 ((uint32_t)1<<8) // Enable DMA Request 8
  775. #define DMA_ERQ_ERQ9 ((uint32_t)1<<9) // Enable DMA Request 9
  776. #define DMA_ERQ_ERQ10 ((uint32_t)1<<10) // Enable DMA Request 10
  777. #define DMA_ERQ_ERQ11 ((uint32_t)1<<11) // Enable DMA Request 11
  778. #define DMA_ERQ_ERQ12 ((uint32_t)1<<12) // Enable DMA Request 12
  779. #define DMA_ERQ_ERQ13 ((uint32_t)1<<13) // Enable DMA Request 13
  780. #define DMA_ERQ_ERQ14 ((uint32_t)1<<14) // Enable DMA Request 14
  781. #define DMA_ERQ_ERQ15 ((uint32_t)1<<15) // Enable DMA Request 15
  782. #define DMA_EEI (*(volatile uint32_t *)0x40008014) // Enable Error Interrupt Register
  783. #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
  784. #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
  785. #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
  786. #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
  787. #define DMA_EEI_EEI4 ((uint32_t)1<<4) // Enable Error Interrupt 4
  788. #define DMA_EEI_EEI5 ((uint32_t)1<<5) // Enable Error Interrupt 5
  789. #define DMA_EEI_EEI6 ((uint32_t)1<<6) // Enable Error Interrupt 6
  790. #define DMA_EEI_EEI7 ((uint32_t)1<<7) // Enable Error Interrupt 7
  791. #define DMA_EEI_EEI8 ((uint32_t)1<<8) // Enable Error Interrupt 8
  792. #define DMA_EEI_EEI9 ((uint32_t)1<<9) // Enable Error Interrupt 9
  793. #define DMA_EEI_EEI10 ((uint32_t)1<<10) // Enable Error Interrupt 10
  794. #define DMA_EEI_EEI11 ((uint32_t)1<<11) // Enable Error Interrupt 11
  795. #define DMA_EEI_EEI12 ((uint32_t)1<<12) // Enable Error Interrupt 12
  796. #define DMA_EEI_EEI13 ((uint32_t)1<<13) // Enable Error Interrupt 13
  797. #define DMA_EEI_EEI14 ((uint32_t)1<<14) // Enable Error Interrupt 14
  798. #define DMA_EEI_EEI15 ((uint32_t)1<<15) // Enable Error Interrupt 15
  799. #define DMA_CEEI (*(volatile uint8_t *)0x40008018) // Clear Enable Error Interrupt Register
  800. #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 15)<<0) // Clear Enable Error Interrupt
  801. #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
  802. #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
  803. #define DMA_SEEI (*(volatile uint8_t *)0x40008019) // Set Enable Error Interrupt Register
  804. #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 15)<<0) // Set Enable Error Interrupt
  805. #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
  806. #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
  807. #define DMA_CERQ (*(volatile uint8_t *)0x4000801A) // Clear Enable Request Register
  808. #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 15)<<0) // Clear Enable Request
  809. #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
  810. #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
  811. #define DMA_SERQ (*(volatile uint8_t *)0x4000801B) // Set Enable Request Register
  812. #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 15)<<0) // Set Enable Request
  813. #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
  814. #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
  815. #define DMA_CDNE (*(volatile uint8_t *)0x4000801C) // Clear DONE Status Bit Register
  816. #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 15)<<0) // Clear Done Bit
  817. #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
  818. #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
  819. #define DMA_SSRT (*(volatile uint8_t *)0x4000801D) // Set START Bit Register
  820. #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 15)<<0) // Set Start Bit
  821. #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
  822. #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
  823. #define DMA_CERR (*(volatile uint8_t *)0x4000801E) // Clear Error Register
  824. #define DMA_CERR_CERR(n) ((uint8_t)(n & 15)<<0) // Clear Error Indicator
  825. #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
  826. #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
  827. #define DMA_CINT (*(volatile uint8_t *)0x4000801F) // Clear Interrupt Request Register
  828. #define DMA_CINT_CINT(n) ((uint8_t)(n & 15)<<0) // Clear Interrupt Request
  829. #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
  830. #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
  831. #define DMA_INT (*(volatile uint32_t *)0x40008024) // Interrupt Request Register
  832. #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
  833. #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
  834. #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
  835. #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
  836. #define DMA_INT_INT4 ((uint32_t)1<<4) // Interrupt Request 4
  837. #define DMA_INT_INT5 ((uint32_t)1<<5) // Interrupt Request 5
  838. #define DMA_INT_INT6 ((uint32_t)1<<6) // Interrupt Request 6
  839. #define DMA_INT_INT7 ((uint32_t)1<<7) // Interrupt Request 7
  840. #define DMA_INT_INT8 ((uint32_t)1<<8) // Interrupt Request 8
  841. #define DMA_INT_INT9 ((uint32_t)1<<9) // Interrupt Request 9
  842. #define DMA_INT_INT10 ((uint32_t)1<<10) // Interrupt Request 10
  843. #define DMA_INT_INT11 ((uint32_t)1<<11) // Interrupt Request 11
  844. #define DMA_INT_INT12 ((uint32_t)1<<12) // Interrupt Request 12
  845. #define DMA_INT_INT13 ((uint32_t)1<<13) // Interrupt Request 13
  846. #define DMA_INT_INT14 ((uint32_t)1<<14) // Interrupt Request 14
  847. #define DMA_INT_INT15 ((uint32_t)1<<15) // Interrupt Request 15
  848. #define DMA_ERR (*(volatile uint32_t *)0x4000802C) // Error Register
  849. #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
  850. #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
  851. #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
  852. #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
  853. #define DMA_ERR_ERR4 ((uint32_t)1<<4) // Error in Channel 4
  854. #define DMA_ERR_ERR5 ((uint32_t)1<<5) // Error in Channel 5
  855. #define DMA_ERR_ERR6 ((uint32_t)1<<6) // Error in Channel 6
  856. #define DMA_ERR_ERR7 ((uint32_t)1<<7) // Error in Channel 7
  857. #define DMA_ERR_ERR8 ((uint32_t)1<<8) // Error in Channel 8
  858. #define DMA_ERR_ERR9 ((uint32_t)1<<9) // Error in Channel 9
  859. #define DMA_ERR_ERR10 ((uint32_t)1<<10) // Error in Channel 10
  860. #define DMA_ERR_ERR11 ((uint32_t)1<<11) // Error in Channel 11
  861. #define DMA_ERR_ERR12 ((uint32_t)1<<12) // Error in Channel 12
  862. #define DMA_ERR_ERR13 ((uint32_t)1<<13) // Error in Channel 13
  863. #define DMA_ERR_ERR14 ((uint32_t)1<<14) // Error in Channel 14
  864. #define DMA_ERR_ERR15 ((uint32_t)1<<15) // Error in Channel 15
  865. #define DMA_HRS (*(volatile uint32_t *)0x40008034) // Hardware Request Status Register
  866. #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
  867. #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
  868. #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
  869. #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
  870. #define DMA_HRS_HRS4 ((uint32_t)1<<4) // Hardware Request Status Channel 4
  871. #define DMA_HRS_HRS5 ((uint32_t)1<<5) // Hardware Request Status Channel 5
  872. #define DMA_HRS_HRS6 ((uint32_t)1<<6) // Hardware Request Status Channel 6
  873. #define DMA_HRS_HRS7 ((uint32_t)1<<7) // Hardware Request Status Channel 7
  874. #define DMA_HRS_HRS8 ((uint32_t)1<<8) // Hardware Request Status Channel 8
  875. #define DMA_HRS_HRS9 ((uint32_t)1<<9) // Hardware Request Status Channel 9
  876. #define DMA_HRS_HRS10 ((uint32_t)1<<10) // Hardware Request Status Channel 10
  877. #define DMA_HRS_HRS11 ((uint32_t)1<<11) // Hardware Request Status Channel 11
  878. #define DMA_HRS_HRS12 ((uint32_t)1<<12) // Hardware Request Status Channel 12
  879. #define DMA_HRS_HRS13 ((uint32_t)1<<13) // Hardware Request Status Channel 13
  880. #define DMA_HRS_HRS14 ((uint32_t)1<<14) // Hardware Request Status Channel 14
  881. #define DMA_HRS_HRS15 ((uint32_t)1<<15) // Hardware Request Status Channel 15
  882. #define DMA_DCHPRI3 (*(volatile uint8_t *)0x40008100) // Channel n Priority Register
  883. #define DMA_DCHPRI2 (*(volatile uint8_t *)0x40008101) // Channel n Priority Register
  884. #define DMA_DCHPRI1 (*(volatile uint8_t *)0x40008102) // Channel n Priority Register
  885. #define DMA_DCHPRI0 (*(volatile uint8_t *)0x40008103) // Channel n Priority Register
  886. #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 15)<<0) // Channel Arbitration Priority
  887. #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
  888. #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
  889. #define DMA_DCHPRI7 (*(volatile uint8_t *)0x40008104) // Channel n Priority Register
  890. #define DMA_DCHPRI6 (*(volatile uint8_t *)0x40008105) // Channel n Priority Register
  891. #define DMA_DCHPRI5 (*(volatile uint8_t *)0x40008106) // Channel n Priority Register
  892. #define DMA_DCHPRI4 (*(volatile uint8_t *)0x40008107) // Channel n Priority Register
  893. #define DMA_DCHPRI11 (*(volatile uint8_t *)0x40008108) // Channel n Priority Register
  894. #define DMA_DCHPRI10 (*(volatile uint8_t *)0x40008109) // Channel n Priority Register
  895. #define DMA_DCHPRI9 (*(volatile uint8_t *)0x4000810A) // Channel n Priority Register
  896. #define DMA_DCHPRI8 (*(volatile uint8_t *)0x4000810B) // Channel n Priority Register
  897. #define DMA_DCHPRI15 (*(volatile uint8_t *)0x4000810C) // Channel n Priority Register
  898. #define DMA_DCHPRI14 (*(volatile uint8_t *)0x4000810D) // Channel n Priority Register
  899. #define DMA_DCHPRI13 (*(volatile uint8_t *)0x4000810E) // Channel n Priority Register
  900. #define DMA_DCHPRI12 (*(volatile uint8_t *)0x4000810F) // Channel n Priority Register
  901. #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
  902. #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
  903. #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
  904. #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
  905. #define DMA_TCD_ATTR_SIZE_8BIT 0
  906. #define DMA_TCD_ATTR_SIZE_16BIT 1
  907. #define DMA_TCD_ATTR_SIZE_32BIT 2
  908. #define DMA_TCD_ATTR_SIZE_16BYTE 4
  909. #define DMA_TCD_ATTR_SIZE_32BYTE 5 // caution: this might not be supported in newer chips?
  910. #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
  911. #define DMA_TCD_CSR_BWC_MASK 0xC000
  912. #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0xF) << 8)
  913. #define DMA_TCD_CSR_MAJORLINKCH_MASK 0x0F00
  914. #define DMA_TCD_CSR_DONE 0x0080
  915. #define DMA_TCD_CSR_ACTIVE 0x0040
  916. #define DMA_TCD_CSR_MAJORELINK 0x0020
  917. #define DMA_TCD_CSR_ESG 0x0010
  918. #define DMA_TCD_CSR_DREQ 0x0008
  919. #define DMA_TCD_CSR_INTHALF 0x0004
  920. #define DMA_TCD_CSR_INTMAJOR 0x0002
  921. #define DMA_TCD_CSR_START 0x0001
  922. #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
  923. #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
  924. #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
  925. #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
  926. #define DMA_TCD_BITER_ELINKYES_ELINK 0x8000
  927. #define DMA_TCD_BITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
  928. #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00
  929. #define DMA_TCD_BITER_ELINKYES_BITER(n) (((n) & 0x1FF) << 0)
  930. #define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x01FF
  931. #define DMA_TCD_CITER_ELINKYES_ELINK 0x8000
  932. #define DMA_TCD_CITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
  933. #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00
  934. #define DMA_TCD_CITER_ELINKYES_CITER(n) (((n) & 0x1FF) << 0)
  935. #define DMA_TCD_CITER_ELINKYES_CITER_MASK 0x01FF
  936. #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
  937. #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
  938. #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
  939. #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
  940. #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
  941. #define DMA_TCD0_SADDR (*(volatile const void * volatile *)0x40009000) // TCD Source Address
  942. #define DMA_TCD0_SOFF (*(volatile int16_t *)0x40009004) // TCD Signed Source Address Offset
  943. #define DMA_TCD0_ATTR (*(volatile uint16_t *)0x40009006) // TCD Transfer Attributes
  944. #define DMA_TCD0_NBYTES_MLNO (*(volatile uint32_t *)0x40009008) // TCD Minor Byte Count (Minor Loop Disabled)
  945. #define DMA_TCD0_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  946. #define DMA_TCD0_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  947. #define DMA_TCD0_SLAST (*(volatile int32_t *)0x4000900C) // TCD Last Source Address Adjustment
  948. #define DMA_TCD0_DADDR (*(volatile void * volatile *)0x40009010) // TCD Destination Address
  949. #define DMA_TCD0_DOFF (*(volatile int16_t *)0x40009014) // TCD Signed Destination Address Offset
  950. #define DMA_TCD0_CITER_ELINKYES (*(volatile uint16_t *)0x40009016) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  951. #define DMA_TCD0_CITER_ELINKNO (*(volatile uint16_t *)0x40009016) // ??
  952. #define DMA_TCD0_DLASTSGA (*(volatile int32_t *)0x40009018) // TCD Last Destination Address Adjustment/Scatter Gather Address
  953. #define DMA_TCD0_CSR (*(volatile uint16_t *)0x4000901C) // TCD Control and Status
  954. #define DMA_TCD0_BITER_ELINKYES (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
  955. #define DMA_TCD0_BITER_ELINKNO (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  956. #define DMA_TCD1_SADDR (*(volatile const void * volatile *)0x40009020) // TCD Source Address
  957. #define DMA_TCD1_SOFF (*(volatile int16_t *)0x40009024) // TCD Signed Source Address Offset
  958. #define DMA_TCD1_ATTR (*(volatile uint16_t *)0x40009026) // TCD Transfer Attributes
  959. #define DMA_TCD1_NBYTES_MLNO (*(volatile uint32_t *)0x40009028) // TCD Minor Byte Count, Minor Loop Disabled
  960. #define DMA_TCD1_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  961. #define DMA_TCD1_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  962. #define DMA_TCD1_SLAST (*(volatile int32_t *)0x4000902C) // TCD Last Source Address Adjustment
  963. #define DMA_TCD1_DADDR (*(volatile void * volatile *)0x40009030) // TCD Destination Address
  964. #define DMA_TCD1_DOFF (*(volatile int16_t *)0x40009034) // TCD Signed Destination Address Offset
  965. #define DMA_TCD1_CITER_ELINKYES (*(volatile uint16_t *)0x40009036) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  966. #define DMA_TCD1_CITER_ELINKNO (*(volatile uint16_t *)0x40009036) // ??
  967. #define DMA_TCD1_DLASTSGA (*(volatile int32_t *)0x40009038) // TCD Last Destination Address Adjustment/Scatter Gather Address
  968. #define DMA_TCD1_CSR (*(volatile uint16_t *)0x4000903C) // TCD Control and Status
  969. #define DMA_TCD1_BITER_ELINKYES (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
  970. #define DMA_TCD1_BITER_ELINKNO (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  971. #define DMA_TCD2_SADDR (*(volatile const void * volatile *)0x40009040) // TCD Source Address
  972. #define DMA_TCD2_SOFF (*(volatile int16_t *)0x40009044) // TCD Signed Source Address Offset
  973. #define DMA_TCD2_ATTR (*(volatile uint16_t *)0x40009046) // TCD Transfer Attributes
  974. #define DMA_TCD2_NBYTES_MLNO (*(volatile uint32_t *)0x40009048) // TCD Minor Byte Count, Minor Loop Disabled
  975. #define DMA_TCD2_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  976. #define DMA_TCD2_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  977. #define DMA_TCD2_SLAST (*(volatile int32_t *)0x4000904C) // TCD Last Source Address Adjustment
  978. #define DMA_TCD2_DADDR (*(volatile void * volatile *)0x40009050) // TCD Destination Address
  979. #define DMA_TCD2_DOFF (*(volatile int16_t *)0x40009054) // TCD Signed Destination Address Offset
  980. #define DMA_TCD2_CITER_ELINKYES (*(volatile uint16_t *)0x40009056) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  981. #define DMA_TCD2_CITER_ELINKNO (*(volatile uint16_t *)0x40009056) // ??
  982. #define DMA_TCD2_DLASTSGA (*(volatile int32_t *)0x40009058) // TCD Last Destination Address Adjustment/Scatter Gather Address
  983. #define DMA_TCD2_CSR (*(volatile uint16_t *)0x4000905C) // TCD Control and Status
  984. #define DMA_TCD2_BITER_ELINKYES (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
  985. #define DMA_TCD2_BITER_ELINKNO (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  986. #define DMA_TCD3_SADDR (*(volatile const void * volatile *)0x40009060) // TCD Source Address
  987. #define DMA_TCD3_SOFF (*(volatile int16_t *)0x40009064) // TCD Signed Source Address Offset
  988. #define DMA_TCD3_ATTR (*(volatile uint16_t *)0x40009066) // TCD Transfer Attributes
  989. #define DMA_TCD3_NBYTES_MLNO (*(volatile uint32_t *)0x40009068) // TCD Minor Byte Count, Minor Loop Disabled
  990. #define DMA_TCD3_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  991. #define DMA_TCD3_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  992. #define DMA_TCD3_SLAST (*(volatile int32_t *)0x4000906C) // TCD Last Source Address Adjustment
  993. #define DMA_TCD3_DADDR (*(volatile void * volatile *)0x40009070) // TCD Destination Address
  994. #define DMA_TCD3_DOFF (*(volatile int16_t *)0x40009074) // TCD Signed Destination Address Offset
  995. #define DMA_TCD3_CITER_ELINKYES (*(volatile uint16_t *)0x40009076) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  996. #define DMA_TCD3_CITER_ELINKNO (*(volatile uint16_t *)0x40009076) // ??
  997. #define DMA_TCD3_DLASTSGA (*(volatile int32_t *)0x40009078) // TCD Last Destination Address Adjustment/Scatter Gather Address
  998. #define DMA_TCD3_CSR (*(volatile uint16_t *)0x4000907C) // TCD Control and Status
  999. #define DMA_TCD3_BITER_ELINKYES (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
  1000. #define DMA_TCD3_BITER_ELINKNO (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
  1001. #define DMA_TCD4_SADDR (*(volatile const void * volatile *)0x40009080) // TCD Source Addr
  1002. #define DMA_TCD4_SOFF (*(volatile int16_t *)0x40009084) // TCD Signed Source Address Offset
  1003. #define DMA_TCD4_ATTR (*(volatile uint16_t *)0x40009086) // TCD Transfer Attributes
  1004. #define DMA_TCD4_NBYTES_MLNO (*(volatile uint32_t *)0x40009088) // TCD Minor Byte Count
  1005. #define DMA_TCD4_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
  1006. #define DMA_TCD4_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
  1007. #define DMA_TCD4_SLAST (*(volatile int32_t *)0x4000908C) // TCD Last Source Addr Adj.
  1008. #define DMA_TCD4_DADDR (*(volatile void * volatile *)0x40009090) // TCD Destination Address
  1009. #define DMA_TCD4_DOFF (*(volatile int16_t *)0x40009094) // TCD Signed Dest Address Offset
  1010. #define DMA_TCD4_CITER_ELINKYES (*(volatile uint16_t *)0x40009096) // TCD Current Minor Loop Link
  1011. #define DMA_TCD4_CITER_ELINKNO (*(volatile uint16_t *)0x40009096) // ??
  1012. #define DMA_TCD4_DLASTSGA (*(volatile int32_t *)0x40009098) // TCD Last Destination Addr Adj
  1013. #define DMA_TCD4_CSR (*(volatile uint16_t *)0x4000909C) // TCD Control and Status
  1014. #define DMA_TCD4_BITER_ELINKYES (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
  1015. #define DMA_TCD4_BITER_ELINKNO (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
  1016. #define DMA_TCD5_SADDR (*(volatile const void * volatile *)0x400090A0) // TCD Source Addr
  1017. #define DMA_TCD5_SOFF (*(volatile int16_t *)0x400090A4) // TCD Signed Source Address Offset
  1018. #define DMA_TCD5_ATTR (*(volatile uint16_t *)0x400090A6) // TCD Transfer Attributes
  1019. #define DMA_TCD5_NBYTES_MLNO (*(volatile uint32_t *)0x400090A8) // TCD Minor Byte Count
  1020. #define DMA_TCD5_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
  1021. #define DMA_TCD5_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
  1022. #define DMA_TCD5_SLAST (*(volatile int32_t *)0x400090AC) // TCD Last Source Addr Adj.
  1023. #define DMA_TCD5_DADDR (*(volatile void * volatile *)0x400090B0) // TCD Destination Address
  1024. #define DMA_TCD5_DOFF (*(volatile int16_t *)0x400090B4) // TCD Signed Dest Address Offset
  1025. #define DMA_TCD5_CITER_ELINKYES (*(volatile uint16_t *)0x400090B6) // TCD Current Minor Loop Link
  1026. #define DMA_TCD5_CITER_ELINKNO (*(volatile uint16_t *)0x400090B6) // ??
  1027. #define DMA_TCD5_DLASTSGA (*(volatile int32_t *)0x400090B8) // TCD Last Destination Addr Adj
  1028. #define DMA_TCD5_CSR (*(volatile uint16_t *)0x400090BC) // TCD Control and Status
  1029. #define DMA_TCD5_BITER_ELINKYES (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
  1030. #define DMA_TCD5_BITER_ELINKNO (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
  1031. #define DMA_TCD6_SADDR (*(volatile const void * volatile *)0x400090C0) // TCD Source Addr
  1032. #define DMA_TCD6_SOFF (*(volatile int16_t *)0x400090C4) // TCD Signed Source Address Offset
  1033. #define DMA_TCD6_ATTR (*(volatile uint16_t *)0x400090C6) // TCD Transfer Attributes
  1034. #define DMA_TCD6_NBYTES_MLNO (*(volatile uint32_t *)0x400090C8) // TCD Minor Byte Count
  1035. #define DMA_TCD6_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
  1036. #define DMA_TCD6_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
  1037. #define DMA_TCD6_SLAST (*(volatile int32_t *)0x400090CC) // TCD Last Source Addr Adj.
  1038. #define DMA_TCD6_DADDR (*(volatile void * volatile *)0x400090D0) // TCD Destination Address
  1039. #define DMA_TCD6_DOFF (*(volatile int16_t *)0x400090D4) // TCD Signed Dest Address Offset
  1040. #define DMA_TCD6_CITER_ELINKYES (*(volatile uint16_t *)0x400090D6) // TCD Current Minor Loop Link
  1041. #define DMA_TCD6_CITER_ELINKNO (*(volatile uint16_t *)0x400090D6) // ??
  1042. #define DMA_TCD6_DLASTSGA (*(volatile int32_t *)0x400090D8) // TCD Last Destination Addr Adj
  1043. #define DMA_TCD6_CSR (*(volatile uint16_t *)0x400090DC) // TCD Control and Status
  1044. #define DMA_TCD6_BITER_ELINKYES (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
  1045. #define DMA_TCD6_BITER_ELINKNO (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
  1046. #define DMA_TCD7_SADDR (*(volatile const void * volatile *)0x400090E0) // TCD Source Addr
  1047. #define DMA_TCD7_SOFF (*(volatile int16_t *)0x400090E4) // TCD Signed Source Address Offset
  1048. #define DMA_TCD7_ATTR (*(volatile uint16_t *)0x400090E6) // TCD Transfer Attributes
  1049. #define DMA_TCD7_NBYTES_MLNO (*(volatile uint32_t *)0x400090E8) // TCD Minor Byte Count
  1050. #define DMA_TCD7_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
  1051. #define DMA_TCD7_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
  1052. #define DMA_TCD7_SLAST (*(volatile int32_t *)0x400090EC) // TCD Last Source Addr Adj.
  1053. #define DMA_TCD7_DADDR (*(volatile void * volatile *)0x400090F0) // TCD Destination Address
  1054. #define DMA_TCD7_DOFF (*(volatile int16_t *)0x400090F4) // TCD Signed Dest Address Offset
  1055. #define DMA_TCD7_CITER_ELINKYES (*(volatile uint16_t *)0x400090F6) // TCD Current Minor Loop Link
  1056. #define DMA_TCD7_CITER_ELINKNO (*(volatile uint16_t *)0x400090F6) // ??
  1057. #define DMA_TCD7_DLASTSGA (*(volatile int32_t *)0x400090F8) // TCD Last Destination Addr Adj
  1058. #define DMA_TCD7_CSR (*(volatile uint16_t *)0x400090FC) // TCD Control and Status
  1059. #define DMA_TCD7_BITER_ELINKYES (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
  1060. #define DMA_TCD7_BITER_ELINKNO (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
  1061. #define DMA_TCD8_SADDR (*(volatile const void * volatile *)0x40009100) // TCD Source Addr
  1062. #define DMA_TCD8_SOFF (*(volatile int16_t *)0x40009104) // TCD Signed Source Address Offset
  1063. #define DMA_TCD8_ATTR (*(volatile uint16_t *)0x40009106) // TCD Transfer Attributes
  1064. #define DMA_TCD8_NBYTES_MLNO (*(volatile uint32_t *)0x40009108) // TCD Minor Byte Count
  1065. #define DMA_TCD8_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
  1066. #define DMA_TCD8_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
  1067. #define DMA_TCD8_SLAST (*(volatile int32_t *)0x4000910C) // TCD Last Source Addr Adj.
  1068. #define DMA_TCD8_DADDR (*(volatile void * volatile *)0x40009110) // TCD Destination Address
  1069. #define DMA_TCD8_DOFF (*(volatile int16_t *)0x40009114) // TCD Signed Dest Address Offset
  1070. #define DMA_TCD8_CITER_ELINKYES (*(volatile uint16_t *)0x40009116) // TCD Current Minor Loop Link
  1071. #define DMA_TCD8_CITER_ELINKNO (*(volatile uint16_t *)0x40009116) // ??
  1072. #define DMA_TCD8_DLASTSGA (*(volatile int32_t *)0x40009118) // TCD Last Destination Addr Adj
  1073. #define DMA_TCD8_CSR (*(volatile uint16_t *)0x4000911C) // TCD Control and Status
  1074. #define DMA_TCD8_BITER_ELINKYES (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
  1075. #define DMA_TCD8_BITER_ELINKNO (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
  1076. #define DMA_TCD9_SADDR (*(volatile const void * volatile *)0x40009120) // TCD Source Addr
  1077. #define DMA_TCD9_SOFF (*(volatile int16_t *)0x40009124) // TCD Signed Source Address Offset
  1078. #define DMA_TCD9_ATTR (*(volatile uint16_t *)0x40009126) // TCD Transfer Attributes
  1079. #define DMA_TCD9_NBYTES_MLNO (*(volatile uint32_t *)0x40009128) // TCD Minor Byte Count
  1080. #define DMA_TCD9_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
  1081. #define DMA_TCD9_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
  1082. #define DMA_TCD9_SLAST (*(volatile int32_t *)0x4000912C) // TCD Last Source Addr Adj.
  1083. #define DMA_TCD9_DADDR (*(volatile void * volatile *)0x40009130) // TCD Destination Address
  1084. #define DMA_TCD9_DOFF (*(volatile int16_t *)0x40009134) // TCD Signed Dest Address Offset
  1085. #define DMA_TCD9_CITER_ELINKYES (*(volatile uint16_t *)0x40009136) // TCD Current Minor Loop Link
  1086. #define DMA_TCD9_CITER_ELINKNO (*(volatile uint16_t *)0x40009136) // ??
  1087. #define DMA_TCD9_DLASTSGA (*(volatile int32_t *)0x40009138) // TCD Last Destination Addr Adj
  1088. #define DMA_TCD9_CSR (*(volatile uint16_t *)0x4000913C) // TCD Control and Status
  1089. #define DMA_TCD9_BITER_ELINKYES (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
  1090. #define DMA_TCD9_BITER_ELINKNO (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
  1091. #define DMA_TCD10_SADDR (*(volatile const void * volatile *)0x40009140) // TCD Source Addr
  1092. #define DMA_TCD10_SOFF (*(volatile int16_t *)0x40009144) // TCD Signed Source Address Offset
  1093. #define DMA_TCD10_ATTR (*(volatile uint16_t *)0x40009146) // TCD Transfer Attributes
  1094. #define DMA_TCD10_NBYTES_MLNO (*(volatile uint32_t *)0x40009148) // TCD Minor Byte Count
  1095. #define DMA_TCD10_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
  1096. #define DMA_TCD10_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
  1097. #define DMA_TCD10_SLAST (*(volatile int32_t *)0x4000914C) // TCD Last Source Addr Adj.
  1098. #define DMA_TCD10_DADDR (*(volatile void * volatile *)0x40009150) // TCD Destination Address
  1099. #define DMA_TCD10_DOFF (*(volatile int16_t *)0x40009154) // TCD Signed Dest Address Offset
  1100. #define DMA_TCD10_CITER_ELINKYES (*(volatile uint16_t *)0x40009156) // TCD Current Minor Loop Link
  1101. #define DMA_TCD10_CITER_ELINKNO (*(volatile uint16_t *)0x40009156) // ??
  1102. #define DMA_TCD10_DLASTSGA (*(volatile int32_t *)0x40009158) // TCD Last Destination Addr Adj
  1103. #define DMA_TCD10_CSR (*(volatile uint16_t *)0x4000915C) // TCD Control and Status
  1104. #define DMA_TCD10_BITER_ELINKYES (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
  1105. #define DMA_TCD10_BITER_ELINKNO (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
  1106. #define DMA_TCD11_SADDR (*(volatile const void * volatile *)0x40009160) // TCD Source Addr
  1107. #define DMA_TCD11_SOFF (*(volatile int16_t *)0x40009164) // TCD Signed Source Address Offset
  1108. #define DMA_TCD11_ATTR (*(volatile uint16_t *)0x40009166) // TCD Transfer Attributes
  1109. #define DMA_TCD11_NBYTES_MLNO (*(volatile uint32_t *)0x40009168) // TCD Minor Byte Count
  1110. #define DMA_TCD11_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
  1111. #define DMA_TCD11_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
  1112. #define DMA_TCD11_SLAST (*(volatile int32_t *)0x4000916C) // TCD Last Source Addr Adj.
  1113. #define DMA_TCD11_DADDR (*(volatile void * volatile *)0x40009170) // TCD Destination Address
  1114. #define DMA_TCD11_DOFF (*(volatile int16_t *)0x40009174) // TCD Signed Dest Address Offset
  1115. #define DMA_TCD11_CITER_ELINKYES (*(volatile uint16_t *)0x40009176) // TCD Current Minor Loop Link
  1116. #define DMA_TCD11_CITER_ELINKNO (*(volatile uint16_t *)0x40009176) // ??
  1117. #define DMA_TCD11_DLASTSGA (*(volatile int32_t *)0x40009178) // TCD Last Destination Addr Adj
  1118. #define DMA_TCD11_CSR (*(volatile uint16_t *)0x4000917C) // TCD Control and Status
  1119. #define DMA_TCD11_BITER_ELINKYES (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
  1120. #define DMA_TCD11_BITER_ELINKNO (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
  1121. #define DMA_TCD12_SADDR (*(volatile const void * volatile *)0x40009180) // TCD Source Addr
  1122. #define DMA_TCD12_SOFF (*(volatile int16_t *)0x40009184) // TCD Signed Source Address Offset
  1123. #define DMA_TCD12_ATTR (*(volatile uint16_t *)0x40009186) // TCD Transfer Attributes
  1124. #define DMA_TCD12_NBYTES_MLNO (*(volatile uint32_t *)0x40009188) // TCD Minor Byte Count
  1125. #define DMA_TCD12_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
  1126. #define DMA_TCD12_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
  1127. #define DMA_TCD12_SLAST (*(volatile int32_t *)0x4000918C) // TCD Last Source Addr Adj.
  1128. #define DMA_TCD12_DADDR (*(volatile void * volatile *)0x40009190) // TCD Destination Address
  1129. #define DMA_TCD12_DOFF (*(volatile int16_t *)0x40009194) // TCD Signed Dest Address Offset
  1130. #define DMA_TCD12_CITER_ELINKYES (*(volatile uint16_t *)0x40009196) // TCD Current Minor Loop Link
  1131. #define DMA_TCD12_CITER_ELINKNO (*(volatile uint16_t *)0x40009196) // ??
  1132. #define DMA_TCD12_DLASTSGA (*(volatile int32_t *)0x40009198) // TCD Last Destination Addr Adj
  1133. #define DMA_TCD12_CSR (*(volatile uint16_t *)0x4000919C) // TCD Control and Status
  1134. #define DMA_TCD12_BITER_ELINKYES (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
  1135. #define DMA_TCD12_BITER_ELINKNO (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
  1136. #define DMA_TCD13_SADDR (*(volatile const void * volatile *)0x400091A0) // TCD Source Addr
  1137. #define DMA_TCD13_SOFF (*(volatile int16_t *)0x400091A4) // TCD Signed Source Address Offset
  1138. #define DMA_TCD13_ATTR (*(volatile uint16_t *)0x400091A6) // TCD Transfer Attributes
  1139. #define DMA_TCD13_NBYTES_MLNO (*(volatile uint32_t *)0x400091A8) // TCD Minor Byte Count
  1140. #define DMA_TCD13_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
  1141. #define DMA_TCD13_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
  1142. #define DMA_TCD13_SLAST (*(volatile int32_t *)0x400091AC) // TCD Last Source Addr Adj.
  1143. #define DMA_TCD13_DADDR (*(volatile void * volatile *)0x400091B0) // TCD Destination Address
  1144. #define DMA_TCD13_DOFF (*(volatile int16_t *)0x400091B4) // TCD Signed Dest Address Offset
  1145. #define DMA_TCD13_CITER_ELINKYES (*(volatile uint16_t *)0x400091B6) // TCD Current Minor Loop Link
  1146. #define DMA_TCD13_CITER_ELINKNO (*(volatile uint16_t *)0x400091B6) // ??
  1147. #define DMA_TCD13_DLASTSGA (*(volatile int32_t *)0x400091B8) // TCD Last Destination Addr Adj
  1148. #define DMA_TCD13_CSR (*(volatile uint16_t *)0x400091BC) // TCD Control and Status
  1149. #define DMA_TCD13_BITER_ELINKYES (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
  1150. #define DMA_TCD13_BITER_ELINKNO (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
  1151. #define DMA_TCD14_SADDR (*(volatile const void * volatile *)0x400091C0) // TCD Source Addr
  1152. #define DMA_TCD14_SOFF (*(volatile int16_t *)0x400091C4) // TCD Signed Source Address Offset
  1153. #define DMA_TCD14_ATTR (*(volatile uint16_t *)0x400091C6) // TCD Transfer Attributes
  1154. #define DMA_TCD14_NBYTES_MLNO (*(volatile uint32_t *)0x400091C8) // TCD Minor Byte Count
  1155. #define DMA_TCD14_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
  1156. #define DMA_TCD14_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
  1157. #define DMA_TCD14_SLAST (*(volatile int32_t *)0x400091CC) // TCD Last Source Addr Adj.
  1158. #define DMA_TCD14_DADDR (*(volatile void * volatile *)0x400091D0) // TCD Destination Address
  1159. #define DMA_TCD14_DOFF (*(volatile int16_t *)0x400091D4) // TCD Signed Dest Address Offset
  1160. #define DMA_TCD14_CITER_ELINKYES (*(volatile uint16_t *)0x400091D6) // TCD Current Minor Loop Link
  1161. #define DMA_TCD14_CITER_ELINKNO (*(volatile uint16_t *)0x400091D6) // ??
  1162. #define DMA_TCD14_DLASTSGA (*(volatile int32_t *)0x400091D8) // TCD Last Destination Addr Adj
  1163. #define DMA_TCD14_CSR (*(volatile uint16_t *)0x400091DC) // TCD Control and Status
  1164. #define DMA_TCD14_BITER_ELINKYES (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
  1165. #define DMA_TCD14_BITER_ELINKNO (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
  1166. #define DMA_TCD15_SADDR (*(volatile const void * volatile *)0x400091E0) // TCD Source Addr
  1167. #define DMA_TCD15_SOFF (*(volatile int16_t *)0x400091E4) // TCD Signed Source Address Offset
  1168. #define DMA_TCD15_ATTR (*(volatile uint16_t *)0x400091E6) // TCD Transfer Attributes
  1169. #define DMA_TCD15_NBYTES_MLNO (*(volatile uint32_t *)0x400091E8) // TCD Minor Byte Count
  1170. #define DMA_TCD15_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
  1171. #define DMA_TCD15_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
  1172. #define DMA_TCD15_SLAST (*(volatile int32_t *)0x400091EC) // TCD Last Source Addr Adj.
  1173. #define DMA_TCD15_DADDR (*(volatile void * volatile *)0x400091F0) // TCD Destination Address
  1174. #define DMA_TCD15_DOFF (*(volatile int16_t *)0x400091F4) // TCD Signed Dest Address Offset
  1175. #define DMA_TCD15_CITER_ELINKYES (*(volatile uint16_t *)0x400091F6) // TCD Current Minor Loop Link
  1176. #define DMA_TCD15_CITER_ELINKNO (*(volatile uint16_t *)0x400091F6) // ??
  1177. #define DMA_TCD15_DLASTSGA (*(volatile int32_t *)0x400091F8) // TCD Last Destination Addr Adj
  1178. #define DMA_TCD15_CSR (*(volatile uint16_t *)0x400091FC) // TCD Control and Status
  1179. #define DMA_TCD15_BITER_ELINKYES (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
  1180. #define DMA_TCD15_BITER_ELINKNO (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
  1181. #elif defined(KINETISL)
  1182. #define DMA_SAR0 (*(volatile const void * volatile *)0x40008100) // Source Address
  1183. #define DMA_DAR0 (*(volatile void * volatile *)0x40008104) // Destination Address
  1184. #define DMA_DSR_BCR0 (*(volatile uint32_t *)0x40008108) // Status / Byte Count
  1185. #define DMA_DCR0 (*(volatile uint32_t *)0x4000810C) // Control
  1186. #define DMA_SAR1 (*(volatile const void * volatile *)0x40008110) // Source Address
  1187. #define DMA_DAR1 (*(volatile void * volatile *)0x40008114) // Destination Address
  1188. #define DMA_DSR_BCR1 (*(volatile uint32_t *)0x40008118) // Status / Byte Count
  1189. #define DMA_DCR1 (*(volatile uint32_t *)0x4000811C) // Control
  1190. #define DMA_SAR2 (*(volatile const void * volatile *)0x40008120) // Source Address
  1191. #define DMA_DAR2 (*(volatile void * volatile *)0x40008124) // Destination Address
  1192. #define DMA_DSR_BCR2 (*(volatile uint32_t *)0x40008128) // Status / Byte Count
  1193. #define DMA_DCR2 (*(volatile uint32_t *)0x4000812C) // Control
  1194. #define DMA_SAR3 (*(volatile const void * volatile *)0x40008130) // Source Address
  1195. #define DMA_DAR3 (*(volatile void * volatile *)0x40008134) // Destination Address
  1196. #define DMA_DSR_BCR3 (*(volatile uint32_t *)0x40008138) // Status / Byte Count
  1197. #define DMA_DCR3 (*(volatile uint32_t *)0x4000813C) // Control
  1198. #define DMA_DSR_BCR_CE ((uint32_t)0x40000000) // Configuration Error
  1199. #define DMA_DSR_BCR_BES ((uint32_t)0x20000000) // Bus Error on Source
  1200. #define DMA_DSR_BCR_BED ((uint32_t)0x10000000) // Bus Error on Destination
  1201. #define DMA_DSR_BCR_REQ ((uint32_t)0x04000000) // Request
  1202. #define DMA_DSR_BCR_BSY ((uint32_t)0x02000000) // Busy
  1203. #define DMA_DSR_BCR_DONE ((uint32_t)0x01000000) // Transactions Done
  1204. #define DMA_DSR_BCR_BCR(n) ((n) & 0x00FFFFFF) // Byte Count Remaining
  1205. #define DMA_DCR_EINT ((uint32_t)0x80000000) // Enable Interrupt on Completion
  1206. #define DMA_DCR_ERQ ((uint32_t)0x40000000) // Enable Peripheral Request
  1207. #define DMA_DCR_CS ((uint32_t)0x20000000) // Cycle Steal
  1208. #define DMA_DCR_AA ((uint32_t)0x10000000) // Auto-align
  1209. #define DMA_DCR_EADREQ ((uint32_t)0x00800000) // Enable asynchronous DMA requests
  1210. #define DMA_DCR_SINC ((uint32_t)0x00400000) // Source Increment
  1211. #define DMA_DCR_SSIZE(n) (((n) & 3) << 20) // Source Size, 0=32, 1=8, 2=16
  1212. #define DMA_DCR_DINC ((uint32_t)0x00080000) // Destination Increment
  1213. #define DMA_DCR_DSIZE(n) (((n) & 3) << 17) // Dest Size, 0=32, 1=8, 2=16
  1214. #define DMA_DCR_START ((uint32_t)0x00010000) // Start Transfer
  1215. #define DMA_DCR_SMOD(n) (((n) & 15) << 12) // Source Address Modulo
  1216. #define DMA_DCR_DMOD(n) (((n) & 15) << 8) // Destination Address Modulo
  1217. #define DMA_DCR_D_REQ ((uint32_t)0x00000080) // Disable Request
  1218. #define DMA_DCR_LINKCC(n) (((n) & 3) << 4) // Link Channel Control
  1219. #define DMA_DCR_LCH1(n) (((n) & 3) << 2) // Link Channel 1
  1220. #define DMA_DCR_LCH2(n) (((n) & 3) << 0) // Link Channel 2
  1221. #endif
  1222. // Chapter 22: External Watchdog Monitor (EWM)
  1223. #define EWM_CTRL (*(volatile uint8_t *)0x40061000) // Control Register
  1224. #define EWM_SERV (*(volatile uint8_t *)0x40061001) // Service Register
  1225. #define EWM_CMPL (*(volatile uint8_t *)0x40061002) // Compare Low Register
  1226. #define EWM_CMPH (*(volatile uint8_t *)0x40061003) // Compare High Register
  1227. // Chapter 23: Watchdog Timer (WDOG)
  1228. #define WDOG_STCTRLH (*(volatile uint16_t *)0x40052000) // Watchdog Status and Control Register High
  1229. #define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) // Allows the WDOG's functional test mode to be disabled permanently.
  1230. #define WDOG_STCTRLH_BYTESEL(n) ((uint16_t)(((n) & 3) << 12)) // selects the byte to be tested when the watchdog is in the byte test mode.
  1231. #define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800)
  1232. #define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400)
  1233. #define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080)
  1234. #define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040)
  1235. #define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020)
  1236. #define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010)
  1237. #define WDOG_STCTRLH_WINEN ((uint16_t)0x0008)
  1238. #define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004)
  1239. #define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002)
  1240. #define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001)
  1241. #define WDOG_STCTRLL (*(volatile uint16_t *)0x40052002) // Watchdog Status and Control Register Low
  1242. #define WDOG_TOVALH (*(volatile uint16_t *)0x40052004) // Watchdog Time-out Value Register High
  1243. #define WDOG_TOVALL (*(volatile uint16_t *)0x40052006) // Watchdog Time-out Value Register Low
  1244. #define WDOG_WINH (*(volatile uint16_t *)0x40052008) // Watchdog Window Register High
  1245. #define WDOG_WINL (*(volatile uint16_t *)0x4005200A) // Watchdog Window Register Low
  1246. #define WDOG_REFRESH (*(volatile uint16_t *)0x4005200C) // Watchdog Refresh register
  1247. #define WDOG_UNLOCK (*(volatile uint16_t *)0x4005200E) // Watchdog Unlock register
  1248. #define WDOG_UNLOCK_SEQ1 ((uint16_t)0xC520)
  1249. #define WDOG_UNLOCK_SEQ2 ((uint16_t)0xD928)
  1250. #define WDOG_TMROUTH (*(volatile uint16_t *)0x40052010) // Watchdog Timer Output Register High
  1251. #define WDOG_TMROUTL (*(volatile uint16_t *)0x40052012) // Watchdog Timer Output Register Low
  1252. #define WDOG_RSTCNT (*(volatile uint16_t *)0x40052014) // Watchdog Reset Count register
  1253. #define WDOG_PRESC (*(volatile uint16_t *)0x40052016) // Watchdog Prescaler register
  1254. // Chapter 24: Multipurpose Clock Generator (MCG)
  1255. #define MCG_C1 (*(volatile uint8_t *)0x40064000) // MCG Control 1 Register
  1256. #define MCG_C1_IREFSTEN ((uint8_t)0x01) // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
  1257. #define MCG_C1_IRCLKEN ((uint8_t)0x02) // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
  1258. #define MCG_C1_IREFS ((uint8_t)0x04) // Internal Reference Select, Selects the reference clock source for the FLL.
  1259. #define MCG_C1_FRDIV(n) ((uint8_t)(((n) & 0x07) << 3)) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
  1260. #define MCG_C1_CLKS(n) ((uint8_t)(((n) & 0x03) << 6)) // Clock Source Select, Selects the clock source for MCGOUTCLK
  1261. #define MCG_C2 (*(volatile uint8_t *)0x40064001) // MCG Control 2 Register
  1262. #define MCG_C2_IRCS ((uint8_t)0x01) // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
  1263. #define MCG_C2_LP ((uint8_t)0x02) // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
  1264. #define MCG_C2_EREFS ((uint8_t)0x04) // External Reference Select, Selects the source for the external reference clock.
  1265. #define MCG_C2_HGO0 ((uint8_t)0x08) // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
  1266. #define MCG_C2_RANGE0(n) ((uint8_t)(((n) & 0x03) << 4)) // Frequency Range Select, Selects the frequency range for the crystal oscillator
  1267. #define MCG_C2_LOCRE0 ((uint8_t)0x80) // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
  1268. #define MCG_C3 (*(volatile uint8_t *)0x40064002) // MCG Control 3 Register
  1269. #define MCG_C3_SCTRIM(n) ((uint8_t)(n)) // Slow Internal Reference Clock Trim Setting
  1270. #define MCG_C4 (*(volatile uint8_t *)0x40064003) // MCG Control 4 Register
  1271. #define MCG_C4_SCFTRIM ((uint8_t)0x01) // Slow Internal Reference Clock Fine Trim
  1272. #define MCG_C4_FCTRIM(n) ((uint8_t)(((n) & 0x0F) << 1)) // Fast Internal Reference Clock Trim Setting
  1273. #define MCG_C4_DRST_DRS(n) ((uint8_t)(((n) & 0x03) << 5)) // DCO Range Select
  1274. #define MCG_C4_DMX32 ((uint8_t)0x80) // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
  1275. #define MCG_C5 (*(volatile uint8_t *)0x40064004) // MCG Control 5 Register
  1276. #define MCG_C5_PRDIV0(n) ((uint8_t)((n) & 0x1F)) // PLL External Reference Divider
  1277. #define MCG_C5_PLLSTEN0 ((uint8_t)0x20) // PLL Stop Enable
  1278. #define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) // PLL Clock Enable
  1279. #define MCG_C6 (*(volatile uint8_t *)0x40064005) // MCG Control 6 Register
  1280. #define MCG_C6_VDIV0(n) ((uint8_t)((n) & 0x1F)) // VCO 0 Divider
  1281. #define MCG_C6_CME0 ((uint8_t)0x20) // Clock Monitor Enable
  1282. #define MCG_C6_PLLS ((uint8_t)0x40) // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
  1283. #define MCG_C6_LOLIE0 ((uint8_t)0x80) // Loss of Lock Interrrupt Enable
  1284. #define MCG_S (*(volatile uint8_t *)0x40064006) // MCG Status Register
  1285. #define MCG_S_IRCST ((uint8_t)0x01) // Internal Reference Clock Status
  1286. #define MCG_S_OSCINIT0 ((uint8_t)0x02) // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
  1287. #define MCG_S_CLKST(n) ((uint8_t)(((n) & 0x03) << 2)) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
  1288. #define MCG_S_CLKST_MASK ((uint8_t)0x0C)
  1289. #define MCG_S_IREFST ((uint8_t)0x10) // Internal Reference Status
  1290. #define MCG_S_PLLST ((uint8_t)0x20) // PLL Select Status
  1291. #define MCG_S_LOCK0 ((uint8_t)0x40) // Lock Status, 0=PLL Unlocked, 1=PLL Locked
  1292. #define MCG_S_LOLS0 ((uint8_t)0x80) // Loss of Lock Status
  1293. #define MCG_SC (*(volatile uint8_t *)0x40064008) // MCG Status and Control Register
  1294. #define MCG_SC_LOCS0 ((uint8_t)0x01) // OSC0 Loss of Clock Status
  1295. #define MCG_SC_FCRDIV(n) ((uint8_t)(((n) & 0x07) << 1)) // Fast Clock Internal Reference Divider
  1296. #define MCG_SC_FLTPRSRV ((uint8_t)0x10) // FLL Filter Preserve Enable
  1297. #define MCG_SC_ATMF ((uint8_t)0x20) // Automatic Trim Machine Fail Flag
  1298. #define MCG_SC_ATMS ((uint8_t)0x40) // Automatic Trim Machine Select
  1299. #define MCG_SC_ATME ((uint8_t)0x80) // Automatic Trim Machine Enable
  1300. #define MCG_ATCVH (*(volatile uint8_t *)0x4006400A) // MCG Auto Trim Compare Value High Register
  1301. #define MCG_ATCVL (*(volatile uint8_t *)0x4006400B) // MCG Auto Trim Compare Value Low Register
  1302. #define MCG_C7 (*(volatile uint8_t *)0x4006400C) // MCG Control 7 Register
  1303. #define MCG_C8 (*(volatile uint8_t *)0x4006400D) // MCG Control 8 Register
  1304. // Chapter 25: Oscillator (OSC)
  1305. #define OSC0_CR (*(volatile uint8_t *)0x40065000) // OSC Control Register
  1306. #define OSC_SC16P ((uint8_t)0x01) // Oscillator 16 pF Capacitor Load Configure
  1307. #define OSC_SC8P ((uint8_t)0x02) // Oscillator 8 pF Capacitor Load Configure
  1308. #define OSC_SC4P ((uint8_t)0x04) // Oscillator 4 pF Capacitor Load Configure
  1309. #define OSC_SC2P ((uint8_t)0x08) // Oscillator 2 pF Capacitor Load Configure
  1310. #define OSC_EREFSTEN ((uint8_t)0x20) // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
  1311. #define OSC_ERCLKEN ((uint8_t)0x80) // External Reference Enable, Enables external reference clock (OSCERCLK).
  1312. // Chapter 27: Flash Memory Controller (FMC)
  1313. #define FMC_PFAPR (*(volatile uint32_t *)0x4001F000) // Flash Access Protection
  1314. #define FMC_PFB0CR (*(volatile uint32_t *)0x4001F004) // Flash Control
  1315. #define FMC_TAGVDW0S0 (*(volatile uint32_t *)0x4001F100) // Cache Tag Storage
  1316. #define FMC_TAGVDW0S1 (*(volatile uint32_t *)0x4001F104) // Cache Tag Storage
  1317. #define FMC_TAGVDW1S0 (*(volatile uint32_t *)0x4001F108)// Cache Tag Storage
  1318. #define FMC_TAGVDW1S1 (*(volatile uint32_t *)0x4001F10C)// Cache Tag Storage
  1319. #define FMC_TAGVDW2S0 (*(volatile uint32_t *)0x4001F110)// Cache Tag Storage
  1320. #define FMC_TAGVDW2S1 (*(volatile uint32_t *)0x4001F114)// Cache Tag Storage
  1321. #define FMC_TAGVDW3S0 (*(volatile uint32_t *)0x4001F118)// Cache Tag Storage
  1322. #define FMC_TAGVDW3S1 (*(volatile uint32_t *)0x4001F11C)// Cache Tag Storage
  1323. #define FMC_DATAW0S0 (*(volatile uint32_t *)0x4001F200)// Cache Data Storage
  1324. #define FMC_DATAW0S1 (*(volatile uint32_t *)0x4001F204)// Cache Data Storage
  1325. #define FMC_DATAW1S0 (*(volatile uint32_t *)0x4001F208)// Cache Data Storage
  1326. #define FMC_DATAW1S1 (*(volatile uint32_t *)0x4001F20C)// Cache Data Storage
  1327. #define FMC_DATAW2S0 (*(volatile uint32_t *)0x4001F210)// Cache Data Storage
  1328. #define FMC_DATAW2S1 (*(volatile uint32_t *)0x4001F214)// Cache Data Storage
  1329. #define FMC_DATAW3S0 (*(volatile uint32_t *)0x4001F218)// Cache Data Storage
  1330. #define FMC_DATAW3S1 (*(volatile uint32_t *)0x4001F21C)// Cache Data Storage
  1331. // Chapter 28: Flash Memory Module (FTFL)
  1332. #define FTFL_FSTAT (*(volatile uint8_t *)0x40020000) // Flash Status Register
  1333. #define FTFL_FSTAT_CCIF ((uint8_t)0x80) // Command Complete Interrupt Flag
  1334. #define FTFL_FSTAT_RDCOLERR ((uint8_t)0x40) // Flash Read Collision Error Flag
  1335. #define FTFL_FSTAT_ACCERR ((uint8_t)0x20) // Flash Access Error Flag
  1336. #define FTFL_FSTAT_FPVIOL ((uint8_t)0x10) // Flash Protection Violation Flag
  1337. #define FTFL_FSTAT_MGSTAT0 ((uint8_t)0x01) // Memory Controller Command Completion Status Flag
  1338. #define FTFL_FCNFG (*(volatile uint8_t *)0x40020001) // Flash Configuration Register
  1339. #define FTFL_FCNFG_CCIE ((uint8_t)0x80) // Command Complete Interrupt Enable
  1340. #define FTFL_FCNFG_RDCOLLIE ((uint8_t)0x40) // Read Collision Error Interrupt Enable
  1341. #define FTFL_FCNFG_ERSAREQ ((uint8_t)0x20) // Erase All Request
  1342. #define FTFL_FCNFG_ERSSUSP ((uint8_t)0x10) // Erase Suspend
  1343. #define FTFL_FCNFG_PFLSH ((uint8_t)0x04) // Flash memory configuration
  1344. #define FTFL_FCNFG_RAMRDY ((uint8_t)0x02) // RAM Ready
  1345. #define FTFL_FCNFG_EEERDY ((uint8_t)0x01) // EEPROM Ready
  1346. #define FTFL_FSEC (*(const uint8_t *)0x40020002) // Flash Security Register
  1347. #define FTFL_FOPT (*(const uint8_t *)0x40020003) // Flash Option Register
  1348. #define FTFL_FCCOB3 (*(volatile uint8_t *)0x40020004) // Flash Common Command Object Registers
  1349. #define FTFL_FCCOB2 (*(volatile uint8_t *)0x40020005)
  1350. #define FTFL_FCCOB1 (*(volatile uint8_t *)0x40020006)
  1351. #define FTFL_FCCOB0 (*(volatile uint8_t *)0x40020007)
  1352. #define FTFL_FCCOB7 (*(volatile uint8_t *)0x40020008)
  1353. #define FTFL_FCCOB6 (*(volatile uint8_t *)0x40020009)
  1354. #define FTFL_FCCOB5 (*(volatile uint8_t *)0x4002000A)
  1355. #define FTFL_FCCOB4 (*(volatile uint8_t *)0x4002000B)
  1356. #define FTFL_FCCOBB (*(volatile uint8_t *)0x4002000C)
  1357. #define FTFL_FCCOBA (*(volatile uint8_t *)0x4002000D)
  1358. #define FTFL_FCCOB9 (*(volatile uint8_t *)0x4002000E)
  1359. #define FTFL_FCCOB8 (*(volatile uint8_t *)0x4002000F)
  1360. #define FTFL_FPROT3 (*(volatile uint8_t *)0x40020010) // Program Flash Protection Registers
  1361. #define FTFL_FPROT2 (*(volatile uint8_t *)0x40020011) // Program Flash Protection Registers
  1362. #define FTFL_FPROT1 (*(volatile uint8_t *)0x40020012) // Program Flash Protection Registers
  1363. #define FTFL_FPROT0 (*(volatile uint8_t *)0x40020013) // Program Flash Protection Registers
  1364. #define FTFL_FEPROT (*(volatile uint8_t *)0x40020016) // EEPROM Protection Register
  1365. #define FTFL_FDPROT (*(volatile uint8_t *)0x40020017) // Data Flash Protection Register
  1366. // Chapter 30: Cyclic Redundancy Check (CRC)
  1367. #define CRC_CRC (*(volatile uint32_t *)0x40032000) // CRC Data register
  1368. #define CRC_GPOLY (*(volatile uint32_t *)0x40032004) // CRC Polynomial register
  1369. #define CRC_CTRL (*(volatile uint32_t *)0x40032008) // CRC Control register
  1370. // Chapter 31: Analog-to-Digital Converter (ADC)
  1371. #define ADC0_SC1A (*(volatile uint32_t *)0x4003B000) // ADC status and control registers 1
  1372. #define ADC0_SC1B (*(volatile uint32_t *)0x4003B004) // ADC status and control registers 1
  1373. #define ADC_SC1_COCO ((uint32_t)0x80) // Conversion complete flag
  1374. #define ADC_SC1_AIEN ((uint32_t)0x40) // Interrupt enable
  1375. #define ADC_SC1_DIFF ((uint32_t)0x20) // Differential mode enable
  1376. #define ADC_SC1_ADCH(n) ((uint32_t)((n) & 0x1F)) // Input channel select
  1377. #define ADC0_CFG1 (*(volatile uint32_t *)0x4003B008) // ADC configuration register 1
  1378. #define ADC_CFG1_ADLPC ((uint32_t)0x80) // Low-power configuration
  1379. #define ADC_CFG1_ADIV(n) ((uint32_t)(((n) & 3) << 5)) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
  1380. #define ADC_CFG1_ADLSMP ((uint32_t)0x10) // Sample time configuration, 0=Short, 1=Long
  1381. #define ADC_CFG1_MODE(n) ((uint32_t)(((n) & 3) << 2)) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
  1382. #define ADC_CFG1_ADICLK(n) ((uint32_t)(((n) & 3) << 0)) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
  1383. #define ADC0_CFG2 (*(volatile uint32_t *)0x4003B00C) // Configuration register 2
  1384. #define ADC_CFG2_MUXSEL ((uint32_t)0x10) // 0=a channels, 1=b channels
  1385. #define ADC_CFG2_ADACKEN ((uint32_t)0x08) // async clock enable
  1386. #define ADC_CFG2_ADHSC ((uint32_t)0x04) // High speed configuration
  1387. #define ADC_CFG2_ADLSTS(n) ((uint32_t)(((n) & 3) << 0)) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
  1388. #define ADC0_RA (*(volatile uint32_t *)0x4003B010) // ADC data result register
  1389. #define ADC0_RB (*(volatile uint32_t *)0x4003B014) // ADC data result register
  1390. #define ADC0_CV1 (*(volatile uint32_t *)0x4003B018) // Compare value registers
  1391. #define ADC0_CV2 (*(volatile uint32_t *)0x4003B01C) // Compare value registers
  1392. #define ADC0_SC2 (*(volatile uint32_t *)0x4003B020) // Status and control register 2
  1393. #define ADC_SC2_ADACT ((uint32_t)0x80) // Conversion active
  1394. #define ADC_SC2_ADTRG ((uint32_t)0x40) // Conversion trigger select, 0=software, 1=hardware
  1395. #define ADC_SC2_ACFE ((uint32_t)0x20) // Compare function enable
  1396. #define ADC_SC2_ACFGT ((uint32_t)0x10) // Compare function greater than enable
  1397. #define ADC_SC2_ACREN ((uint32_t)0x08) // Compare function range enable
  1398. #define ADC_SC2_DMAEN ((uint32_t)0x04) // DMA enable
  1399. #define ADC_SC2_REFSEL(n) ((uint32_t)(((n) & 3) << 0)) // Voltage reference, 0=vcc/external, 1=1.2 volts
  1400. #define ADC0_SC3 (*(volatile uint32_t *)0x4003B024) // Status and control register 3
  1401. #define ADC_SC3_CAL ((uint32_t)0x80) // Calibration, 1=begin, stays set while cal in progress
  1402. #define ADC_SC3_CALF ((uint32_t)0x40) // Calibration failed flag
  1403. #define ADC_SC3_ADCO ((uint32_t)0x08) // Continuous conversion enable
  1404. #define ADC_SC3_AVGE ((uint32_t)0x04) // Hardware average enable
  1405. #define ADC_SC3_AVGS(n) ((uint32_t)(((n) & 3) << 0)) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
  1406. #define ADC0_OFS (*(volatile uint32_t *)0x4003B028) // ADC offset correction register
  1407. #define ADC0_PG (*(volatile uint32_t *)0x4003B02C) // ADC plus-side gain register
  1408. #define ADC0_MG (*(volatile uint32_t *)0x4003B030) // ADC minus-side gain register
  1409. #define ADC0_CLPD (*(volatile uint32_t *)0x4003B034) // ADC plus-side general calibration value register
  1410. #define ADC0_CLPS (*(volatile uint32_t *)0x4003B038) // ADC plus-side general calibration value register
  1411. #define ADC0_CLP4 (*(volatile uint32_t *)0x4003B03C) // ADC plus-side general calibration value register
  1412. #define ADC0_CLP3 (*(volatile uint32_t *)0x4003B040) // ADC plus-side general calibration value register
  1413. #define ADC0_CLP2 (*(volatile uint32_t *)0x4003B044) // ADC plus-side general calibration value register
  1414. #define ADC0_CLP1 (*(volatile uint32_t *)0x4003B048) // ADC plus-side general calibration value register
  1415. #define ADC0_CLP0 (*(volatile uint32_t *)0x4003B04C) // ADC plus-side general calibration value register
  1416. #define ADC0_PGA (*(volatile uint32_t *)0x4003B050) // ADC Programmable Gain Amplifier
  1417. #define ADC_PGA_PGAEN ((uint32_t)0x00800000) // Enable
  1418. #define ADC_PGA_PGALPB ((uint32_t)0x00100000) // Low-Power Mode Control, 0=low power, 1=normal
  1419. #define ADC_PGA_PGAG(n) ((uint32_t)(((n) & 15) << 16)) // Gain, 0=1X, 1=2X, 2=4X, 3=8X, 4=16X, 5=32X, 6=64X
  1420. #define ADC0_CLMD (*(volatile uint32_t *)0x4003B054) // ADC minus-side general calibration value register
  1421. #define ADC0_CLMS (*(volatile uint32_t *)0x4003B058) // ADC minus-side general calibration value register
  1422. #define ADC0_CLM4 (*(volatile uint32_t *)0x4003B05C) // ADC minus-side general calibration value register
  1423. #define ADC0_CLM3 (*(volatile uint32_t *)0x4003B060) // ADC minus-side general calibration value register
  1424. #define ADC0_CLM2 (*(volatile uint32_t *)0x4003B064) // ADC minus-side general calibration value register
  1425. #define ADC0_CLM1 (*(volatile uint32_t *)0x4003B068) // ADC minus-side general calibration value register
  1426. #define ADC0_CLM0 (*(volatile uint32_t *)0x4003B06C) // ADC minus-side general calibration value register
  1427. #define ADC1_SC1A (*(volatile uint32_t *)0x400BB000) // ADC status and control registers 1
  1428. #define ADC1_SC1B (*(volatile uint32_t *)0x400BB004) // ADC status and control registers 1
  1429. #define ADC1_CFG1 (*(volatile uint32_t *)0x400BB008) // ADC configuration register 1
  1430. #define ADC1_CFG2 (*(volatile uint32_t *)0x400BB00C) // Configuration register 2
  1431. #define ADC1_RA (*(volatile uint32_t *)0x400BB010) // ADC data result register
  1432. #define ADC1_RB (*(volatile uint32_t *)0x400BB014) // ADC data result register
  1433. #define ADC1_CV1 (*(volatile uint32_t *)0x400BB018) // Compare value registers
  1434. #define ADC1_CV2 (*(volatile uint32_t *)0x400BB01C) // Compare value registers
  1435. #define ADC1_SC2 (*(volatile uint32_t *)0x400BB020) // Status and control register 2
  1436. #define ADC1_SC3 (*(volatile uint32_t *)0x400BB024) // Status and control register 3
  1437. #define ADC1_OFS (*(volatile uint32_t *)0x400BB028) // ADC offset correction register
  1438. #define ADC1_PG (*(volatile uint32_t *)0x400BB02C) // ADC plus-side gain register
  1439. #define ADC1_MG (*(volatile uint32_t *)0x400BB030) // ADC minus-side gain register
  1440. #define ADC1_CLPD (*(volatile uint32_t *)0x400BB034) // ADC plus-side general calibration value register
  1441. #define ADC1_CLPS (*(volatile uint32_t *)0x400BB038) // ADC plus-side general calibration value register
  1442. #define ADC1_CLP4 (*(volatile uint32_t *)0x400BB03C) // ADC plus-side general calibration value register
  1443. #define ADC1_CLP3 (*(volatile uint32_t *)0x400BB040) // ADC plus-side general calibration value register
  1444. #define ADC1_CLP2 (*(volatile uint32_t *)0x400BB044) // ADC plus-side general calibration value register
  1445. #define ADC1_CLP1 (*(volatile uint32_t *)0x400BB048) // ADC plus-side general calibration value register
  1446. #define ADC1_CLP0 (*(volatile uint32_t *)0x400BB04C) // ADC plus-side general calibration value register
  1447. #define ADC1_PGA (*(volatile uint32_t *)0x400BB050) // ADC Programmable Gain Amplifier
  1448. #define ADC1_CLMD (*(volatile uint32_t *)0x400BB054) // ADC minus-side general calibration value register
  1449. #define ADC1_CLMS (*(volatile uint32_t *)0x400BB058) // ADC minus-side general calibration value register
  1450. #define ADC1_CLM4 (*(volatile uint32_t *)0x400BB05C) // ADC minus-side general calibration value register
  1451. #define ADC1_CLM3 (*(volatile uint32_t *)0x400BB060) // ADC minus-side general calibration value register
  1452. #define ADC1_CLM2 (*(volatile uint32_t *)0x400BB064) // ADC minus-side general calibration value register
  1453. #define ADC1_CLM1 (*(volatile uint32_t *)0x400BB068) // ADC minus-side general calibration value register
  1454. #define ADC1_CLM0 (*(volatile uint32_t *)0x400BB06C) // ADC minus-side general calibration value register
  1455. #if defined(KINETISK)
  1456. #define DAC0_DAT0L (*(volatile uint8_t *)0x400CC000) // DAC Data Low Register
  1457. #define DAC0_DATH (*(volatile uint8_t *)0x400CC001) // DAC Data High Register
  1458. #define DAC0_DAT1L (*(volatile uint8_t *)0x400CC002) // DAC Data Low Register
  1459. #define DAC0_DAT2L (*(volatile uint8_t *)0x400CC004) // DAC Data Low Register
  1460. #define DAC0_DAT3L (*(volatile uint8_t *)0x400CC006) // DAC Data Low Register
  1461. #define DAC0_DAT4L (*(volatile uint8_t *)0x400CC008) // DAC Data Low Register
  1462. #define DAC0_DAT5L (*(volatile uint8_t *)0x400CC00A) // DAC Data Low Register
  1463. #define DAC0_DAT6L (*(volatile uint8_t *)0x400CC00C) // DAC Data Low Register
  1464. #define DAC0_DAT7L (*(volatile uint8_t *)0x400CC00E) // DAC Data Low Register
  1465. #define DAC0_DAT8L (*(volatile uint8_t *)0x400CC010) // DAC Data Low Register
  1466. #define DAC0_DAT9L (*(volatile uint8_t *)0x400CC012) // DAC Data Low Register
  1467. #define DAC0_DAT10L (*(volatile uint8_t *)0x400CC014) // DAC Data Low Register
  1468. #define DAC0_DAT11L (*(volatile uint8_t *)0x400CC016) // DAC Data Low Register
  1469. #define DAC0_DAT12L (*(volatile uint8_t *)0x400CC018) // DAC Data Low Register
  1470. #define DAC0_DAT13L (*(volatile uint8_t *)0x400CC01A) // DAC Data Low Register
  1471. #define DAC0_DAT14L (*(volatile uint8_t *)0x400CC01C) // DAC Data Low Register
  1472. #define DAC0_DAT15L (*(volatile uint8_t *)0x400CC01E) // DAC Data Low Register
  1473. #define DAC0_SR (*(volatile uint8_t *)0x400CC020) // DAC Status Register
  1474. #define DAC0_C0 (*(volatile uint8_t *)0x400CC021) // DAC Control Register
  1475. #define DAC_C0_DACEN 0x80 // DAC Enable
  1476. #define DAC_C0_DACRFS 0x40 // DAC Reference Select
  1477. #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
  1478. #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
  1479. #define DAC_C0_LPEN 0x08 // DAC Low Power Control
  1480. #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
  1481. #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
  1482. #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
  1483. #define DAC0_C1 (*(volatile uint8_t *)0x400CC022) // DAC Control Register 1
  1484. #define DAC_C1_DMAEN 0x80 // DMA Enable Select
  1485. #define DAC_C1_DACBFWM(n) ((((n) & 3) << 3)) // DAC Buffer Watermark Select
  1486. #define DAC_C1_DACBFMD(n) ((((n) & 3) << 1)) // DAC Buffer Work Mode Select
  1487. #define DAC_C1_DACBFEN 0x01 // DAC Buffer Enable
  1488. #define DAC0_C2 (*(volatile uint8_t *)0x400CC023) // DAC Control Register 2
  1489. #define DAC_C2_DACBFRP(n) ((((n) & 15) << 4)) // DAC Buffer Read Pointer
  1490. #define DAC_C2_DACBFUP(n) ((((n) & 15) << 0)) // DAC Buffer Upper Limit
  1491. #elif defined(KINETISL)
  1492. #define DAC0_DAT0L (*(volatile uint8_t *)0x4003F000) // Data Low
  1493. #define DAC0_DAT0H (*(volatile uint8_t *)0x4003F001) // Data High
  1494. #define DAC0_DAT1L (*(volatile uint8_t *)0x4003F002) // Data Low
  1495. #define DAC0_DAT1H (*(volatile uint8_t *)0x4003F003) // Data High
  1496. #define DAC0_SR (*(volatile uint8_t *)0x4003F020) // Status
  1497. #define DAC0_C0 (*(volatile uint8_t *)0x4003F021) // Control Register
  1498. #define DAC0_C1 (*(volatile uint8_t *)0x4003F022) // Control Register 1
  1499. #define DAC0_C2 (*(volatile uint8_t *)0x4003F023) // Control Register 2
  1500. #define DAC_SR_DACBFRPTF ((uint8_t)0x02) // Read Pointer Top Position Flag
  1501. #define DAC_SR_DACBFRPBF ((uint8_t)0x01) // Read Pointer Bottom Position Flag
  1502. #define DAC_C0_DACEN ((uint8_t)0x80) // Enable
  1503. #define DAC_C0_DACRFS ((uint8_t)0x40) // Reference, 0=AREF pin, 1=VCC
  1504. #define DAC_C0_DACTRGSEL ((uint8_t)0x20) // Trigger Select
  1505. #define DAC_C0_DACSWTRG ((uint8_t)0x10) // Software Trigger
  1506. #define DAC_C0_LPEN ((uint8_t)0x08) // Low Power Control
  1507. #define DAC_C0_DACBTIEN ((uint8_t)0x02) // Top Flag Interrupt Enable
  1508. #define DAC_C0_DACBBIEN ((uint8_t)0x01) // Bottom Flag Interrupt Enable
  1509. #define DAC_C1_DMAEN ((uint8_t)0x80) // DMA Enable
  1510. #define DAC_C1_DACBFMD ((uint8_t)0x04) // Work Mode Select
  1511. #define DAC_C1_DACBFEN ((uint8_t)0x01) // Buffer Enable
  1512. #define DAC_C2_DACBFRP ((uint8_t)0x10) // Buffer Read Pointer
  1513. #define DAC_C2_DACBFUP ((uint8_t)0x01) // Buffer Upper Limit
  1514. #endif
  1515. //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
  1516. //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
  1517. // Chapter 32: Comparator (CMP)
  1518. #define CMP0_CR0 (*(volatile uint8_t *)0x40073000) // CMP Control Register 0
  1519. #define CMP0_CR1 (*(volatile uint8_t *)0x40073001) // CMP Control Register 1
  1520. #define CMP0_FPR (*(volatile uint8_t *)0x40073002) // CMP Filter Period Register
  1521. #define CMP0_SCR (*(volatile uint8_t *)0x40073003) // CMP Status and Control Register
  1522. #define CMP0_DACCR (*(volatile uint8_t *)0x40073004) // DAC Control Register
  1523. #define CMP0_MUXCR (*(volatile uint8_t *)0x40073005) // MUX Control Register
  1524. #define CMP1_CR0 (*(volatile uint8_t *)0x40073008) // CMP Control Register 0
  1525. #define CMP1_CR1 (*(volatile uint8_t *)0x40073009) // CMP Control Register 1
  1526. #define CMP1_FPR (*(volatile uint8_t *)0x4007300A) // CMP Filter Period Register
  1527. #define CMP1_SCR (*(volatile uint8_t *)0x4007300B) // CMP Status and Control Register
  1528. #define CMP1_DACCR (*(volatile uint8_t *)0x4007300C) // DAC Control Register
  1529. #define CMP1_MUXCR (*(volatile uint8_t *)0x4007300D) // MUX Control Register
  1530. #define CMP2_CR0 (*(volatile uint8_t *)0x40073010) // CMP Control Register 0
  1531. #define CMP2_CR1 (*(volatile uint8_t *)0x40073011) // CMP Control Register 1
  1532. #define CMP2_FPR (*(volatile uint8_t *)0x40073012) // CMP Filter Period Register
  1533. #define CMP2_SCR (*(volatile uint8_t *)0x40073013) // CMP Status and Control Register
  1534. #define CMP2_DACCR (*(volatile uint8_t *)0x40073014) // DAC Control Register
  1535. #define CMP2_MUXCR (*(volatile uint8_t *)0x40073015) // MUX Control Register
  1536. // Chapter 33: Voltage Reference (VREFV1)
  1537. #define VREF_TRM (*(volatile uint8_t *)0x40074000) // VREF Trim Register
  1538. #define VREF_TRM_CHOPEN ((uint8_t)0x40) // Chop oscillator enable
  1539. #define VREF_TRM_TRIM(n) ((n) & 0x3F) // Trim bits
  1540. #define VREF_SC (*(volatile uint8_t *)0x40074001) // VREF Status and Control Register
  1541. #define VREF_SC_VREFEN ((uint8_t)0x80) // Internal Voltage Reference enable
  1542. #define VREF_SC_REGEN ((uint8_t)0x40) // Regulator enable
  1543. #define VREF_SC_ICOMPEN ((uint8_t)0x20) // Second order curvature compensation enable
  1544. #define VREF_SC_VREFST ((uint8_t)0x04) // Internal Voltage Reference stable flag
  1545. #define VREF_SC_MODE_LV(n) (uint8_t)(((n) & 3) << 0) // Buffer Mode selection: 0=Bandgap on only
  1546. // 1=High power buffer mode,
  1547. // 2=Low-power buffer mode
  1548. // Chapter 34: Programmable Delay Block (PDB)
  1549. #define PDB0_SC (*(volatile uint32_t *)0x40036000) // Status and Control Register
  1550. #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select
  1551. #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable
  1552. #define PDB_SC_SWTRIG 0x00010000 // Software Trigger
  1553. #define PDB_SC_DMAEN 0x00008000 // DMA Enable
  1554. #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select
  1555. #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select
  1556. #define PDB_SC_PDBEN 0x00000080 // PDB Enable
  1557. #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag
  1558. #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable.
  1559. #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor
  1560. #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable
  1561. #define PDB_SC_LDOK 0x00000001 // Load OK
  1562. #define PDB0_MOD (*(volatile uint32_t *)0x40036004) // Modulus Register
  1563. #define PDB0_CNT (*(volatile uint32_t *)0x40036008) // Counter Register
  1564. #define PDB0_IDLY (*(volatile uint32_t *)0x4003600C) // Interrupt Delay Register
  1565. #define PDB0_CH0C1 (*(volatile uint32_t *)0x40036010) // Channel n Control Register 1
  1566. #define PDB0_CH0S (*(volatile uint32_t *)0x40036014) // Channel n Status Register
  1567. #define PDB0_CH0DLY0 (*(volatile uint32_t *)0x40036018) // Channel n Delay 0 Register
  1568. #define PDB0_CH0DLY1 (*(volatile uint32_t *)0x4003601C) // Channel n Delay 1 Register
  1569. #define PDB0_POEN (*(volatile uint32_t *)0x40036190) // Pulse-Out n Enable Register
  1570. #define PDB0_PO0DLY (*(volatile uint32_t *)0x40036194) // Pulse-Out n Delay Register
  1571. #define PDB0_PO1DLY (*(volatile uint32_t *)0x40036198) // Pulse-Out n Delay Register
  1572. // Chapter 35: FlexTimer Module (FTM)
  1573. #define FTM0_SC (*(volatile uint32_t *)0x40038000) // Status And Control
  1574. #define FTM_SC_TOF 0x80 // Timer Overflow Flag
  1575. #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable
  1576. #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select
  1577. #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection
  1578. #define FTM_SC_CLKS_MASK 0x18
  1579. #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection
  1580. #define FTM_SC_PS_MASK 0x07
  1581. #define FTM0_CNT (*(volatile uint32_t *)0x40038004) // Counter
  1582. #define FTM0_MOD (*(volatile uint32_t *)0x40038008) // Modulo
  1583. #define FTM0_C0SC (*(volatile uint32_t *)0x4003800C) // Channel 0 Status And Control
  1584. #define FTM_CSC_CHF 0x80 // Channel Flag
  1585. #define FTM_CSC_CHIE 0x40 // Channel Interrupt Enable
  1586. #define FTM_CSC_MSB 0x20 // Channel Mode Select
  1587. #define FTM_CSC_MSA 0x10 // Channel Mode Select
  1588. #define FTM_CSC_ELSB 0x08 // Edge or Level Select
  1589. #define FTM_CSC_ELSA 0x04 // Edge or Level Select
  1590. #define FTM_CSC_DMA 0x01 // DMA Enable
  1591. #define FTM0_C0V (*(volatile uint32_t *)0x40038010) // Channel 0 Value
  1592. #define FTM0_C1SC (*(volatile uint32_t *)0x40038014) // Channel 1 Status And Control
  1593. #define FTM0_C1V (*(volatile uint32_t *)0x40038018) // Channel 1 Value
  1594. #define FTM0_C2SC (*(volatile uint32_t *)0x4003801C) // Channel 2 Status And Control
  1595. #define FTM0_C2V (*(volatile uint32_t *)0x40038020) // Channel 2 Value
  1596. #define FTM0_C3SC (*(volatile uint32_t *)0x40038024) // Channel 3 Status And Control
  1597. #define FTM0_C3V (*(volatile uint32_t *)0x40038028) // Channel 3 Value
  1598. #define FTM0_C4SC (*(volatile uint32_t *)0x4003802C) // Channel 4 Status And Control
  1599. #define FTM0_C4V (*(volatile uint32_t *)0x40038030) // Channel 4 Value
  1600. #define FTM0_C5SC (*(volatile uint32_t *)0x40038034) // Channel 5 Status And Control
  1601. #define FTM0_C5V (*(volatile uint32_t *)0x40038038) // Channel 5 Value
  1602. #define FTM0_C6SC (*(volatile uint32_t *)0x4003803C) // Channel 6 Status And Control
  1603. #define FTM0_C6V (*(volatile uint32_t *)0x40038040) // Channel 6 Value
  1604. #define FTM0_C7SC (*(volatile uint32_t *)0x40038044) // Channel 7 Status And Control
  1605. #define FTM0_C7V (*(volatile uint32_t *)0x40038048) // Channel 7 Value
  1606. #define FTM0_CNTIN (*(volatile uint32_t *)0x4003804C) // Counter Initial Value
  1607. #define FTM0_STATUS (*(volatile uint32_t *)0x40038050) // Capture And Compare Status
  1608. #define FTM_STATUS_CH7F 0x80 //
  1609. #define FTM_STATUS_CH6F 0x40 //
  1610. #define FTM_STATUS_CH5F 0x20 //
  1611. #define FTM_STATUS_CH4F 0x10 //
  1612. #define FTM_STATUS_CH3F 0x08 //
  1613. #define FTM_STATUS_CH2F 0x04 //
  1614. #define FTM_STATUS_CH1F 0x02 //
  1615. #define FTM_STATUS_CH0F 0x01 //
  1616. #define FTM0_MODE (*(volatile uint32_t *)0x40038054) // Features Mode Selection
  1617. #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
  1618. #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
  1619. #define FTM_MODE_FAULTM_MASK 0x60
  1620. #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
  1621. #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
  1622. #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
  1623. #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
  1624. #define FTM_MODE_FTMEN 0x01 // FTM Enable
  1625. #define FTM0_SYNC (*(volatile uint32_t *)0x40038058) // Synchronization
  1626. #define FTM_SYNC_SWSYNC 0x80 //
  1627. #define FTM_SYNC_TRIG2 0x40 //
  1628. #define FTM_SYNC_TRIG1 0x20 //
  1629. #define FTM_SYNC_TRIG0 0x10 //
  1630. #define FTM_SYNC_SYNCHOM 0x08 //
  1631. #define FTM_SYNC_REINIT 0x04 //
  1632. #define FTM_SYNC_CNTMAX 0x02 //
  1633. #define FTM_SYNC_CNTMIN 0x01 //
  1634. #define FTM0_OUTINIT (*(volatile uint32_t *)0x4003805C) // Initial State For Channels Output
  1635. #define FTM_OUTINIT_CH7OI 0x80 //
  1636. #define FTM_OUTINIT_CH6OI 0x40 //
  1637. #define FTM_OUTINIT_CH5OI 0x20 //
  1638. #define FTM_OUTINIT_CH4OI 0x10 //
  1639. #define FTM_OUTINIT_CH3OI 0x08 //
  1640. #define FTM_OUTINIT_CH2OI 0x04 //
  1641. #define FTM_OUTINIT_CH1OI 0x02 //
  1642. #define FTM_OUTINIT_CH0OI 0x01 //
  1643. #define FTM0_OUTMASK (*(volatile uint32_t *)0x40038060) // Output Mask
  1644. #define FTM_OUTMASK_CH7OM 0x80 //
  1645. #define FTM_OUTMASK_CH6OM 0x40 //
  1646. #define FTM_OUTMASK_CH5OM 0x20 //
  1647. #define FTM_OUTMASK_CH4OM 0x10 //
  1648. #define FTM_OUTMASK_CH3OM 0x08 //
  1649. #define FTM_OUTMASK_CH2OM 0x04 //
  1650. #define FTM_OUTMASK_CH1OM 0x02 //
  1651. #define FTM_OUTMASK_CH0OM 0x01 //
  1652. #define FTM0_COMBINE (*(volatile uint32_t *)0x40038064) // Function For Linked Channels
  1653. #define FTM_COMBINE_FAULTEN3 0x40000000 // Enable the fault control, ch #6 & #7
  1654. #define FTM_COMBINE_SYNCEN3 0x20000000 // Enable PWM sync of C6V & C7V
  1655. #define FTM_COMBINE_DTEN3 0x10000000 // Enable deadtime insertion, ch #6 & #7
  1656. #define FTM_COMBINE_DECAP3 0x08000000 // Dual Edge Capture Mode
  1657. #define FTM_COMBINE_DECAPEN3 0x04000000 // Dual Edge Capture Mode Enable
  1658. #define FTM_COMBINE_COMP3 0x02000000 // Complement Of Channel #6 & #7
  1659. #define FTM_COMBINE_COMBINE3 0x01000000 // Combine Channels #6 & #7
  1660. #define FTM_COMBINE_FAULTEN2 0x00400000 // Enable the fault control, ch #4 & #5
  1661. #define FTM_COMBINE_SYNCEN2 0x00200000 // Enable PWM sync of C4V & C5V
  1662. #define FTM_COMBINE_DTEN2 0x00100000 // Enable deadtime insertion, ch #4 & #5
  1663. #define FTM_COMBINE_DECAP2 0x00080000 // Dual Edge Capture Mode
  1664. #define FTM_COMBINE_DECAPEN2 0x00040000 // Dual Edge Capture Mode Enable
  1665. #define FTM_COMBINE_COMP2 0x00020000 // Complement Of Channel #4 & #5
  1666. #define FTM_COMBINE_COMBINE2 0x00010000 // Combine Channels #4 & #5
  1667. #define FTM_COMBINE_FAULTEN1 0x00004000 // Enable the fault control, ch #2 & #3
  1668. #define FTM_COMBINE_SYNCEN1 0x00002000 // Enable PWM sync of C2V & C3V
  1669. #define FTM_COMBINE_DTEN1 0x00001000 // Enable deadtime insertion, ch #2 & #3
  1670. #define FTM_COMBINE_DECAP1 0x00000800 // Dual Edge Capture Mode
  1671. #define FTM_COMBINE_DECAPEN1 0x00000400 // Dual Edge Capture Mode Enable
  1672. #define FTM_COMBINE_COMP1 0x00000200 // Complement Of Channel #2 & #3
  1673. #define FTM_COMBINE_COMBINE1 0x00000100 // Combine Channels #2 & #3
  1674. #define FTM_COMBINE_FAULTEN0 0x00000040 // Enable the fault control, ch #0 & #1
  1675. #define FTM_COMBINE_SYNCEN0 0x00000020 // Enable PWM sync of C0V & C1V
  1676. #define FTM_COMBINE_DTEN0 0x00000010 // Enable deadtime insertion, ch #0 & #1
  1677. #define FTM_COMBINE_DECAP0 0x00000008 // Dual Edge Capture Mode
  1678. #define FTM_COMBINE_DECAPEN0 0x00000004 // Dual Edge Capture Mode Enable
  1679. #define FTM_COMBINE_COMP0 0x00000002 // Complement Of Channel #0 & #1
  1680. #define FTM_COMBINE_COMBINE0 0x00000001 // Combine Channels #0 & #1
  1681. #define FTM0_DEADTIME (*(volatile uint32_t *)0x40038068) // Deadtime Insertion Control
  1682. #define FTM_DEADTIME_DTPS(n) (((n) & 3) << 6) // Prescaler Value, 0=1x, 2=4x, 3=16x
  1683. #define FTM_DEADTIME_DTPS_MASK 0xC0
  1684. #define FTM_DEADTIME_DTVAL(n) (((n) & 63) << 0) // Deadtime Value
  1685. #define FTM_DEADTIME_DTVAL_MASK 0x3F
  1686. #define FTM0_EXTTRIG (*(volatile uint32_t *)0x4003806C) // FTM External Trigger
  1687. #define FTM_EXTTRIG_TRIGF 0x80 // Channel Trigger Flag
  1688. #define FTM_EXTTRIG_INITTRIGEN 0x40 // Initialization Trigger Enable
  1689. #define FTM_EXTTRIG_CH1TRIG 0x20 // Channel 1 Trigger Enable
  1690. #define FTM_EXTTRIG_CH0TRIG 0x10 // Channel 0 Trigger Enable
  1691. #define FTM_EXTTRIG_CH5TRIG 0x08 // Channel 5 Trigger Enable
  1692. #define FTM_EXTTRIG_CH4TRIG 0x04 // Channel 4 Trigger Enable
  1693. #define FTM_EXTTRIG_CH3TRIG 0x02 // Channel 3 Trigger Enable
  1694. #define FTM_EXTTRIG_CH2TRIG 0x01 // Channel 2 Trigger Enable
  1695. #define FTM0_POL (*(volatile uint32_t *)0x40038070) // Channels Polarity
  1696. #define FTM_POL_POL7 0x80 // Channel 7 Polarity, 0=active high, 1=active low
  1697. #define FTM_POL_POL6 0x40 // Channel 6 Polarity, 0=active high, 1=active low
  1698. #define FTM_POL_POL5 0x20 // Channel 5 Polarity, 0=active high, 1=active low
  1699. #define FTM_POL_POL4 0x10 // Channel 4 Polarity, 0=active high, 1=active low
  1700. #define FTM_POL_POL3 0x08 // Channel 3 Polarity, 0=active high, 1=active low
  1701. #define FTM_POL_POL2 0x04 // Channel 2 Polarity, 0=active high, 1=active low
  1702. #define FTM_POL_POL1 0x02 // Channel 1 Polarity, 0=active high, 1=active low
  1703. #define FTM_POL_POL0 0x01 // Channel 0 Polarity, 0=active high, 1=active low
  1704. #define FTM0_FMS (*(volatile uint32_t *)0x40038074) // Fault Mode Status
  1705. #define FTM_FMS_FAULTF 0x80 // Fault Detection Flag
  1706. #define FTM_FMS_WPEN 0x40 // Write Protection Enable
  1707. #define FTM_FMS_FAULTIN 0x20 // Fault Inputs
  1708. #define FTM_FMS_FAULTF3 0x08 // Fault Detection Flag 3
  1709. #define FTM_FMS_FAULTF2 0x04 // Fault Detection Flag 2
  1710. #define FTM_FMS_FAULTF1 0x02 // Fault Detection Flag 1
  1711. #define FTM_FMS_FAULTF0 0x01 // Fault Detection Flag 0
  1712. #define FTM0_FILTER (*(volatile uint32_t *)0x40038078) // Input Capture Filter Control
  1713. #define FTM_FILTER_CH3FVAL(n) (((n) & 15) << 12) // Channel 3 Input Filter
  1714. #define FTM_FILTER_CH2FVAL(n) (((n) & 15) << 8) // Channel 2 Input Filter
  1715. #define FTM_FILTER_CH1FVAL(n) (((n) & 15) << 4) // Channel 1 Input Filter
  1716. #define FTM_FILTER_CH0FVAL(n) (((n) & 15) << 0) // Channel 0 Input Filter
  1717. #define FTM_FILTER_CH3FVAL_MASK 0xF000
  1718. #define FTM_FILTER_CH2FVAL_MASK 0x0F00
  1719. #define FTM_FILTER_CH1FVAL_MASK 0x00F0
  1720. #define FTM_FILTER_CH0FVAL_MASK 0x000F
  1721. #define FTM0_FLTCTRL (*(volatile uint32_t *)0x4003807C) // Fault Control
  1722. #define FTM_FLTCTRL_FFVAL(n) (((n) & 15) << 8) // Fault Input Filter Value, 0=disable
  1723. #define FTM_FLTCTRL_FFVAL_MASK 0xF00
  1724. #define FTM_FLTCTRL_FFLTR3EN 0x80 // Fault Input 3 Filter Enable
  1725. #define FTM_FLTCTRL_FFLTR2EN 0x40 // Fault Input 2 Filter Enable
  1726. #define FTM_FLTCTRL_FFLTR1EN 0x20 // Fault Input 1 Filter Enable
  1727. #define FTM_FLTCTRL_FFLTR0EN 0x10 // Fault Input 0 Filter Enable
  1728. #define FTM_FLTCTRL_FAULT3EN 0x08 // Fault Input 3 Enable
  1729. #define FTM_FLTCTRL_FAULT2EN 0x04 // Fault Input 2 Enable
  1730. #define FTM_FLTCTRL_FAULT1EN 0x02 // Fault Input 1 Enable
  1731. #define FTM_FLTCTRL_FAULT0EN 0x01 // Fault Input 0 Enable
  1732. #define FTM0_QDCTRL (*(volatile uint32_t *)0x40038080) // Quadrature Decoder Control And Status
  1733. #define FTM_QDCTRL_PHAFLTREN 0x80 // Phase A Input Filter Enable
  1734. #define FTM_QDCTRL_PHBFLTREN 0x40 // Phase B Input Filter Enable
  1735. #define FTM_QDCTRL_PHAPOL 0x20 // Phase A Input Polarity
  1736. #define FTM_QDCTRL_PHBPOL 0x10 // Phase B Input Polarity
  1737. #define FTM_QDCTRL_QUADMODE 0x08 // Quadrature Decoder Mode
  1738. #define FTM_QDCTRL_QUADIR 0x04 // FTM Counter Direction In Quadrature Decoder Mode
  1739. #define FTM_QDCTRL_TOFDIR 0x02 // Timer Overflow Direction In Quadrature Decoder Mode
  1740. #define FTM_QDCTRL_QUADEN 0x01 // Quadrature Decoder Mode Enable
  1741. #define FTM0_CONF (*(volatile uint32_t *)0x40038084) // Configuration
  1742. #define FTM_CONF_GTBEOUT 0x400 // Global Time Base Output
  1743. #define FTM_CONF_GTBEEN 0x200 // Global Time Base Enable
  1744. #define FTM_CONF_BDMMODE (((n) & 3) << 6) // Behavior when in debug mode
  1745. #define FTM_CONF_NUMTOF (((n) & 31) << 0) // ratio of counter overflows to TOF bit set
  1746. #define FTM0_FLTPOL (*(volatile uint32_t *)0x40038088) // FTM Fault Input Polarity
  1747. #define FTM_FLTPOL_FLT3POL 0x08 // Fault Input 3 Polarity
  1748. #define FTM_FLTPOL_FLT2POL 0x04 // Fault Input 2 Polarity
  1749. #define FTM_FLTPOL_FLT1POL 0x02 // Fault Input 1 Polarity
  1750. #define FTM_FLTPOL_FLT0POL 0x01 // Fault Input 0 Polarity
  1751. #define FTM0_SYNCONF (*(volatile uint32_t *)0x4003808C) // Synchronization Configuration
  1752. #define FTM_SYNCONF_HWSOC 0x100000 // Software output control synchronization is activated by a hardware trigger.
  1753. #define FTM_SYNCONF_HWINVC 0x080000 // Inverting control synchronization is activated by a hardware trigger.
  1754. #define FTM_SYNCONF_HWOM 0x040000 // Output mask synchronization is activated by a hardware trigger.
  1755. #define FTM_SYNCONF_HWWRBUF 0x020000 // MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
  1756. #define FTM_SYNCONF_HWRSTCNT 0x010000 // FTM counter synchronization is activated by a hardware trigger.
  1757. #define FTM_SYNCONF_SWSOC 0x001000 // Software output control synchronization is activated by the software trigger.
  1758. #define FTM_SYNCONF_SWINVC 0x000800 // Inverting control synchronization is activated by the software trigger.
  1759. #define FTM_SYNCONF_SWOM 0x000400 // Output mask synchronization is activated by the software trigger.
  1760. #define FTM_SYNCONF_SWWRBUF 0x000200 // MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
  1761. #define FTM_SYNCONF_SWRSTCNT 0x000100 // FTM counter synchronization is activated by the software trigger.
  1762. #define FTM_SYNCONF_SYNCMODE 0x000080 // Synchronization Mode, 0=Legacy, 1=Enhanced PWM
  1763. #define FTM_SYNCONF_SWOC 0x000020 // SWOCTRL Register Synchronization
  1764. #define FTM_SYNCONF_INVC 0x000010 // INVCTRL Register Synchronization
  1765. #define FTM_SYNCONF_CNTINC 0x000004 // CNTIN Register Synchronization
  1766. #define FTM_SYNCONF_HWTRIGMODE 0x000001 // Hardware Trigger Mode
  1767. #define FTM0_INVCTRL (*(volatile uint32_t *)0x40038090) // FTM Inverting Control
  1768. #define FTM_INVCTRL_INV3EN 0x08 // Pair Channels 3 Inverting Enable
  1769. #define FTM_INVCTRL_INV2EN 0x04 // Pair Channels 2 Inverting Enable
  1770. #define FTM_INVCTRL_INV1EN 0x02 // Pair Channels 1 Inverting Enable
  1771. #define FTM_INVCTRL_INV0EN 0x01 // Pair Channels 0 Inverting Enable
  1772. #define FTM0_SWOCTRL (*(volatile uint32_t *)0x40038094) // FTM Software Output Control
  1773. #define FTM_SWOCTRL_CH7OCV 0x8000 // Channel 7 Software Output Control Value
  1774. #define FTM_SWOCTRL_CH6OCV 0x4000 // Channel 6 Software Output Control Value
  1775. #define FTM_SWOCTRL_CH5OCV 0x2000 // Channel 5 Software Output Control Value
  1776. #define FTM_SWOCTRL_CH4OCV 0x1000 // Channel 4 Software Output Control Value
  1777. #define FTM_SWOCTRL_CH3OCV 0x0800 // Channel 3 Software Output Control Value
  1778. #define FTM_SWOCTRL_CH2OCV 0x0400 // Channel 2 Software Output Control Value
  1779. #define FTM_SWOCTRL_CH1OCV 0x0200 // Channel 1 Software Output Control Value
  1780. #define FTM_SWOCTRL_CH0OCV 0x0100 // Channel 0 Software Output Control Value
  1781. #define FTM_SWOCTRL_CH7OC 0x0080 // Channel 7 Software Output Control Enable
  1782. #define FTM_SWOCTRL_CH6OC 0x0040 // Channel 6 Software Output Control Enable
  1783. #define FTM_SWOCTRL_CH5OC 0x0020 // Channel 5 Software Output Control Enable
  1784. #define FTM_SWOCTRL_CH4OC 0x0010 // Channel 4 Software Output Control Enable
  1785. #define FTM_SWOCTRL_CH3OC 0x0008 // Channel 3 Software Output Control Enable
  1786. #define FTM_SWOCTRL_CH2OC 0x0004 // Channel 2 Software Output Control Enable
  1787. #define FTM_SWOCTRL_CH1OC 0x0002 // Channel 1 Software Output Control Enable
  1788. #define FTM_SWOCTRL_CH0OC 0x0001 // Channel 0 Software Output Control Enable
  1789. #define FTM0_PWMLOAD (*(volatile uint32_t *)0x40038098) // FTM PWM Load
  1790. #define FTM_PWMLOAD_LDOK 0x200 // Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers
  1791. #define FTM_PWMLOAD_CH7SEL 0x80 // Channel 7 Select
  1792. #define FTM_PWMLOAD_CH6SEL 0x40 // Channel 6 Select
  1793. #define FTM_PWMLOAD_CH5SEL 0x20 // Channel 5 Select
  1794. #define FTM_PWMLOAD_CH4SEL 0x10 // Channel 4 Select
  1795. #define FTM_PWMLOAD_CH3SEL 0x08 // Channel 4 Select
  1796. #define FTM_PWMLOAD_CH2SEL 0x04 // Channel 3 Select
  1797. #define FTM_PWMLOAD_CH1SEL 0x02 // Channel 2 Select
  1798. #define FTM_PWMLOAD_CH0SEL 0x01 // Channel 1 Select
  1799. #define FTM1_SC (*(volatile uint32_t *)0x40039000) // Status And Control
  1800. #define FTM1_CNT (*(volatile uint32_t *)0x40039004) // Counter
  1801. #define FTM1_MOD (*(volatile uint32_t *)0x40039008) // Modulo
  1802. #define FTM1_C0SC (*(volatile uint32_t *)0x4003900C) // Channel 0 Status And Control
  1803. #define FTM1_C0V (*(volatile uint32_t *)0x40039010) // Channel 0 Value
  1804. #define FTM1_C1SC (*(volatile uint32_t *)0x40039014) // Channel 1 Status And Control
  1805. #define FTM1_C1V (*(volatile uint32_t *)0x40039018) // Channel 1 Value
  1806. #define FTM1_CNTIN (*(volatile uint32_t *)0x4003904C) // Counter Initial Value
  1807. #define FTM1_STATUS (*(volatile uint32_t *)0x40039050) // Capture And Compare Status
  1808. #define FTM1_MODE (*(volatile uint32_t *)0x40039054) // Features Mode Selection
  1809. #define FTM1_SYNC (*(volatile uint32_t *)0x40039058) // Synchronization
  1810. #define FTM1_OUTINIT (*(volatile uint32_t *)0x4003905C) // Initial State For Channels Output
  1811. #define FTM1_OUTMASK (*(volatile uint32_t *)0x40039060) // Output Mask
  1812. #define FTM1_COMBINE (*(volatile uint32_t *)0x40039064) // Function For Linked Channels
  1813. #define FTM1_DEADTIME (*(volatile uint32_t *)0x40039068) // Deadtime Insertion Control
  1814. #define FTM1_EXTTRIG (*(volatile uint32_t *)0x4003906C) // FTM External Trigger
  1815. #define FTM1_POL (*(volatile uint32_t *)0x40039070) // Channels Polarity
  1816. #define FTM1_FMS (*(volatile uint32_t *)0x40039074) // Fault Mode Status
  1817. #define FTM1_FILTER (*(volatile uint32_t *)0x40039078) // Input Capture Filter Control
  1818. #define FTM1_FLTCTRL (*(volatile uint32_t *)0x4003907C) // Fault Control
  1819. #define FTM1_QDCTRL (*(volatile uint32_t *)0x40039080) // Quadrature Decoder Control And Status
  1820. #define FTM1_CONF (*(volatile uint32_t *)0x40039084) // Configuration
  1821. #define FTM1_FLTPOL (*(volatile uint32_t *)0x40039088) // FTM Fault Input Polarity
  1822. #define FTM1_SYNCONF (*(volatile uint32_t *)0x4003908C) // Synchronization Configuration
  1823. #define FTM1_INVCTRL (*(volatile uint32_t *)0x40039090) // FTM Inverting Control
  1824. #define FTM1_SWOCTRL (*(volatile uint32_t *)0x40039094) // FTM Software Output Control
  1825. #define FTM1_PWMLOAD (*(volatile uint32_t *)0x40039098) // FTM PWM Load
  1826. #if defined(KINETISK)
  1827. #define FTM2_SC (*(volatile uint32_t *)0x400B8000) // Status And Control
  1828. #define FTM2_CNT (*(volatile uint32_t *)0x400B8004) // Counter
  1829. #define FTM2_MOD (*(volatile uint32_t *)0x400B8008) // Modulo
  1830. #define FTM2_C0SC (*(volatile uint32_t *)0x400B800C) // Channel 0 Status And Control
  1831. #define FTM2_C0V (*(volatile uint32_t *)0x400B8010) // Channel 0 Value
  1832. #define FTM2_C1SC (*(volatile uint32_t *)0x400B8014) // Channel 1 Status And Control
  1833. #define FTM2_C1V (*(volatile uint32_t *)0x400B8018) // Channel 1 Value
  1834. #define FTM2_CNTIN (*(volatile uint32_t *)0x400B804C) // Counter Initial Value
  1835. #define FTM2_STATUS (*(volatile uint32_t *)0x400B8050) // Capture And Compare Status
  1836. #define FTM2_MODE (*(volatile uint32_t *)0x400B8054) // Features Mode Selection
  1837. #define FTM2_SYNC (*(volatile uint32_t *)0x400B8058) // Synchronization
  1838. #define FTM2_OUTINIT (*(volatile uint32_t *)0x400B805C) // Initial State For Channels Output
  1839. #define FTM2_OUTMASK (*(volatile uint32_t *)0x400B8060) // Output Mask
  1840. #define FTM2_COMBINE (*(volatile uint32_t *)0x400B8064) // Function For Linked Channels
  1841. #define FTM2_DEADTIME (*(volatile uint32_t *)0x400B8068) // Deadtime Insertion Control
  1842. #define FTM2_EXTTRIG (*(volatile uint32_t *)0x400B806C) // FTM External Trigger
  1843. #define FTM2_POL (*(volatile uint32_t *)0x400B8070) // Channels Polarity
  1844. #define FTM2_FMS (*(volatile uint32_t *)0x400B8074) // Fault Mode Status
  1845. #define FTM2_FILTER (*(volatile uint32_t *)0x400B8078) // Input Capture Filter Control
  1846. #define FTM2_FLTCTRL (*(volatile uint32_t *)0x400B807C) // Fault Control
  1847. #define FTM2_QDCTRL (*(volatile uint32_t *)0x400B8080) // Quadrature Decoder Control And Status
  1848. #define FTM2_CONF (*(volatile uint32_t *)0x400B8084) // Configuration
  1849. #define FTM2_FLTPOL (*(volatile uint32_t *)0x400B8088) // FTM Fault Input Polarity
  1850. #define FTM2_SYNCONF (*(volatile uint32_t *)0x400B808C) // Synchronization Configuration
  1851. #define FTM2_INVCTRL (*(volatile uint32_t *)0x400B8090) // FTM Inverting Control
  1852. #define FTM2_SWOCTRL (*(volatile uint32_t *)0x400B8094) // FTM Software Output Control
  1853. #define FTM2_PWMLOAD (*(volatile uint32_t *)0x400B8098) // FTM PWM Load
  1854. #elif defined(KINETISL)
  1855. #define FTM2_SC (*(volatile uint32_t *)0x4003A000) // Status And Control
  1856. #define FTM2_CNT (*(volatile uint32_t *)0x4003A004) // Counter
  1857. #define FTM2_MOD (*(volatile uint32_t *)0x4003A008) // Modulo
  1858. #define FTM2_C0SC (*(volatile uint32_t *)0x4003A00C) // Channel 0 Status And Control
  1859. #define FTM2_C0V (*(volatile uint32_t *)0x4003A010) // Channel 0 Value
  1860. #define FTM2_C1SC (*(volatile uint32_t *)0x4003A014) // Channel 1 Status And Control
  1861. #define FTM2_C1V (*(volatile uint32_t *)0x4003A018) // Channel 1 Value
  1862. #define FTM2_STATUS (*(volatile uint32_t *)0x4003A050) // Capture And Compare Status
  1863. #define FTM2_CONF (*(volatile uint32_t *)0x4003A084) // Configuration
  1864. #endif
  1865. // Chapter 36: Periodic Interrupt Timer (PIT)
  1866. #define PIT_MCR (*(volatile uint32_t *)0x40037000) // PIT Module Control Register
  1867. #define PIT_LDVAL0 (*(volatile uint32_t *)0x40037100) // Timer Load Value Register
  1868. #define PIT_CVAL0 (*(volatile uint32_t *)0x40037104) // Current Timer Value Register
  1869. #define PIT_TCTRL0 (*(volatile uint32_t *)0x40037108) // Timer Control Register
  1870. #define PIT_TFLG0 (*(volatile uint32_t *)0x4003710C) // Timer Flag Register
  1871. #define PIT_LDVAL1 (*(volatile uint32_t *)0x40037110) // Timer Load Value Register
  1872. #define PIT_CVAL1 (*(volatile uint32_t *)0x40037114) // Current Timer Value Register
  1873. #define PIT_TCTRL1 (*(volatile uint32_t *)0x40037118) // Timer Control Register
  1874. #define PIT_TFLG1 (*(volatile uint32_t *)0x4003711C) // Timer Flag Register
  1875. #define PIT_LDVAL2 (*(volatile uint32_t *)0x40037120) // Timer Load Value Register
  1876. #define PIT_CVAL2 (*(volatile uint32_t *)0x40037124) // Current Timer Value Register
  1877. #define PIT_TCTRL2 (*(volatile uint32_t *)0x40037128) // Timer Control Register
  1878. #define PIT_TFLG2 (*(volatile uint32_t *)0x4003712C) // Timer Flag Register
  1879. #define PIT_LDVAL3 (*(volatile uint32_t *)0x40037130) // Timer Load Value Register
  1880. #define PIT_CVAL3 (*(volatile uint32_t *)0x40037134) // Current Timer Value Register
  1881. #define PIT_TCTRL3 (*(volatile uint32_t *)0x40037138) // Timer Control Register
  1882. #define PIT_TFLG3 (*(volatile uint32_t *)0x4003713C) // Timer Flag Register
  1883. // Chapter 37: Low-Power Timer (LPTMR)
  1884. #define LPTMR0_CSR (*(volatile uint32_t *)0x40040000) // Low Power Timer Control Status Register
  1885. #define LPTMR_CSR_TCF 0x80 // Compare Flag
  1886. #define LPTMR_CSR_TIE 0x40 // Interrupt Enable
  1887. #define LPTMR_CSR_TPS(n) (((n) & 3) << 4) // Pin: 0=CMP0, 1=xtal, 2=pin13
  1888. #define LPTMR_CSR_TPP 0x08 // Pin Polarity
  1889. #define LPTMR_CSR_TFC 0x04 // Free-Running Counter
  1890. #define LPTMR_CSR_TMS 0x02 // Mode Select, 0=timer, 1=counter
  1891. #define LPTMR_CSR_TEN 0x01 // Enable
  1892. #define LPTMR0_PSR (*(volatile uint32_t *)0x40040004) // Low Power Timer Prescale Register
  1893. #define LPTMR_PSR_PRESCALE(n) (((n) & 15) << 3) // Prescaler value
  1894. #define LPTMR_PSR_PBYP 0x04 // Prescaler bypass
  1895. #define LPTMR_PSR_PCS(n) (((n) & 3) << 0) // Clock: 0=MCGIRCLK, 1=LPO(1kHz), 2=ERCLK32K, 3=OSCERCLK
  1896. #define LPTMR0_CMR (*(volatile uint32_t *)0x40040008) // Low Power Timer Compare Register
  1897. #define LPTMR0_CNR (*(volatile uint32_t *)0x4004000C) // Low Power Timer Counter Register
  1898. // Chapter 38: Carrier Modulator Transmitter (CMT)
  1899. #define CMT_CGH1 (*(volatile uint8_t *)0x40062000) // CMT Carrier Generator High Data Register 1
  1900. #define CMT_CGL1 (*(volatile uint8_t *)0x40062001) // CMT Carrier Generator Low Data Register 1
  1901. #define CMT_CGH2 (*(volatile uint8_t *)0x40062002) // CMT Carrier Generator High Data Register 2
  1902. #define CMT_CGL2 (*(volatile uint8_t *)0x40062003) // CMT Carrier Generator Low Data Register 2
  1903. #define CMT_OC (*(volatile uint8_t *)0x40062004) // CMT Output Control Register
  1904. #define CMT_MSC (*(volatile uint8_t *)0x40062005) // CMT Modulator Status and Control Register
  1905. #define CMT_CMD1 (*(volatile uint8_t *)0x40062006) // CMT Modulator Data Register Mark High
  1906. #define CMT_CMD2 (*(volatile uint8_t *)0x40062007) // CMT Modulator Data Register Mark Low
  1907. #define CMT_CMD3 (*(volatile uint8_t *)0x40062008) // CMT Modulator Data Register Space High
  1908. #define CMT_CMD4 (*(volatile uint8_t *)0x40062009) // CMT Modulator Data Register Space Low
  1909. #define CMT_PPS (*(volatile uint8_t *)0x4006200A) // CMT Primary Prescaler Register
  1910. #define CMT_DMA (*(volatile uint8_t *)0x4006200B) // CMT Direct Memory Access Register
  1911. // Chapter 39: Real Time Clock (RTC)
  1912. #define RTC_TSR (*(volatile uint32_t *)0x4003D000) // RTC Time Seconds Register
  1913. #define RTC_TPR (*(volatile uint32_t *)0x4003D004) // RTC Time Prescaler Register
  1914. #define RTC_TAR (*(volatile uint32_t *)0x4003D008) // RTC Time Alarm Register
  1915. #define RTC_TCR (*(volatile uint32_t *)0x4003D00C) // RTC Time Compensation Register
  1916. #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
  1917. #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
  1918. #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
  1919. #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
  1920. #define RTC_CR (*(volatile uint32_t *)0x4003D010) // RTC Control Register
  1921. #define RTC_CR_SC2P ((uint32_t)0x00002000) //
  1922. #define RTC_CR_SC4P ((uint32_t)0x00001000) //
  1923. #define RTC_CR_SC8P ((uint32_t)0x00000800) //
  1924. #define RTC_CR_SC16P ((uint32_t)0x00000400) //
  1925. #define RTC_CR_CLKO ((uint32_t)0x00000200) //
  1926. #define RTC_CR_OSCE ((uint32_t)0x00000100) //
  1927. #define RTC_CR_UM ((uint32_t)0x00000008) //
  1928. #define RTC_CR_SUP ((uint32_t)0x00000004) //
  1929. #define RTC_CR_WPE ((uint32_t)0x00000002) //
  1930. #define RTC_CR_SWR ((uint32_t)0x00000001) //
  1931. #define RTC_SR (*(volatile uint32_t *)0x4003D014) // RTC Status Register
  1932. #define RTC_SR_TCE ((uint32_t)0x00000010) //
  1933. #define RTC_SR_TAF ((uint32_t)0x00000004) //
  1934. #define RTC_SR_TOF ((uint32_t)0x00000002) //
  1935. #define RTC_SR_TIF ((uint32_t)0x00000001) //
  1936. #define RTC_LR (*(volatile uint32_t *)0x4003D018) // RTC Lock Register
  1937. #define RTC_IER (*(volatile uint32_t *)0x4003D01C) // RTC Interrupt Enable Register
  1938. #define RTC_WAR (*(volatile uint32_t *)0x4003D800) // RTC Write Access Register
  1939. #define RTC_RAR (*(volatile uint32_t *)0x4003D804) // RTC Read Access Register
  1940. // Chapter 40: Universal Serial Bus OTG Controller (USBOTG)
  1941. #define USB0_PERID (*(const uint8_t *)0x40072000) // Peripheral ID register
  1942. #define USB0_IDCOMP (*(const uint8_t *)0x40072004) // Peripheral ID Complement register
  1943. #define USB0_REV (*(const uint8_t *)0x40072008) // Peripheral Revision register
  1944. #define USB0_ADDINFO (*(volatile uint8_t *)0x4007200C) // Peripheral Additional Info register
  1945. #define USB0_OTGISTAT (*(volatile uint8_t *)0x40072010) // OTG Interrupt Status register
  1946. #define USB_OTGISTAT_IDCHG ((uint8_t)0x80) //
  1947. #define USB_OTGISTAT_ONEMSEC ((uint8_t)0x40) //
  1948. #define USB_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) //
  1949. #define USB_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) //
  1950. #define USB_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) //
  1951. #define USB_OTGISTAT_AVBUSCHG ((uint8_t)0x01) //
  1952. #define USB0_OTGICR (*(volatile uint8_t *)0x40072014) // OTG Interrupt Control Register
  1953. #define USB_OTGICR_IDEN ((uint8_t)0x80) //
  1954. #define USB_OTGICR_ONEMSECEN ((uint8_t)0x40) //
  1955. #define USB_OTGICR_LINESTATEEN ((uint8_t)0x20) //
  1956. #define USB_OTGICR_SESSVLDEN ((uint8_t)0x08) //
  1957. #define USB_OTGICR_BSESSEN ((uint8_t)0x04) //
  1958. #define USB_OTGICR_AVBUSEN ((uint8_t)0x01) //
  1959. #define USB0_OTGSTAT (*(volatile uint8_t *)0x40072018) // OTG Status register
  1960. #define USB_OTGSTAT_ID ((uint8_t)0x80) //
  1961. #define USB_OTGSTAT_ONEMSECEN ((uint8_t)0x40) //
  1962. #define USB_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) //
  1963. #define USB_OTGSTAT_SESS_VLD ((uint8_t)0x08) //
  1964. #define USB_OTGSTAT_BSESSEND ((uint8_t)0x04) //
  1965. #define USB_OTGSTAT_AVBUSVLD ((uint8_t)0x01) //
  1966. #define USB0_OTGCTL (*(volatile uint8_t *)0x4007201C) // OTG Control Register
  1967. #define USB_OTGCTL_DPHIGH ((uint8_t)0x80) //
  1968. #define USB_OTGCTL_DPLOW ((uint8_t)0x20) //
  1969. #define USB_OTGCTL_DMLOW ((uint8_t)0x10) //
  1970. #define USB_OTGCTL_OTGEN ((uint8_t)0x04) //
  1971. #define USB0_ISTAT (*(volatile uint8_t *)0x40072080) // Interrupt Status Register
  1972. #define USB_ISTAT_STALL ((uint8_t)0x80) //
  1973. #define USB_ISTAT_ATTACH ((uint8_t)0x40) //
  1974. #define USB_ISTAT_RESUME ((uint8_t)0x20) //
  1975. #define USB_ISTAT_SLEEP ((uint8_t)0x10) //
  1976. #define USB_ISTAT_TOKDNE ((uint8_t)0x08) //
  1977. #define USB_ISTAT_SOFTOK ((uint8_t)0x04) //
  1978. #define USB_ISTAT_ERROR ((uint8_t)0x02) //
  1979. #define USB_ISTAT_USBRST ((uint8_t)0x01) //
  1980. #define USB0_INTEN (*(volatile uint8_t *)0x40072084) // Interrupt Enable Register
  1981. #define USB_INTEN_STALLEN ((uint8_t)0x80) //
  1982. #define USB_INTEN_ATTACHEN ((uint8_t)0x40) //
  1983. #define USB_INTEN_RESUMEEN ((uint8_t)0x20) //
  1984. #define USB_INTEN_SLEEPEN ((uint8_t)0x10) //
  1985. #define USB_INTEN_TOKDNEEN ((uint8_t)0x08) //
  1986. #define USB_INTEN_SOFTOKEN ((uint8_t)0x04) //
  1987. #define USB_INTEN_ERROREN ((uint8_t)0x02) //
  1988. #define USB_INTEN_USBRSTEN ((uint8_t)0x01) //
  1989. #define USB0_ERRSTAT (*(volatile uint8_t *)0x40072088) // Error Interrupt Status Register
  1990. #define USB_ERRSTAT_BTSERR ((uint8_t)0x80) //
  1991. #define USB_ERRSTAT_DMAERR ((uint8_t)0x20) //
  1992. #define USB_ERRSTAT_BTOERR ((uint8_t)0x10) //
  1993. #define USB_ERRSTAT_DFN8 ((uint8_t)0x08) //
  1994. #define USB_ERRSTAT_CRC16 ((uint8_t)0x04) //
  1995. #define USB_ERRSTAT_CRC5EOF ((uint8_t)0x02) //
  1996. #define USB_ERRSTAT_PIDERR ((uint8_t)0x01) //
  1997. #define USB0_ERREN (*(volatile uint8_t *)0x4007208C) // Error Interrupt Enable Register
  1998. #define USB_ERREN_BTSERREN ((uint8_t)0x80) //
  1999. #define USB_ERREN_DMAERREN ((uint8_t)0x20) //
  2000. #define USB_ERREN_BTOERREN ((uint8_t)0x10) //
  2001. #define USB_ERREN_DFN8EN ((uint8_t)0x08) //
  2002. #define USB_ERREN_CRC16EN ((uint8_t)0x04) //
  2003. #define USB_ERREN_CRC5EOFEN ((uint8_t)0x02) //
  2004. #define USB_ERREN_PIDERREN ((uint8_t)0x01) //
  2005. #define USB0_STAT (*(volatile uint8_t *)0x40072090) // Status Register
  2006. #define USB_STAT_TX ((uint8_t)0x08) //
  2007. #define USB_STAT_ODD ((uint8_t)0x04) //
  2008. #define USB_STAT_ENDP(n) ((uint8_t)((n) >> 4)) //
  2009. #define USB0_CTL (*(volatile uint8_t *)0x40072094) // Control Register
  2010. #define USB_CTL_JSTATE ((uint8_t)0x80) //
  2011. #define USB_CTL_SE0 ((uint8_t)0x40) //
  2012. #define USB_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) //
  2013. #define USB_CTL_RESET ((uint8_t)0x10) //
  2014. #define USB_CTL_HOSTMODEEN ((uint8_t)0x08) //
  2015. #define USB_CTL_RESUME ((uint8_t)0x04) //
  2016. #define USB_CTL_ODDRST ((uint8_t)0x02) //
  2017. #define USB_CTL_USBENSOFEN ((uint8_t)0x01) //
  2018. #define USB0_ADDR (*(volatile uint8_t *)0x40072098) // Address Register
  2019. #define USB0_BDTPAGE1 (*(volatile uint8_t *)0x4007209C) // BDT Page Register 1
  2020. #define USB0_FRMNUML (*(volatile uint8_t *)0x400720A0) // Frame Number Register Low
  2021. #define USB0_FRMNUMH (*(volatile uint8_t *)0x400720A4) // Frame Number Register High
  2022. #define USB0_TOKEN (*(volatile uint8_t *)0x400720A8) // Token Register
  2023. #define USB0_SOFTHLD (*(volatile uint8_t *)0x400720AC) // SOF Threshold Register
  2024. #define USB0_BDTPAGE2 (*(volatile uint8_t *)0x400720B0) // BDT Page Register 2
  2025. #define USB0_BDTPAGE3 (*(volatile uint8_t *)0x400720B4) // BDT Page Register 3
  2026. #define USB0_ENDPT0 (*(volatile uint8_t *)0x400720C0) // Endpoint Control Register
  2027. #define USB_ENDPT_HOSTWOHUB ((uint8_t)0x80) // host only, enable low speed
  2028. #define USB_ENDPT_RETRYDIS ((uint8_t)0x40) // host only, set to disable NAK retry
  2029. #define USB_ENDPT_EPCTLDIS ((uint8_t)0x10) // 0=control, 1=bulk, interrupt, isync
  2030. #define USB_ENDPT_EPRXEN ((uint8_t)0x08) // enables the endpoint for RX transfers.
  2031. #define USB_ENDPT_EPTXEN ((uint8_t)0x04) // enables the endpoint for TX transfers.
  2032. #define USB_ENDPT_EPSTALL ((uint8_t)0x02) // set to stall endpoint
  2033. #define USB_ENDPT_EPHSHK ((uint8_t)0x01) // enable handshaking during a transaction, generally set unless Isochronous
  2034. #define USB0_ENDPT1 (*(volatile uint8_t *)0x400720C4) // Endpoint Control Register
  2035. #define USB0_ENDPT2 (*(volatile uint8_t *)0x400720C8) // Endpoint Control Register
  2036. #define USB0_ENDPT3 (*(volatile uint8_t *)0x400720CC) // Endpoint Control Register
  2037. #define USB0_ENDPT4 (*(volatile uint8_t *)0x400720D0) // Endpoint Control Register
  2038. #define USB0_ENDPT5 (*(volatile uint8_t *)0x400720D4) // Endpoint Control Register
  2039. #define USB0_ENDPT6 (*(volatile uint8_t *)0x400720D8) // Endpoint Control Register
  2040. #define USB0_ENDPT7 (*(volatile uint8_t *)0x400720DC) // Endpoint Control Register
  2041. #define USB0_ENDPT8 (*(volatile uint8_t *)0x400720E0) // Endpoint Control Register
  2042. #define USB0_ENDPT9 (*(volatile uint8_t *)0x400720E4) // Endpoint Control Register
  2043. #define USB0_ENDPT10 (*(volatile uint8_t *)0x400720E8) // Endpoint Control Register
  2044. #define USB0_ENDPT11 (*(volatile uint8_t *)0x400720EC) // Endpoint Control Register
  2045. #define USB0_ENDPT12 (*(volatile uint8_t *)0x400720F0) // Endpoint Control Register
  2046. #define USB0_ENDPT13 (*(volatile uint8_t *)0x400720F4) // Endpoint Control Register
  2047. #define USB0_ENDPT14 (*(volatile uint8_t *)0x400720F8) // Endpoint Control Register
  2048. #define USB0_ENDPT15 (*(volatile uint8_t *)0x400720FC) // Endpoint Control Register
  2049. #define USB0_USBCTRL (*(volatile uint8_t *)0x40072100) // USB Control Register
  2050. #define USB_USBCTRL_SUSP ((uint8_t)0x80) // Places the USB transceiver into the suspend state.
  2051. #define USB_USBCTRL_PDE ((uint8_t)0x40) // Enables the weak pulldowns on the USB transceiver.
  2052. #define USB0_OBSERVE (*(volatile uint8_t *)0x40072104) // USB OTG Observe Register
  2053. #define USB_OBSERVE_DPPU ((uint8_t)0x80) //
  2054. #define USB_OBSERVE_DPPD ((uint8_t)0x40) //
  2055. #define USB_OBSERVE_DMPD ((uint8_t)0x10) //
  2056. #define USB0_CONTROL (*(volatile uint8_t *)0x40072108) // USB OTG Control Register
  2057. #define USB_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
  2058. #define USB0_USBTRC0 (*(volatile uint8_t *)0x4007210C) // USB Transceiver Control Register 0
  2059. #define USB_USBTRC_USBRESET ((uint8_t)0x80) //
  2060. #define USB_USBTRC_USBRESMEN ((uint8_t)0x20) //
  2061. #define USB_USBTRC_SYNC_DET ((uint8_t)0x02) //
  2062. #define USB_USBTRC_USB_RESUME_INT ((uint8_t)0x01) //
  2063. #define USB0_USBFRMADJUST (*(volatile uint8_t *)0x40072114) // Frame Adjust Register
  2064. // Chapter 41: USB Device Charger Detection Module (USBDCD)
  2065. #define USBDCD_CONTROL (*(volatile uint32_t *)0x40035000) // Control register
  2066. #define USBDCD_CLOCK (*(volatile uint32_t *)0x40035004) // Clock register
  2067. #define USBDCD_STATUS (*(volatile uint32_t *)0x40035008) // Status register
  2068. #define USBDCD_TIMER0 (*(volatile uint32_t *)0x40035010) // TIMER0 register
  2069. #define USBDCD_TIMER1 (*(volatile uint32_t *)0x40035014) // TIMER1 register
  2070. #define USBDCD_TIMER2 (*(volatile uint32_t *)0x40035018) // TIMER2 register
  2071. #if defined(KINETISK)
  2072. // Chapter 43: SPI (DSPI)
  2073. typedef struct {
  2074. volatile uint32_t MCR; // 0
  2075. volatile uint32_t unused1;// 4
  2076. volatile uint32_t TCR; // 8
  2077. volatile uint32_t CTAR0; // c
  2078. volatile uint32_t CTAR1; // 10
  2079. volatile uint32_t CTAR2; // 14
  2080. volatile uint32_t CTAR3; // 18
  2081. volatile uint32_t CTAR4; // 1c
  2082. volatile uint32_t CTAR5; // 20
  2083. volatile uint32_t CTAR6; // 24
  2084. volatile uint32_t CTAR7; // 28
  2085. volatile uint32_t SR; // 2c
  2086. volatile uint32_t RSER; // 30
  2087. volatile uint32_t PUSHR; // 34
  2088. volatile uint32_t POPR; // 38
  2089. volatile uint32_t TXFR[16]; // 3c
  2090. volatile uint32_t RXFR[16]; // 7c
  2091. } KINETISK_SPI_t;
  2092. #define KINETISK_SPI0 (*(KINETISK_SPI_t *)0x4002C000)
  2093. #define SPI0_MCR (KINETISK_SPI0.MCR) // DSPI Module Configuration Register
  2094. #define SPI_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select
  2095. #define SPI_MCR_CONT_SCKE ((uint32_t)0x40000000) //
  2096. #define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
  2097. #define SPI_MCR_FRZ ((uint32_t)0x08000000) //
  2098. #define SPI_MCR_MTFE ((uint32_t)0x04000000) //
  2099. #define SPI_MCR_ROOE ((uint32_t)0x01000000) //
  2100. #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
  2101. #define SPI_MCR_DOZE ((uint32_t)0x00008000) //
  2102. #define SPI_MCR_MDIS ((uint32_t)0x00004000) //
  2103. #define SPI_MCR_DIS_TXF ((uint32_t)0x00002000) //
  2104. #define SPI_MCR_DIS_RXF ((uint32_t)0x00001000) //
  2105. #define SPI_MCR_CLR_TXF ((uint32_t)0x00000800) //
  2106. #define SPI_MCR_CLR_RXF ((uint32_t)0x00000400) //
  2107. #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
  2108. #define SPI_MCR_HALT ((uint32_t)0x00000001) //
  2109. #define SPI0_TCR (KINETISK_SPI0.TCR) // DSPI Transfer Count Register
  2110. #define SPI0_CTAR0 (KINETISK_SPI0.CTAR0) // DSPI Clock and Transfer Attributes Register, In Master Mode
  2111. #define SPI_CTAR_DBR ((uint32_t)0x80000000) // Double Baud Rate
  2112. #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
  2113. #define SPI_CTAR_CPOL ((uint32_t)0x04000000) // Clock Polarity
  2114. #define SPI_CTAR_CPHA ((uint32_t)0x02000000) // Clock Phase
  2115. #define SPI_CTAR_LSBFE ((uint32_t)0x01000000) // LSB First
  2116. #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
  2117. #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
  2118. #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
  2119. #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
  2120. #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
  2121. #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
  2122. #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
  2123. #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
  2124. #define SPI0_CTAR0_SLAVE (KINETISK_SPI0.CTAR0) // DSPI Clock and Transfer Attributes Register, In Slave Mode
  2125. #define SPI0_CTAR1 (KINETISK_SPI0.CTAR1) // DSPI Clock and Transfer Attributes Register, In Master Mode
  2126. #define SPI0_SR (KINETISK_SPI0.SR) // DSPI Status Register
  2127. #define SPI_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag
  2128. #define SPI_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status
  2129. #define SPI_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag
  2130. #define SPI_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag
  2131. #define SPI_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag
  2132. #define SPI_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag
  2133. #define SPI_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag
  2134. #define SPI0_RSER (KINETISK_SPI0.RSER) // DSPI DMA/Interrupt Request Select and Enable Register
  2135. #define SPI_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable
  2136. #define SPI_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable
  2137. #define SPI_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable
  2138. #define SPI_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable
  2139. #define SPI_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select
  2140. #define SPI_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable
  2141. #define SPI_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable
  2142. #define SPI_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select
  2143. #define SPI0_PUSHR (KINETISK_SPI0.PUSHR) // DSPI PUSH TX FIFO Register In Master Mode
  2144. #define SPI_PUSHR_CONT ((uint32_t)0x80000000) //
  2145. #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
  2146. #define SPI_PUSHR_EOQ ((uint32_t)0x08000000) //
  2147. #define SPI_PUSHR_CTCNT ((uint32_t)0x04000000) //
  2148. #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
  2149. #define SPI0_PUSHR_SLAVE (KINETISK_SPI0.PUSHR) // DSPI PUSH TX FIFO Register In Slave Mode
  2150. #define SPI0_POPR (KINETISK_SPI0.POPR) // DSPI POP RX FIFO Register
  2151. #define SPI0_TXFR0 (KINETISK_SPI0.TXFR[0]) // DSPI Transmit FIFO Registers
  2152. #define SPI0_TXFR1 (KINETISK_SPI0.TXFR[1]) // DSPI Transmit FIFO Registers
  2153. #define SPI0_TXFR2 (KINETISK_SPI0.TXFR[2]) // DSPI Transmit FIFO Registers
  2154. #define SPI0_TXFR3 (KINETISK_SPI0.TXFR[3]) // DSPI Transmit FIFO Registers
  2155. #define SPI0_RXFR0 (KINETISK_SPI0.RXFR[0]) // DSPI Receive FIFO Registers
  2156. #define SPI0_RXFR1 (KINETISK_SPI0.RXFR[1]) // DSPI Receive FIFO Registers
  2157. #define SPI0_RXFR2 (KINETISK_SPI0.RXFR[2]) // DSPI Receive FIFO Registers
  2158. #define SPI0_RXFR3 (KINETISK_SPI0.RXFR[3]) // DSPI Receive FIFO Registers
  2159. #elif defined(KINETISL)
  2160. typedef struct {
  2161. volatile uint8_t S;
  2162. volatile uint8_t BR;
  2163. volatile uint8_t C2;
  2164. volatile uint8_t C1;
  2165. volatile uint8_t ML;
  2166. volatile uint8_t MH;
  2167. volatile uint8_t DL;
  2168. volatile uint8_t DH;
  2169. volatile uint8_t unused1;
  2170. volatile uint8_t unused2;
  2171. volatile uint8_t CI;
  2172. volatile uint8_t C3;
  2173. } KINETISL_SPI_t;
  2174. #define KINETISL_SPI0 (*(KINETISL_SPI_t *)0x40076000)
  2175. #define KINETISL_SPI1 (*(KINETISL_SPI_t *)0x40077000)
  2176. #define SPI0_S (KINETISL_SPI0.S) // Status
  2177. #define SPI_S_SPRF ((uint8_t)0x80) // Read Buffer Full Flag
  2178. #define SPI_S_SPMF ((uint8_t)0x40) // Match Flag
  2179. #define SPI_S_SPTEF ((uint8_t)0x20) // Transmit Buffer Empty Flag
  2180. #define SPI_S_MODF ((uint8_t)0x10) // Fault Flag
  2181. #define SPI_S_RNFULLF ((uint8_t)0x08) // Receive FIFO nearly full flag
  2182. #define SPI_S_TNEAREF ((uint8_t)0x04) // Transmit FIFO nearly empty flag
  2183. #define SPI_S_TXFULLF ((uint8_t)0x02) // Transmit FIFO full flag
  2184. #define SPI_S_RFIFOEF ((uint8_t)0x01) // Read FIFO empty flag
  2185. #define SPI0_BR (KINETISL_SPI0.BR) // Baud Rate
  2186. #define SPI_BR_SPPR(n) (((n) & 7) << 4) // Prescale = N+1
  2187. #define SPI_BR_SPR(n) (((n) & 15) << 0) // Baud Rate Divisor = 2^(N+1) : 0-8 -> 2 to 512
  2188. #define SPI0_C2 (KINETISL_SPI0.C2) // Control Register 2
  2189. #define SPI_C2_SPMIE ((uint8_t)0x80) // Match Interrupt Enable
  2190. #define SPI_C2_SPIMODE ((uint8_t)0x40) // 0 = 8 bit mode, 1 = 16 bit mode
  2191. #define SPI_C2_TXDMAE ((uint8_t)0x20) // Transmit DMA enable
  2192. #define SPI_C2_MODFEN ((uint8_t)0x10) // Master Mode-Fault Function Enable
  2193. #define SPI_C2_BIDIROE ((uint8_t)0x08) // Bidirectional Mode Output Enable
  2194. #define SPI_C2_RXDMAE ((uint8_t)0x04) // Receive DMA enable
  2195. #define SPI_C2_SPISWAI ((uint8_t)0x02) // SPI Stop in Wait Mode
  2196. #define SPI_C2_SPC0 ((uint8_t)0x01) // SPI Pin Control, 0=normal, 1=single bidirectional
  2197. #define SPI0_C1 (KINETISL_SPI0.C1) // Control Register 1
  2198. #define SPI_C1_SPIE ((uint8_t)0x80) // Interrupt Enable
  2199. #define SPI_C1_SPE ((uint8_t)0x40) // SPI System Enable
  2200. #define SPI_C1_SPTIE ((uint8_t)0x20) // Transmit Interrupt Enable
  2201. #define SPI_C1_MSTR ((uint8_t)0x10) // Master/Slave Mode: 0=slave, 1=master
  2202. #define SPI_C1_CPOL ((uint8_t)0x08) // Clock Polarity
  2203. #define SPI_C1_CPHA ((uint8_t)0x04) // Clock Phase
  2204. #define SPI_C1_SSOE ((uint8_t)0x02) // Slave Select Output Enable
  2205. #define SPI_C1_LSBFE ((uint8_t)0x01) // LSB First: 0=MSB First, 1=LSB First
  2206. #define SPI0_ML (KINETISL_SPI0.ML) // Match Low
  2207. #define SPI0_MH (KINETISL_SPI0.MH) // Match High
  2208. #define SPI0_DL (KINETISL_SPI0.DL) // Data Low
  2209. #define SPI0_DH (KINETISL_SPI0.DH) // Data High
  2210. #define SPI0_CI (KINETISL_SPI0.CI) // Clear Interrupt
  2211. #define SPI_CI_TXFERR ((uint8_t)0x80) // Transmit FIFO error flag
  2212. #define SPI_CI_RXFERR ((uint8_t)0x40) // Receive FIFO error flag
  2213. #define SPI_CI_TXFOF ((uint8_t)0x20) // Transmit FIFO overflow flag
  2214. #define SPI_CI_RXFOF ((uint8_t)0x10) // Receive FIFO overflow flag
  2215. #define SPI_CI_TNEAREFCI ((uint8_t)0x08) // Transmit FIFO nearly empty flag clear interrupt
  2216. #define SPI_CI_RNFULLFCI ((uint8_t)0x04) // Receive FIFO nearly full flag clear interrupt
  2217. #define SPI_CI_SPTEFCI ((uint8_t)0x02) // Transmit FIFO empty flag clear interrupt
  2218. #define SPI_CI_SPRFCI ((uint8_t)0x01) // Receive FIFO full flag clear interrupt
  2219. #define SPI0_C3 (KINETISL_SPI0.C3) // Control Register 3
  2220. #define SPI_C3_TNEAREF_MARK ((uint8_t)0x20) // Transmit FIFO nearly empty watermark
  2221. #define SPI_C3_RNFULLF_MARK ((uint8_t)0x10) // Receive FIFO nearly full watermark
  2222. #define SPI_C3_INTCLR ((uint8_t)0x08) // Interrupt clearing mechanism select
  2223. #define SPI_C3_TNEARIEN ((uint8_t)0x04) // Transmit FIFO nearly empty interrupt enable
  2224. #define SPI_C3_RNFULLIEN ((uint8_t)0x02) // Receive FIFO nearly full interrupt enable
  2225. #define SPI_C3_FIFOMODE ((uint8_t)0x01) // FIFO mode enable
  2226. #define SPI1_S (KINETISL_SPI1.S) // Status
  2227. #define SPI1_BR (KINETISL_SPI1.BR) // Baud Rate
  2228. #define SPI1_C2 (KINETISL_SPI1.C2) // Control Register 2
  2229. #define SPI1_C1 (KINETISL_SPI1.C1) // Control Register 1
  2230. #define SPI1_ML (KINETISL_SPI1.ML) // Match Low
  2231. #define SPI1_MH (KINETISL_SPI1.MH) // Match High
  2232. #define SPI1_DL (KINETISL_SPI1.DL) // Data Low
  2233. #define SPI1_DH (KINETISL_SPI1.DH) // Data High
  2234. #define SPI1_CI (KINETISL_SPI1.CI) // Dlear Interrupt
  2235. #define SPI1_C3 (KINETISL_SPI1.C3) // Control Register 3
  2236. #endif
  2237. // Chapter 44: Inter-Integrated Circuit (I2C)
  2238. typedef struct {
  2239. volatile uint8_t A1;
  2240. volatile uint8_t F;
  2241. volatile uint8_t C1;
  2242. volatile uint8_t S;
  2243. volatile uint8_t D;
  2244. volatile uint8_t C2;
  2245. volatile uint8_t FLT;
  2246. volatile uint8_t RA;
  2247. volatile uint8_t SMB;
  2248. volatile uint8_t A2;
  2249. volatile uint8_t SLTH;
  2250. volatile uint8_t SLTL;
  2251. } KINETIS_I2C_t;
  2252. #define KINETIS_I2C0 (*(KINETIS_I2C_t *)0x40066000)
  2253. #define KINETIS_I2C1 (*(KINETIS_I2C_t *)0x40067000)
  2254. #define I2C0_A1 (KINETIS_I2C0.A1) // I2C Address Register 1
  2255. #define I2C0_F (KINETIS_I2C0.F) // I2C Frequency Divider register
  2256. #define I2C0_C1 (KINETIS_I2C0.C1) // I2C Control Register 1
  2257. #define I2C_C1_IICEN ((uint8_t)0x80) // I2C Enable
  2258. #define I2C_C1_IICIE ((uint8_t)0x40) // I2C Interrupt Enable
  2259. #define I2C_C1_MST ((uint8_t)0x20) // Master Mode Select
  2260. #define I2C_C1_TX ((uint8_t)0x10) // Transmit Mode Select
  2261. #define I2C_C1_TXAK ((uint8_t)0x08) // Transmit Acknowledge Enable
  2262. #define I2C_C1_RSTA ((uint8_t)0x04) // Repeat START
  2263. #define I2C_C1_WUEN ((uint8_t)0x02) // Wakeup Enable
  2264. #define I2C_C1_DMAEN ((uint8_t)0x01) // DMA Enable
  2265. #define I2C0_S (KINETIS_I2C0.S) // I2C Status register
  2266. #define I2C_S_TCF ((uint8_t)0x80) // Transfer Complete Flag
  2267. #define I2C_S_IAAS ((uint8_t)0x40) // Addressed As A Slave
  2268. #define I2C_S_BUSY ((uint8_t)0x20) // Bus Busy
  2269. #define I2C_S_ARBL ((uint8_t)0x10) // Arbitration Lost
  2270. #define I2C_S_RAM ((uint8_t)0x08) // Range Address Match
  2271. #define I2C_S_SRW ((uint8_t)0x04) // Slave Read/Write
  2272. #define I2C_S_IICIF ((uint8_t)0x02) // Interrupt Flag
  2273. #define I2C_S_RXAK ((uint8_t)0x01) // Receive Acknowledge
  2274. #define I2C0_D (KINETIS_I2C0.D) // I2C Data I/O register
  2275. #define I2C0_C2 (KINETIS_I2C0.C2) // I2C Control Register 2
  2276. #define I2C_C2_GCAEN ((uint8_t)0x80) // General Call Address Enable
  2277. #define I2C_C2_ADEXT ((uint8_t)0x40) // Address Extension
  2278. #define I2C_C2_HDRS ((uint8_t)0x20) // High Drive Select
  2279. #define I2C_C2_SBRC ((uint8_t)0x10) // Slave Baud Rate Control
  2280. #define I2C_C2_RMEN ((uint8_t)0x08) // Range Address Matching Enable
  2281. #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
  2282. #define I2C0_FLT (KINETIS_I2C0.FLT) // I2C Programmable Input Glitch Filter register
  2283. #define I2C_FLT_SHEN ((uint8_t)0x80) // Stop Hold Enable
  2284. #define I2C_FLT_STOPF ((uint8_t)0x40) // Stop Detect Flag
  2285. #define I2C_FLT_STOPIE ((uint8_t)0x20) // Stop Interrupt Enable
  2286. #define I2C_FLT_FTL(n) ((n) & 0x1F) // Programmable Filter Factor
  2287. #define I2C0_RA (KINETIS_I2C0.RA) // I2C Range Address register
  2288. #define I2C0_SMB (KINETIS_I2C0.SMB) // I2C SMBus Control and Status register
  2289. #define I2C0_A2 (KINETIS_I2C0.A2) // I2C Address Register 2
  2290. #define I2C0_SLTH (KINETIS_I2C0.SLTH) // I2C SCL Low Timeout Register High
  2291. #define I2C0_SLTL (KINETIS_I2C0.SLTL) // I2C SCL Low Timeout Register Low
  2292. #define I2C1_A1 (KINETIS_I2C1.A1) // I2C Address Register 1
  2293. #define I2C1_F (KINETIS_I2C1.F) // I2C Frequency Divider register
  2294. #define I2C1_C1 (KINETIS_I2C1.C1) // I2C Control Register 1
  2295. #define I2C1_S (KINETIS_I2C1.S) // I2C Status register
  2296. #define I2C1_D (KINETIS_I2C1.D) // I2C Data I/O register
  2297. #define I2C1_C2 (KINETIS_I2C1.C2) // I2C Control Register 2
  2298. #define I2C1_FLT (KINETIS_I2C1.FLT) // I2C Programmable Input Glitch Filter register
  2299. #define I2C1_RA (KINETIS_I2C1.RA) // I2C Range Address register
  2300. #define I2C1_SMB (KINETIS_I2C1.SMB) // I2C SMBus Control and Status register
  2301. #define I2C1_A2 (KINETIS_I2C1.A2) // I2C Address Register 2
  2302. #define I2C1_SLTH (KINETIS_I2C1.SLTH) // I2C SCL Low Timeout Register High
  2303. #define I2C1_SLTL (KINETIS_I2C1.SLTL) // I2C SCL Low Timeout Register Low
  2304. // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
  2305. typedef struct __attribute__((packed)) {
  2306. volatile uint8_t BDH;
  2307. volatile uint8_t BDL;
  2308. volatile uint8_t C1;
  2309. volatile uint8_t C2;
  2310. volatile uint8_t S1;
  2311. volatile uint8_t S2;
  2312. volatile uint8_t C3;
  2313. volatile uint8_t D;
  2314. volatile uint8_t MA1;
  2315. volatile uint8_t MA2;
  2316. volatile uint8_t C4;
  2317. volatile uint8_t C5;
  2318. volatile uint8_t ED;
  2319. volatile uint8_t MODEM;
  2320. volatile uint8_t IR;
  2321. volatile uint8_t unused1;
  2322. volatile uint8_t PFIFO;
  2323. volatile uint8_t CFIFO;
  2324. volatile uint8_t SFIFO;
  2325. volatile uint8_t TWFIFO;
  2326. volatile uint8_t TCFIFO;
  2327. volatile uint8_t RWFIFO;
  2328. volatile uint8_t RCFIFO;
  2329. volatile uint8_t unused2;
  2330. volatile uint8_t C7816;
  2331. volatile uint8_t IE7816;
  2332. volatile uint8_t IS7816;
  2333. union { volatile uint8_t WP7816T0; volatile uint8_t WP7816T1; };
  2334. volatile uint8_t WN7816;
  2335. volatile uint8_t WF7816;
  2336. volatile uint8_t ET7816;
  2337. volatile uint8_t TL7816;
  2338. volatile uint8_t unused3;
  2339. volatile uint8_t C6;
  2340. volatile uint8_t PCTH;
  2341. volatile uint8_t PCTL;
  2342. volatile uint8_t B1T;
  2343. volatile uint8_t SDTH;
  2344. volatile uint8_t SDTL;
  2345. volatile uint8_t PRE;
  2346. volatile uint8_t TPL;
  2347. volatile uint8_t IE;
  2348. volatile uint8_t WB;
  2349. volatile uint8_t S3;
  2350. volatile uint8_t S4;
  2351. volatile uint8_t RPL;
  2352. volatile uint8_t RPREL;
  2353. volatile uint8_t CPW;
  2354. volatile uint8_t RIDT;
  2355. volatile uint8_t TIDT;
  2356. } KINETISK_UART_t;
  2357. #define KINETISK_UART0 (*(KINETISK_UART_t *)0x4006A000)
  2358. #define UART0_BDH (KINETISK_UART0.BDH) // UART Baud Rate Registers: High
  2359. #define UART0_BDL (KINETISK_UART0.BDL) // UART Baud Rate Registers: Low
  2360. #define UART0_C1 (KINETISK_UART0.C1) // UART Control Register 1
  2361. #define UART_C1_LOOPS 0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
  2362. #define UART_C1_UARTSWAI 0x40 // UART Stops in Wait Mode
  2363. #define UART_C1_RSRC 0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
  2364. #define UART_C1_M 0x10 // 9-bit or 8-bit Mode Select
  2365. #define UART_C1_WAKE 0x08 // Determines which condition wakes the UART
  2366. #define UART_C1_ILT 0x04 // Idle Line Type Select
  2367. #define UART_C1_PE 0x02 // Parity Enable
  2368. #define UART_C1_PT 0x01 // Parity Type, 0=even, 1=odd
  2369. #define UART0_C2 (KINETISK_UART0.C2) // UART Control Register 2
  2370. #define UART_C2_TIE 0x80 // Transmitter Interrupt or DMA Transfer Enable.
  2371. #define UART_C2_TCIE 0x40 // Transmission Complete Interrupt Enable
  2372. #define UART_C2_RIE 0x20 // Receiver Full Interrupt or DMA Transfer Enable
  2373. #define UART_C2_ILIE 0x10 // Idle Line Interrupt Enable
  2374. #define UART_C2_TE 0x08 // Transmitter Enable
  2375. #define UART_C2_RE 0x04 // Receiver Enable
  2376. #define UART_C2_RWU 0x02 // Receiver Wakeup Control
  2377. #define UART_C2_SBK 0x01 // Send Break
  2378. #define UART0_S1 (KINETISK_UART0.S1) // UART Status Register 1
  2379. #define UART_S1_TDRE 0x80 // Transmit Data Register Empty Flag
  2380. #define UART_S1_TC 0x40 // Transmit Complete Flag
  2381. #define UART_S1_RDRF 0x20 // Receive Data Register Full Flag
  2382. #define UART_S1_IDLE 0x10 // Idle Line Flag
  2383. #define UART_S1_OR 0x08 // Receiver Overrun Flag
  2384. #define UART_S1_NF 0x04 // Noise Flag
  2385. #define UART_S1_FE 0x02 // Framing Error Flag
  2386. #define UART_S1_PF 0x01 // Parity Error Flag
  2387. #define UART0_S2 (KINETISK_UART0.S2) // UART Status Register 2
  2388. #define UART0_C3 (KINETISK_UART0.C3) // UART Control Register 3
  2389. #define UART0_D (KINETISK_UART0.D) // UART Data Register
  2390. #define UART0_MA1 (KINETISK_UART0.MA1) // UART Match Address Registers 1
  2391. #define UART0_MA2 (KINETISK_UART0.MA2) // UART Match Address Registers 2
  2392. #define UART0_C4 (KINETISK_UART0.C4) // UART Control Register 4
  2393. #define UART0_C5 (KINETISK_UART0.C5) // UART Control Register 5
  2394. #define UART0_ED (KINETISK_UART0.ED) // UART Extended Data Register
  2395. #define UART0_MODEM (KINETISK_UART0.MODEM) // UART Modem Register
  2396. #define UART0_IR (KINETISK_UART0.IR) // UART Infrared Register
  2397. #define UART0_PFIFO (KINETISK_UART0.PFIFO) // UART FIFO Parameters
  2398. #define UART_PFIFO_TXFE 0x80 // Transmit FIFO Enable
  2399. #define UART_PFIFO_TXFIFOSIZE(n) (((n) & 7) << 4) // Transmit FIFO Size, 0=1, 1=4, 2=8, 3=16, 4=32, 5=64, 6=128
  2400. #define UART_PFIFO_RXFE 0x08 // Receive FIFO Enable
  2401. #define UART_PFIFO_RXFIFOSIZE(n) (((n) & 7) << 0) // Transmit FIFO Size, 0=1, 1=4, 2=8, 3=16, 4=32, 5=64, 6=128
  2402. #define UART0_CFIFO (KINETISK_UART0.CFIFO) // UART FIFO Control Register
  2403. #define UART_CFIFO_TXFLUSH 0x80 // Transmit FIFO/Buffer Flush
  2404. #define UART_CFIFO_RXFLUSH 0x40 // Receive FIFO/Buffer Flush
  2405. #define UART_CFIFO_RXOFE 0x04 // Receive FIFO Overflow Interrupt Enable
  2406. #define UART_CFIFO_TXOFE 0x02 // Transmit FIFO Overflow Interrupt Enable
  2407. #define UART_CFIFO_RXUFE 0x01 // Receive FIFO Underflow Interrupt Enable
  2408. #define UART0_SFIFO (KINETISK_UART0.SFIFO) // UART FIFO Status Register
  2409. #define UART_SFIFO_TXEMPT 0x80 // Transmit Buffer/FIFO Empty
  2410. #define UART_SFIFO_RXEMPT 0x40 // Receive Buffer/FIFO Empty
  2411. #define UART_SFIFO_RXOF 0x04 // Receiver Buffer Overflow Flag
  2412. #define UART_SFIFO_TXOF 0x02 // Transmitter Buffer Overflow Flag
  2413. #define UART_SFIFO_RXUF 0x01 // Receiver Buffer Underflow Flag
  2414. #define UART0_TWFIFO (KINETISK_UART0.TWFIFO) // UART FIFO Transmit Watermark
  2415. #define UART0_TCFIFO (KINETISK_UART0.TCFIFO) // UART FIFO Transmit Count
  2416. #define UART0_RWFIFO (KINETISK_UART0.RWFIFO) // UART FIFO Receive Watermark
  2417. #define UART0_RCFIFO (KINETISK_UART0.RCFIFO) // UART FIFO Receive Count
  2418. #define UART0_C7816 (KINETISK_UART0.C7816) // UART 7816 Control Register
  2419. #define UART_C7816_ONACK 0x10 // Generate NACK on Overflow
  2420. #define UART_C7816_ANACK 0x08 // Generate NACK on Error
  2421. #define UART_C7816_INIT 0x04 // Detect Initial Character
  2422. #define UART_C7816_TTYPE 0x02 // Transfer Type
  2423. #define UART_C7816_ISO_7816E 0x01 // ISO-7816 Functionality Enabled
  2424. #define UART0_IE7816 (KINETISK_UART0.IE7816) // UART 7816 Interrupt Enable Register
  2425. #define UART_IE7816_WTE 0x80 // Wait Timer Interrupt Enable
  2426. #define UART_IE7816_CWTE 0x40 // Character Wait Timer Interrupt Enable
  2427. #define UART_IE7816_BWTE 0x20 // Block Wait Timer Interrupt Enable
  2428. #define UART_IE7816_INITDE 0x10 // Initial Character Detected Interrupt Enable
  2429. #define UART_IE7816_GTVE 0x04 // Guard Timer Violated Interrupt Enable
  2430. #define UART_IE7816_TXTE 0x02 // Transmit Threshold Exceeded Interrupt Enable
  2431. #define UART_IE7816_RXTE 0x01 // Receive Threshold Exceeded Interrupt Enable
  2432. #define UART0_IS7816 (KINETISK_UART0.IS7816) // UART 7816 Interrupt Status Register
  2433. #define UART_IS7816_WT 0x80 // Wait Timer Interrupt
  2434. #define UART_IS7816_CWT 0x40 // Character Wait Timer Interrupt
  2435. #define UART_IS7816_BWT 0x20 // Block Wait Timer Interrupt
  2436. #define UART_IS7816_INITD 0x10 // Initial Character Detected Interrupt
  2437. #define UART_IS7816_GTV 0x04 // Guard Timer Violated Interrupt
  2438. #define UART_IS7816_TXT 0x02 // Transmit Threshold Exceeded Interrupt
  2439. #define UART_IS7816_RXT 0x01 // Receive Threshold Exceeded Interrupt
  2440. #define UART0_WP7816T0 (KINETISK_UART0.WP7816T0) // UART 7816 Wait Parameter Register
  2441. #define UART0_WP7816T1 (KINETISK_UART0.WP7816T1) // UART 7816 Wait Parameter Register
  2442. #define UART_WP7816T1_CWI(n) (((n) & 15) << 4) // Character Wait Time Integer (C7816[TTYPE] = 1)
  2443. #define UART_WP7816T1_BWI(n) (((n) & 15) << 0) // Block Wait Time Integer(C7816[TTYPE] = 1)
  2444. #define UART0_WN7816 (KINETISK_UART0.WN7816) // UART 7816 Wait N Register
  2445. #define UART0_WF7816 (KINETISK_UART0.WF7816) // UART 7816 Wait FD Register
  2446. #define UART0_ET7816 (KINETISK_UART0.ET7816) // UART 7816 Error Threshold Register
  2447. #define UART_ET7816_TXTHRESHOLD(n) (((n) & 15) << 4) // Transmit NACK Threshold
  2448. #define UART_ET7816_RXTHRESHOLD(n) (((n) & 15) << 0) // Receive NACK Threshold
  2449. #define UART0_TL7816 (KINETISK_UART0.TL7816) // UART 7816 Transmit Length Register
  2450. #define UART0_C6 (KINETISK_UART0.C6) // UART CEA709.1-B Control Register 6
  2451. #define UART_C6_EN709 0x80 // Enables the CEA709.1-B feature.
  2452. #define UART_C6_TX709 0x40 // Starts CEA709.1-B transmission.
  2453. #define UART_C6_CE 0x20 // Collision Enable
  2454. #define UART_C6_CP 0x10 // Collision Signal Polarity
  2455. #define UART0_PCTH (KINETISK_UART0.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
  2456. #define UART0_PCTL (KINETISK_UART0.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
  2457. #define UART0_B1T (KINETISK_UART0.B1T) // UART CEA709.1-B Beta1 Timer
  2458. #define UART0_SDTH (KINETISK_UART0.SDTH) // UART CEA709.1-B Secondary Delay Timer High
  2459. #define UART0_SDTL (KINETISK_UART0.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
  2460. #define UART0_PRE (KINETISK_UART0.PRE) // UART CEA709.1-B Preamble
  2461. #define UART0_TPL (KINETISK_UART0.TPL) // UART CEA709.1-B Transmit Packet Length
  2462. #define UART0_IE (KINETISK_UART0.IE) // UART CEA709.1-B Interrupt Enable Register
  2463. #define UART_IE_WBEIE 0x40 // WBASE Expired Interrupt Enable
  2464. #define UART_IE_ISDIE 0x20 // Initial Sync Detection Interrupt Enable
  2465. #define UART_IE_PRXIE 0x10 // Packet Received Interrupt Enable
  2466. #define UART_IE_PTXIE 0x08 // Packet Transmitted Interrupt Enable
  2467. #define UART_IE_PCTEIE 0x04 // Packet Cycle Timer Interrupt Enable
  2468. #define UART_IE_PSIE 0x02 // Preamble Start Interrupt Enable
  2469. #define UART_IE_TXFIE 0x01 // Transmission Fail Interrupt Enable
  2470. #define UART0_WB (KINETISK_UART0.WB) // UART CEA709.1-B WBASE
  2471. #define UART0_S3 (KINETISK_UART0.S3) // UART CEA709.1-B Status Register
  2472. #define UART_S3_PEF 0x80 // Preamble Error Flag
  2473. #define UART_S3_WBEF 0x40 // Wbase Expired Flag
  2474. #define UART_S3_ISD 0x20 // Initial Sync Detect
  2475. #define UART_S3_PRXF 0x10 // Packet Received Flag
  2476. #define UART_S3_PTXF 0x08 // Packet Transmitted Flag
  2477. #define UART_S3_PCTEF 0x04 // Packet Cycle Timer Expired Flag
  2478. #define UART_S3_PSF 0x02 // Preamble Start Flag
  2479. #define UART_S3_TXFF 0x01 // Transmission Fail Flag
  2480. #define UART0_S4 (KINETISK_UART0.S4) // UART CEA709.1-B Status Register
  2481. #define UART_S4_INITF 0x10 // Initial Synchronization Fail Flag
  2482. #define UART_S4_CDET(n) (((n) & 3) << 2) // Indicates collision: 0=none, 1=preamble, 2=data, 3=line code violation
  2483. #define UART_S4_ILCV 0x02 // Improper Line Code Violation
  2484. #define UART_S4_FE 0x01 // Framing Error
  2485. #define UART0_RPL (KINETISK_UART0.RPL) // UART CEA709.1-B Received Packet Length
  2486. #define UART0_RPREL (KINETISK_UART0.RPREL) // UART CEA709.1-B Received Preamble Length
  2487. #define UART0_CPW (KINETISK_UART0.CPW) // UART CEA709.1-B Collision Pulse Width
  2488. #define UART0_RIDT (KINETISK_UART0.RIDT) // UART CEA709.1-B Receive Indeterminate Time
  2489. #define UART0_TIDT (KINETISK_UART0.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
  2490. #define KINETISK_UART1 (*(KINETISK_UART_t *)0x4006B000)
  2491. #define UART1_BDH (KINETISK_UART1.BDH) // UART Baud Rate Registers: High
  2492. #define UART1_BDL (KINETISK_UART1.BDL) // UART Baud Rate Registers: Low
  2493. #define UART1_C1 (KINETISK_UART1.C1) // UART Control Register 1
  2494. #define UART1_C2 (KINETISK_UART1.C2) // UART Control Register 2
  2495. #define UART1_S1 (KINETISK_UART1.S1) // UART Status Register 1
  2496. #define UART1_S2 (KINETISK_UART1.S2) // UART Status Register 2
  2497. #define UART1_C3 (KINETISK_UART1.C3) // UART Control Register 3
  2498. #define UART1_D (KINETISK_UART1.D) // UART Data Register
  2499. #define UART1_MA1 (KINETISK_UART1.MA1) // UART Match Address Registers 1
  2500. #define UART1_MA2 (KINETISK_UART1.MA2) // UART Match Address Registers 2
  2501. #define UART1_C4 (KINETISK_UART1.C4) // UART Control Register 4
  2502. #define UART1_C5 (KINETISK_UART1.C5) // UART Control Register 5
  2503. #define UART1_ED (KINETISK_UART1.ED) // UART Extended Data Register
  2504. #define UART1_MODEM (KINETISK_UART1.MODEM) // UART Modem Register
  2505. #define UART1_IR (KINETISK_UART1.IR) // UART Infrared Register
  2506. #define UART1_PFIFO (KINETISK_UART1.PFIFO) // UART FIFO Parameters
  2507. #define UART1_CFIFO (KINETISK_UART1.CFIFO) // UART FIFO Control Register
  2508. #define UART1_SFIFO (KINETISK_UART1.SFIFO) // UART FIFO Status Register
  2509. #define UART1_TWFIFO (KINETISK_UART1.TWFIFO) // UART FIFO Transmit Watermark
  2510. #define UART1_TCFIFO (KINETISK_UART1.TCFIFO) // UART FIFO Transmit Count
  2511. #define UART1_RWFIFO (KINETISK_UART1.RWFIFO) // UART FIFO Receive Watermark
  2512. #define UART1_RCFIFO (KINETISK_UART1.RCFIFO) // UART FIFO Receive Count
  2513. #define UART1_C7816 (KINETISK_UART1.C7816) // UART 7816 Control Register
  2514. #define UART1_IE7816 (KINETISK_UART1.IE7816) // UART 7816 Interrupt Enable Register
  2515. #define UART1_IS7816 (KINETISK_UART1.IS7816) // UART 7816 Interrupt Status Register
  2516. #define UART1_WP7816T0 (KINETISK_UART1.WP7816T0)// UART 7816 Wait Parameter Register
  2517. #define UART1_WP7816T1 (KINETISK_UART1.WP7816T1)// UART 7816 Wait Parameter Register
  2518. #define UART1_WN7816 (KINETISK_UART1.WN7816) // UART 7816 Wait N Register
  2519. #define UART1_WF7816 (KINETISK_UART1.WF7816) // UART 7816 Wait FD Register
  2520. #define UART1_ET7816 (KINETISK_UART1.ET7816) // UART 7816 Error Threshold Register
  2521. #define UART1_TL7816 (KINETISK_UART1.TL7816) // UART 7816 Transmit Length Register
  2522. #define UART1_C6 (KINETISK_UART1.C6) // UART CEA709.1-B Control Register 6
  2523. #define UART1_PCTH (KINETISK_UART1.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
  2524. #define UART1_PCTL (KINETISK_UART1.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
  2525. #define UART1_B1T (KINETISK_UART1.B1T) // UART CEA709.1-B Beta1 Timer
  2526. #define UART1_SDTH (KINETISK_UART1.SDTH) // UART CEA709.1-B Secondary Delay Timer High
  2527. #define UART1_SDTL (KINETISK_UART1.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
  2528. #define UART1_PRE (KINETISK_UART1.PRE) // UART CEA709.1-B Preamble
  2529. #define UART1_TPL (KINETISK_UART1.TPL) // UART CEA709.1-B Transmit Packet Length
  2530. #define UART1_IE (KINETISK_UART1.IE) // UART CEA709.1-B Interrupt Enable Register
  2531. #define UART1_WB (KINETISK_UART1.WB) // UART CEA709.1-B WBASE
  2532. #define UART1_S3 (KINETISK_UART1.S3) // UART CEA709.1-B Status Register
  2533. #define UART1_S4 (KINETISK_UART1.S4) // UART CEA709.1-B Status Register
  2534. #define UART1_RPL (KINETISK_UART1.RPL) // UART CEA709.1-B Received Packet Length
  2535. #define UART1_RPREL (KINETISK_UART1.RPREL) // UART CEA709.1-B Received Preamble Length
  2536. #define UART1_CPW (KINETISK_UART1.CPW) // UART CEA709.1-B Collision Pulse Width
  2537. #define UART1_RIDT (KINETISK_UART1.RIDT) // UART CEA709.1-B Receive Indeterminate Time
  2538. #define UART1_TIDT (KINETISK_UART1.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
  2539. #define KINETISK_UART2 (*(KINETISK_UART_t *)0x4006C000)
  2540. #define UART2_BDH (KINETISK_UART2.BDH) // UART Baud Rate Registers: High
  2541. #define UART2_BDL (KINETISK_UART2.BDL) // UART Baud Rate Registers: Low
  2542. #define UART2_C1 (KINETISK_UART2.C1) // UART Control Register 1
  2543. #define UART2_C2 (KINETISK_UART2.C2) // UART Control Register 2
  2544. #define UART2_S1 (KINETISK_UART2.S1) // UART Status Register 1
  2545. #define UART2_S2 (KINETISK_UART2.S2) // UART Status Register 2
  2546. #define UART2_C3 (KINETISK_UART2.C3) // UART Control Register 3
  2547. #define UART2_D (KINETISK_UART2.D) // UART Data Register
  2548. #define UART2_MA1 (KINETISK_UART2.MA1) // UART Match Address Registers 1
  2549. #define UART2_MA2 (KINETISK_UART2.MA2) // UART Match Address Registers 2
  2550. #define UART2_C4 (KINETISK_UART2.C4) // UART Control Register 4
  2551. #define UART2_C5 (KINETISK_UART2.C5) // UART Control Register 5
  2552. #define UART2_ED (KINETISK_UART2.ED) // UART Extended Data Register
  2553. #define UART2_MODEM (KINETISK_UART2.MODEM) // UART Modem Register
  2554. #define UART2_IR (KINETISK_UART2.IR) // UART Infrared Register
  2555. #define UART2_PFIFO (KINETISK_UART2.PFIFO) // UART FIFO Parameters
  2556. #define UART2_CFIFO (KINETISK_UART2.CFIFO) // UART FIFO Control Register
  2557. #define UART2_SFIFO (KINETISK_UART2.SFIFO) // UART FIFO Status Register
  2558. #define UART2_TWFIFO (KINETISK_UART2.TWFIFO) // UART FIFO Transmit Watermark
  2559. #define UART2_TCFIFO (KINETISK_UART2.TCFIFO) // UART FIFO Transmit Count
  2560. #define UART2_RWFIFO (KINETISK_UART2.RWFIFO) // UART FIFO Receive Watermark
  2561. #define UART2_RCFIFO (KINETISK_UART2.RCFIFO) // UART FIFO Receive Count
  2562. #define UART2_C7816 (KINETISK_UART2.C7816) // UART 7816 Control Register
  2563. #define UART2_IE7816 (KINETISK_UART2.IE7816) // UART 7816 Interrupt Enable Register
  2564. #define UART2_IS7816 (KINETISK_UART2.IS7816) // UART 7816 Interrupt Status Register
  2565. #define UART2_WP7816T0 (KINETISK_UART2.WP7816T0)// UART 7816 Wait Parameter Register
  2566. #define UART2_WP7816T1 (KINETISK_UART2.WP7816T1)// UART 7816 Wait Parameter Register
  2567. #define UART2_WN7816 (KINETISK_UART2.WN7816) // UART 7816 Wait N Register
  2568. #define UART2_WF7816 (KINETISK_UART2.WF7816) // UART 7816 Wait FD Register
  2569. #define UART2_ET7816 (KINETISK_UART2.ET7816) // UART 7816 Error Threshold Register
  2570. #define UART2_TL7816 (KINETISK_UART2.TL7816) // UART 7816 Transmit Length Register
  2571. #define UART2_C6 (KINETISK_UART2.C6) // UART CEA709.1-B Control Register 6
  2572. #define UART2_PCTH (KINETISK_UART2.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
  2573. #define UART2_PCTL (KINETISK_UART2.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
  2574. #define UART2_B1T (KINETISK_UART2.B1T) // UART CEA709.1-B Beta1 Timer
  2575. #define UART2_SDTH (KINETISK_UART2.SDTH) // UART CEA709.1-B Secondary Delay Timer High
  2576. #define UART2_SDTL (KINETISK_UART2.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
  2577. #define UART2_PRE (KINETISK_UART2.PRE) // UART CEA709.1-B Preamble
  2578. #define UART2_TPL (KINETISK_UART2.TPL) // UART CEA709.1-B Transmit Packet Length
  2579. #define UART2_IE (KINETISK_UART2.IE) // UART CEA709.1-B Interrupt Enable Register
  2580. #define UART2_WB (KINETISK_UART2.WB) // UART CEA709.1-B WBASE
  2581. #define UART2_S3 (KINETISK_UART2.S3) // UART CEA709.1-B Status Register
  2582. #define UART2_S4 (KINETISK_UART2.S4) // UART CEA709.1-B Status Register
  2583. #define UART2_RPL (KINETISK_UART2.RPL) // UART CEA709.1-B Received Packet Length
  2584. #define UART2_RPREL (KINETISK_UART2.RPREL) // UART CEA709.1-B Received Preamble Length
  2585. #define UART2_CPW (KINETISK_UART2.CPW) // UART CEA709.1-B Collision Pulse Width
  2586. #define UART2_RIDT (KINETISK_UART2.RIDT) // UART CEA709.1-B Receive Indeterminate Time
  2587. #define UART2_TIDT (KINETISK_UART2.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
  2588. // Chapter 46: Synchronous Audio Interface (SAI)
  2589. #define I2S0_TCSR (*(volatile uint32_t *)0x4002F000) // SAI Transmit Control Register
  2590. #define I2S_TCSR_TE ((uint32_t)0x80000000) // Transmitter Enable
  2591. #define I2S_TCSR_STOPE ((uint32_t)0x40000000) // Transmitter Enable in Stop mode
  2592. #define I2S_TCSR_DBGE ((uint32_t)0x20000000) // Transmitter Enable in Debug mode
  2593. #define I2S_TCSR_BCE ((uint32_t)0x10000000) // Bit Clock Enable
  2594. #define I2S_TCSR_FR ((uint32_t)0x02000000) // FIFO Reset
  2595. #define I2S_TCSR_SR ((uint32_t)0x01000000) // Software Reset
  2596. #define I2S_TCSR_WSF ((uint32_t)0x00100000) // Word Start Flag
  2597. #define I2S_TCSR_SEF ((uint32_t)0x00080000) // Sync Error Flag
  2598. #define I2S_TCSR_FEF ((uint32_t)0x00040000) // FIFO Error Flag (underrun)
  2599. #define I2S_TCSR_FWF ((uint32_t)0x00020000) // FIFO Warning Flag (empty)
  2600. #define I2S_TCSR_FRF ((uint32_t)0x00010000) // FIFO Request Flag (Data Ready)
  2601. #define I2S_TCSR_WSIE ((uint32_t)0x00001000) // Word Start Interrupt Enable
  2602. #define I2S_TCSR_SEIE ((uint32_t)0x00000800) // Sync Error Interrupt Enable
  2603. #define I2S_TCSR_FEIE ((uint32_t)0x00000400) // FIFO Error Interrupt Enable
  2604. #define I2S_TCSR_FWIE ((uint32_t)0x00000200) // FIFO Warning Interrupt Enable
  2605. #define I2S_TCSR_FRIE ((uint32_t)0x00000100) // FIFO Request Interrupt Enable
  2606. #define I2S_TCSR_FWDE ((uint32_t)0x00000002) // FIFO Warning DMA Enable
  2607. #define I2S_TCSR_FRDE ((uint32_t)0x00000001) // FIFO Request DMA Enable
  2608. #define I2S0_TCR1 (*(volatile uint32_t *)0x4002F004) // SAI Transmit Configuration 1 Register
  2609. #define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
  2610. #define I2S0_TCR2 (*(volatile uint32_t *)0x4002F008) // SAI Transmit Configuration 2 Register
  2611. #define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
  2612. #define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
  2613. #define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
  2614. #define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
  2615. #define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
  2616. #define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
  2617. #define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
  2618. #define I2S0_TCR3 (*(volatile uint32_t *)0x4002F00C) // SAI Transmit Configuration 3 Register
  2619. #define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
  2620. #define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
  2621. #define I2S0_TCR4 (*(volatile uint32_t *)0x4002F010) // SAI Transmit Configuration 4 Register
  2622. #define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
  2623. #define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
  2624. #define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
  2625. #define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
  2626. #define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
  2627. #define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
  2628. #define I2S0_TCR5 (*(volatile uint32_t *)0x4002F014) // SAI Transmit Configuration 5 Register
  2629. #define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
  2630. #define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
  2631. #define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
  2632. #define I2S0_TDR0 (*(volatile uint32_t *)0x4002F020) // SAI Transmit Data Register
  2633. #define I2S0_TDR1 (*(volatile uint32_t *)0x4002F024) // SAI Transmit Data Register
  2634. #define I2S0_TFR0 (*(volatile uint32_t *)0x4002F040) // SAI Transmit FIFO Register
  2635. #define I2S0_TFR1 (*(volatile uint32_t *)0x4002F044) // SAI Transmit FIFO Register
  2636. #define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
  2637. #define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
  2638. #define I2S0_TMR (*(volatile uint32_t *)0x4002F060) // SAI Transmit Mask Register
  2639. #define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) //
  2640. #define I2S0_RCSR (*(volatile uint32_t *)0x4002F080) // SAI Receive Control Register
  2641. #define I2S_RCSR_RE ((uint32_t)0x80000000) // Receiver Enable
  2642. #define I2S_RCSR_STOPE ((uint32_t)0x40000000) // Receiver Enable in Stop mode
  2643. #define I2S_RCSR_DBGE ((uint32_t)0x20000000) // Receiver Enable in Debug mode
  2644. #define I2S_RCSR_BCE ((uint32_t)0x10000000) // Bit Clock Enable
  2645. #define I2S_RCSR_FR ((uint32_t)0x02000000) // FIFO Reset
  2646. #define I2S_RCSR_SR ((uint32_t)0x01000000) // Software Reset
  2647. #define I2S_RCSR_WSF ((uint32_t)0x00100000) // Word Start Flag
  2648. #define I2S_RCSR_SEF ((uint32_t)0x00080000) // Sync Error Flag
  2649. #define I2S_RCSR_FEF ((uint32_t)0x00040000) // FIFO Error Flag (underrun)
  2650. #define I2S_RCSR_FWF ((uint32_t)0x00020000) // FIFO Warning Flag (empty)
  2651. #define I2S_RCSR_FRF ((uint32_t)0x00010000) // FIFO Request Flag (Data Ready)
  2652. #define I2S_RCSR_WSIE ((uint32_t)0x00001000) // Word Start Interrupt Enable
  2653. #define I2S_RCSR_SEIE ((uint32_t)0x00000800) // Sync Error Interrupt Enable
  2654. #define I2S_RCSR_FEIE ((uint32_t)0x00000400) // FIFO Error Interrupt Enable
  2655. #define I2S_RCSR_FWIE ((uint32_t)0x00000200) // FIFO Warning Interrupt Enable
  2656. #define I2S_RCSR_FRIE ((uint32_t)0x00000100) // FIFO Request Interrupt Enable
  2657. #define I2S_RCSR_FWDE ((uint32_t)0x00000002) // FIFO Warning DMA Enable
  2658. #define I2S_RCSR_FRDE ((uint32_t)0x00000001) // FIFO Request DMA Enable
  2659. #define I2S0_RCR1 (*(volatile uint32_t *)0x4002F084) // SAI Receive Configuration 1 Register
  2660. #define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
  2661. #define I2S0_RCR2 (*(volatile uint32_t *)0x4002F088) // SAI Receive Configuration 2 Register
  2662. #define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
  2663. #define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
  2664. #define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
  2665. #define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
  2666. #define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
  2667. #define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
  2668. #define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
  2669. #define I2S0_RCR3 (*(volatile uint32_t *)0x4002F08C) // SAI Receive Configuration 3 Register
  2670. #define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
  2671. #define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
  2672. #define I2S0_RCR4 (*(volatile uint32_t *)0x4002F090) // SAI Receive Configuration 4 Register
  2673. #define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
  2674. #define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
  2675. #define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
  2676. #define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
  2677. #define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
  2678. #define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
  2679. #define I2S0_RCR5 (*(volatile uint32_t *)0x4002F094) // SAI Receive Configuration 5 Register
  2680. #define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
  2681. #define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
  2682. #define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
  2683. #define I2S0_RDR0 (*(volatile uint32_t *)0x4002F0A0) // SAI Receive Data Register
  2684. #define I2S0_RDR1 (*(volatile uint32_t *)0x4002F0A4) // SAI Receive Data Register
  2685. #define I2S0_RFR0 (*(volatile uint32_t *)0x4002F0C0) // SAI Receive FIFO Register
  2686. #define I2S0_RFR1 (*(volatile uint32_t *)0x4002F0C4) // SAI Receive FIFO Register
  2687. #define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
  2688. #define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
  2689. #define I2S0_RMR (*(volatile uint32_t *)0x4002F0E0) // SAI Receive Mask Register
  2690. #define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) //
  2691. #define I2S0_MCR (*(volatile uint32_t *)0x4002F100) // SAI MCLK Control Register
  2692. #define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
  2693. #define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
  2694. #define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
  2695. #define I2S0_MDR (*(volatile uint32_t *)0x4002F104) // SAI MCLK Divide Register
  2696. #define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
  2697. #define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide
  2698. // Chapter 47: General-Purpose Input/Output (GPIO)
  2699. #define GPIOA_PDOR (*(volatile uint32_t *)0x400FF000) // Port Data Output Register
  2700. #define GPIOA_PSOR (*(volatile uint32_t *)0x400FF004) // Port Set Output Register
  2701. #define GPIOA_PCOR (*(volatile uint32_t *)0x400FF008) // Port Clear Output Register
  2702. #define GPIOA_PTOR (*(volatile uint32_t *)0x400FF00C) // Port Toggle Output Register
  2703. #define GPIOA_PDIR (*(volatile uint32_t *)0x400FF010) // Port Data Input Register
  2704. #define GPIOA_PDDR (*(volatile uint32_t *)0x400FF014) // Port Data Direction Register
  2705. #define GPIOB_PDOR (*(volatile uint32_t *)0x400FF040) // Port Data Output Register
  2706. #define GPIOB_PSOR (*(volatile uint32_t *)0x400FF044) // Port Set Output Register
  2707. #define GPIOB_PCOR (*(volatile uint32_t *)0x400FF048) // Port Clear Output Register
  2708. #define GPIOB_PTOR (*(volatile uint32_t *)0x400FF04C) // Port Toggle Output Register
  2709. #define GPIOB_PDIR (*(volatile uint32_t *)0x400FF050) // Port Data Input Register
  2710. #define GPIOB_PDDR (*(volatile uint32_t *)0x400FF054) // Port Data Direction Register
  2711. #define GPIOC_PDOR (*(volatile uint32_t *)0x400FF080) // Port Data Output Register
  2712. #define GPIOC_PSOR (*(volatile uint32_t *)0x400FF084) // Port Set Output Register
  2713. #define GPIOC_PCOR (*(volatile uint32_t *)0x400FF088) // Port Clear Output Register
  2714. #define GPIOC_PTOR (*(volatile uint32_t *)0x400FF08C) // Port Toggle Output Register
  2715. #define GPIOC_PDIR (*(volatile uint32_t *)0x400FF090) // Port Data Input Register
  2716. #define GPIOC_PDDR (*(volatile uint32_t *)0x400FF094) // Port Data Direction Register
  2717. #define GPIOD_PDOR (*(volatile uint32_t *)0x400FF0C0) // Port Data Output Register
  2718. #define GPIOD_PSOR (*(volatile uint32_t *)0x400FF0C4) // Port Set Output Register
  2719. #define GPIOD_PCOR (*(volatile uint32_t *)0x400FF0C8) // Port Clear Output Register
  2720. #define GPIOD_PTOR (*(volatile uint32_t *)0x400FF0CC) // Port Toggle Output Register
  2721. #define GPIOD_PDIR (*(volatile uint32_t *)0x400FF0D0) // Port Data Input Register
  2722. #define GPIOD_PDDR (*(volatile uint32_t *)0x400FF0D4) // Port Data Direction Register
  2723. #define GPIOE_PDOR (*(volatile uint32_t *)0x400FF100) // Port Data Output Register
  2724. #define GPIOE_PSOR (*(volatile uint32_t *)0x400FF104) // Port Set Output Register
  2725. #define GPIOE_PCOR (*(volatile uint32_t *)0x400FF108) // Port Clear Output Register
  2726. #define GPIOE_PTOR (*(volatile uint32_t *)0x400FF10C) // Port Toggle Output Register
  2727. #define GPIOE_PDIR (*(volatile uint32_t *)0x400FF110) // Port Data Input Register
  2728. #define GPIOE_PDDR (*(volatile uint32_t *)0x400FF114) // Port Data Direction Register
  2729. #if defined(KINETISL)
  2730. #define FGPIOA_PDOR (*(volatile uint32_t *)0xF8000000) // Port Data Output Register
  2731. #define FGPIOA_PSOR (*(volatile uint32_t *)0xF8000004) // Port Set Output Register
  2732. #define FGPIOA_PCOR (*(volatile uint32_t *)0xF8000008) // Port Clear Output Register
  2733. #define FGPIOA_PTOR (*(volatile uint32_t *)0xF800000C) // Port Toggle Output Register
  2734. #define FGPIOA_PDIR (*(volatile uint32_t *)0xF8000010) // Port Data Input Register
  2735. #define FGPIOA_PDDR (*(volatile uint32_t *)0xF8000014) // Port Data Direction Register
  2736. #define FGPIOB_PDOR (*(volatile uint32_t *)0xF8000040) // Port Data Output Register
  2737. #define FGPIOB_PSOR (*(volatile uint32_t *)0xF8000044) // Port Set Output Register
  2738. #define FGPIOB_PCOR (*(volatile uint32_t *)0xF8000048) // Port Clear Output Register
  2739. #define FGPIOB_PTOR (*(volatile uint32_t *)0xF800004C) // Port Toggle Output Register
  2740. #define FGPIOB_PDIR (*(volatile uint32_t *)0xF8000050) // Port Data Input Register
  2741. #define FGPIOB_PDDR (*(volatile uint32_t *)0xF8000054) // Port Data Direction Register
  2742. #define FGPIOC_PDOR (*(volatile uint32_t *)0xF8000080) // Port Data Output Register
  2743. #define FGPIOC_PSOR (*(volatile uint32_t *)0xF8000084) // Port Set Output Register
  2744. #define FGPIOC_PCOR (*(volatile uint32_t *)0xF8000088) // Port Clear Output Register
  2745. #define FGPIOC_PTOR (*(volatile uint32_t *)0xF800008C) // Port Toggle Output Register
  2746. #define FGPIOC_PDIR (*(volatile uint32_t *)0xF8000090) // Port Data Input Register
  2747. #define FGPIOC_PDDR (*(volatile uint32_t *)0xF8000094) // Port Data Direction Register
  2748. #define FGPIOD_PDOR (*(volatile uint32_t *)0xF80000C0) // Port Data Output Register
  2749. #define FGPIOD_PSOR (*(volatile uint32_t *)0xF80000C4) // Port Set Output Register
  2750. #define FGPIOD_PCOR (*(volatile uint32_t *)0xF80000C8) // Port Clear Output Register
  2751. #define FGPIOD_PTOR (*(volatile uint32_t *)0xF80000CC) // Port Toggle Output Register
  2752. #define FGPIOD_PDIR (*(volatile uint32_t *)0xF80000D0) // Port Data Input Register
  2753. #define FGPIOD_PDDR (*(volatile uint32_t *)0xF80000D4) // Port Data Direction Register
  2754. #define FGPIOE_PDOR (*(volatile uint32_t *)0xF8000100) // Port Data Output Register
  2755. #define FGPIOE_PSOR (*(volatile uint32_t *)0xF8000104) // Port Set Output Register
  2756. #define FGPIOE_PCOR (*(volatile uint32_t *)0xF8000108) // Port Clear Output Register
  2757. #define FGPIOE_PTOR (*(volatile uint32_t *)0xF800010C) // Port Toggle Output Register
  2758. #define FGPIOE_PDIR (*(volatile uint32_t *)0xF8000110) // Port Data Input Register
  2759. #define FGPIOE_PDDR (*(volatile uint32_t *)0xF8000114) // Port Data Direction Register
  2760. #endif
  2761. // Chapter 48: Touch sense input (TSI)
  2762. #if defined(KINETISK)
  2763. #define TSI0_GENCS (*(volatile uint32_t *)0x40045000) // General Control and Status Register
  2764. #define TSI_GENCS_LPCLKS ((uint32_t)0x10000000) //
  2765. #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
  2766. #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
  2767. #define TSI_GENCS_PS(n) (((n) & 7) << 16) //
  2768. #define TSI_GENCS_EOSF ((uint32_t)0x00008000) //
  2769. #define TSI_GENCS_OUTRGF ((uint32_t)0x00004000) //
  2770. #define TSI_GENCS_EXTERF ((uint32_t)0x00002000) //
  2771. #define TSI_GENCS_OVRF ((uint32_t)0x00001000) //
  2772. #define TSI_GENCS_SCNIP ((uint32_t)0x00000200) //
  2773. #define TSI_GENCS_SWTS ((uint32_t)0x00000100) //
  2774. #define TSI_GENCS_TSIEN ((uint32_t)0x00000080) //
  2775. #define TSI_GENCS_TSIIE ((uint32_t)0x00000040) //
  2776. #define TSI_GENCS_ERIE ((uint32_t)0x00000020) //
  2777. #define TSI_GENCS_ESOR ((uint32_t)0x00000010) //
  2778. #define TSI_GENCS_STM ((uint32_t)0x00000002) //
  2779. #define TSI_GENCS_STPE ((uint32_t)0x00000001) //
  2780. #define TSI0_SCANC (*(volatile uint32_t *)0x40045004) // SCAN Control Register
  2781. #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
  2782. #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
  2783. #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
  2784. #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
  2785. #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
  2786. #define TSI0_PEN (*(volatile uint32_t *)0x40045008) // Pin Enable Register
  2787. #define TSI0_WUCNTR (*(volatile uint32_t *)0x4004500C) // Wake-Up Channel Counter Register
  2788. #define TSI0_CNTR1 (*(volatile uint32_t *)0x40045100) // Counter Register
  2789. #define TSI0_CNTR3 (*(volatile uint32_t *)0x40045104) // Counter Register
  2790. #define TSI0_CNTR5 (*(volatile uint32_t *)0x40045108) // Counter Register
  2791. #define TSI0_CNTR7 (*(volatile uint32_t *)0x4004510C) // Counter Register
  2792. #define TSI0_CNTR9 (*(volatile uint32_t *)0x40045110) // Counter Register
  2793. #define TSI0_CNTR11 (*(volatile uint32_t *)0x40045114) // Counter Register
  2794. #define TSI0_CNTR13 (*(volatile uint32_t *)0x40045118) // Counter Register
  2795. #define TSI0_CNTR15 (*(volatile uint32_t *)0x4004511C) // Counter Register
  2796. #define TSI0_THRESHOLD (*(volatile uint32_t *)0x40045120) // Low Power Channel Threshold Register
  2797. #elif defined(KINETISL)
  2798. #define TSI0_GENCS (*(volatile uint32_t *)0x40045000) // General Control and Status
  2799. #define TSI_GENCS_OUTRGF ((uint32_t)0x80000000) // Out of Range Flag
  2800. #define TSI_GENCS_ESOR ((uint32_t)0x10000000) // End-of-scan or Out-of-Range Interrupt Selection
  2801. #define TSI_GENCS_MODE(n) (((n) & 15) << 24) // analog modes & status
  2802. #define TSI_GENCS_REFCHRG(n) (((n) & 7) << 21) // reference charge and discharge current
  2803. #define TSI_GENCS_DVOLT(n) (((n) & 3) << 19) // voltage rails
  2804. #define TSI_GENCS_EXTCHRG(n) (((n) & 7) << 16) // electrode charge and discharge current
  2805. #define TSI_GENCS_PS(n) (((n) & 7) << 13) // prescaler
  2806. #define TSI_GENCS_NSCN(n) (((n) & 31) << 8) // scan number
  2807. #define TSI_GENCS_TSIEN ((uint32_t)0x00000080) // Enable
  2808. #define TSI_GENCS_TSIIEN ((uint32_t)0x00000040) // Interrupt Enable
  2809. #define TSI_GENCS_STPE ((uint32_t)0x00000020) // STOP Enable
  2810. #define TSI_GENCS_STM ((uint32_t)0x00000010) // Trigger Mode
  2811. #define TSI_GENCS_SCNIP ((uint32_t)0x00000008) // Scan In Progress Status
  2812. #define TSI_GENCS_EOSF ((uint32_t)0x00000004) // End of Scan Flag
  2813. #define TSI_GENCS_CURSW ((uint32_t)0x00000002) // current sources swapped
  2814. #define TSI0_DATA (*(volatile uint32_t *)0x40045004) // Data
  2815. #define TSI_DATA_TSICH(n) (((n) & 15) << 28) // channel
  2816. #define TSI_DATA_DMAEN ((uint32_t)0x00800000) // DMA Transfer Enabled
  2817. #define TSI_DATA_SWTS ((uint32_t)0x00400000) // Software Trigger Start
  2818. #define TSI_DATA_TSICNT(n) (((n) & 65535) << 0) // Conversion Counter Value
  2819. #define TSI0_TSHD (*(volatile uint32_t *)0x40045008) // Threshold
  2820. #define TSI_TSHD_THRESH(n) (((n) & 65535) << 16) // High wakeup threshold
  2821. #define TSI_TSHD_THRESL(n) (((n) & 65535) << 0) // Low wakeup threshold
  2822. #endif
  2823. // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
  2824. #define NVIC_STIR (*(volatile uint32_t *)0xE000EF00)
  2825. #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + ((n) >> 5)) = (1 << ((n) & 31)))
  2826. #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + ((n) >> 5)) = (1 << ((n) & 31)))
  2827. #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + ((n) >> 5)) = (1 << ((n) & 31)))
  2828. #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + ((n) >> 5)) = (1 << ((n) & 31)))
  2829. #define NVIC_IS_PENDING(n) (*((volatile uint32_t *)0xE000E200 + ((n) >> 5)) & (1 << ((n) & 31)))
  2830. #define NVIC_IS_ACTIVE(n) (*((volatile uint32_t *)0xE000E300 + ((n) >> 5)) & (1 << ((n) & 31)))
  2831. #define NVIC_TRIGGER_IRQ(n) NVIC_STIR=(n)
  2832. #define NVIC_ISER0 (*(volatile uint32_t *)0xE000E100)
  2833. #define NVIC_ISER1 (*(volatile uint32_t *)0xE000E104)
  2834. #define NVIC_ISER2 (*(volatile uint32_t *)0xE000E108)
  2835. #define NVIC_ISER3 (*(volatile uint32_t *)0xE000E10C)
  2836. #define NVIC_ICER0 (*(volatile uint32_t *)0xE000E180)
  2837. #define NVIC_ICER1 (*(volatile uint32_t *)0xE000E184)
  2838. #define NVIC_ICER2 (*(volatile uint32_t *)0xE000E188)
  2839. #define NVIC_ICER3 (*(volatile uint32_t *)0xE000E18C)
  2840. // 0 = highest priority
  2841. // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240
  2842. // Cortex-M0: 0,64,128,192
  2843. #ifdef KINETISK
  2844. #define NVIC_SET_PRIORITY(irqnum, priority) (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))
  2845. #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))
  2846. #else
  2847. #define NVIC_SET_PRIORITY(irqnum, priority) (*((uint32_t *)0xE000E400 + ((irqnum) >> 2)) = (*((uint32_t *)0xE000E400 + ((irqnum) >> 2)) & (~(0xFF << (8 * ((irqnum) & 3))))) | (((priority) & 0xFF) << (8 * ((irqnum) & 3))))
  2848. #define NVIC_GET_PRIORITY(irqnum) (*((uint32_t *)0xE000E400 + ((irqnum) >> 2)) >> (8 * ((irqnum) & 3)) & 255)
  2849. #endif
  2850. #define __disable_irq() __asm__ volatile("CPSID i");
  2851. #define __enable_irq() __asm__ volatile("CPSIE i");
  2852. // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
  2853. #define SCB_CPUID (*(const uint32_t *)0xE000ED00) // CPUID Base Register
  2854. #define SCB_ICSR (*(volatile uint32_t *)0xE000ED04) // Interrupt Control and State
  2855. #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
  2856. #define SCB_VTOR (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset
  2857. #define SCB_AIRCR (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt and Reset Control
  2858. #define SCB_SCR (*(volatile uint32_t *)0xE000ED10) // System Control Register
  2859. #define SCB_CCR (*(volatile uint32_t *)0xE000ED14) // Configuration and Control
  2860. #define SCB_SHPR1 (*(volatile uint32_t *)0xE000ED18) // System Handler Priority Register 1
  2861. #define SCB_SHPR2 (*(volatile uint32_t *)0xE000ED1C) // System Handler Priority Register 2
  2862. #define SCB_SHPR3 (*(volatile uint32_t *)0xE000ED20) // System Handler Priority Register 3
  2863. #define SCB_SHCSR (*(volatile uint32_t *)0xE000ED24) // System Handler Control and State
  2864. #define SCB_CFSR (*(volatile uint32_t *)0xE000ED28) // Configurable Fault Status Register
  2865. #define SCB_HFSR (*(volatile uint32_t *)0xE000ED2C) // HardFault Status
  2866. #define SCB_DFSR (*(volatile uint32_t *)0xE000ED30) // Debug Fault Status
  2867. #define SCB_MMFAR (*(volatile uint32_t *)0xE000ED34) // MemManage Fault Address
  2868. #define SYST_CSR (*(volatile uint32_t *)0xE000E010) // SysTick Control and Status
  2869. #define SYST_CSR_COUNTFLAG ((uint32_t)0x00010000)
  2870. #define SYST_CSR_CLKSOURCE ((uint32_t)0x00000004)
  2871. #define SYST_CSR_TICKINT ((uint32_t)0x00000002)
  2872. #define SYST_CSR_ENABLE ((uint32_t)0x00000001)
  2873. #define SYST_RVR (*(volatile uint32_t *)0xE000E014) // SysTick Reload Value Register
  2874. #define SYST_CVR (*(volatile uint32_t *)0xE000E018) // SysTick Current Value Register
  2875. #define SYST_CALIB (*(const uint32_t *)0xE000E01C) // SysTick Calibration Value
  2876. #define ARM_DEMCR (*(volatile uint32_t *)0xE000EDFC) // Debug Exception and Monitor Control
  2877. #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
  2878. #define ARM_DWT_CTRL (*(volatile uint32_t *)0xE0001000) // DWT control register
  2879. #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
  2880. #define ARM_DWT_CYCCNT (*(volatile uint32_t *)0xE0001004) // Cycle count register
  2881. #ifdef __cplusplus
  2882. extern "C" {
  2883. #endif
  2884. extern int nvic_execution_priority(void);
  2885. extern void nmi_isr(void);
  2886. extern void hard_fault_isr(void);
  2887. extern void memmanage_fault_isr(void);
  2888. extern void bus_fault_isr(void);
  2889. extern void usage_fault_isr(void);
  2890. extern void svcall_isr(void);
  2891. extern void debugmonitor_isr(void);
  2892. extern void pendablesrvreq_isr(void);
  2893. extern void systick_isr(void);
  2894. extern void dma_ch0_isr(void);
  2895. extern void dma_ch1_isr(void);
  2896. extern void dma_ch2_isr(void);
  2897. extern void dma_ch3_isr(void);
  2898. extern void dma_ch4_isr(void);
  2899. extern void dma_ch5_isr(void);
  2900. extern void dma_ch6_isr(void);
  2901. extern void dma_ch7_isr(void);
  2902. extern void dma_ch8_isr(void);
  2903. extern void dma_ch9_isr(void);
  2904. extern void dma_ch10_isr(void);
  2905. extern void dma_ch11_isr(void);
  2906. extern void dma_ch12_isr(void);
  2907. extern void dma_ch13_isr(void);
  2908. extern void dma_ch14_isr(void);
  2909. extern void dma_ch15_isr(void);
  2910. extern void dma_error_isr(void);
  2911. extern void mcm_isr(void);
  2912. extern void flash_cmd_isr(void);
  2913. extern void flash_error_isr(void);
  2914. extern void low_voltage_isr(void);
  2915. extern void wakeup_isr(void);
  2916. extern void watchdog_isr(void);
  2917. extern void i2c0_isr(void);
  2918. extern void i2c1_isr(void);
  2919. extern void i2c2_isr(void);
  2920. extern void spi0_isr(void);
  2921. extern void spi1_isr(void);
  2922. extern void spi2_isr(void);
  2923. extern void sdhc_isr(void);
  2924. extern void can0_message_isr(void);
  2925. extern void can0_bus_off_isr(void);
  2926. extern void can0_error_isr(void);
  2927. extern void can0_tx_warn_isr(void);
  2928. extern void can0_rx_warn_isr(void);
  2929. extern void can0_wakeup_isr(void);
  2930. extern void i2s0_tx_isr(void);
  2931. extern void i2s0_rx_isr(void);
  2932. extern void i2s0_isr(void);
  2933. extern void uart0_lon_isr(void);
  2934. extern void uart0_status_isr(void);
  2935. extern void uart0_error_isr(void);
  2936. extern void uart1_status_isr(void);
  2937. extern void uart1_error_isr(void);
  2938. extern void uart2_status_isr(void);
  2939. extern void uart2_error_isr(void);
  2940. extern void uart3_status_isr(void);
  2941. extern void uart3_error_isr(void);
  2942. extern void uart4_status_isr(void);
  2943. extern void uart4_error_isr(void);
  2944. extern void uart5_status_isr(void);
  2945. extern void uart5_error_isr(void);
  2946. extern void adc0_isr(void);
  2947. extern void adc1_isr(void);
  2948. extern void cmp0_isr(void);
  2949. extern void cmp1_isr(void);
  2950. extern void cmp2_isr(void);
  2951. extern void ftm0_isr(void);
  2952. extern void ftm1_isr(void);
  2953. extern void ftm2_isr(void);
  2954. extern void ftm3_isr(void);
  2955. extern void cmt_isr(void);
  2956. extern void rtc_alarm_isr(void);
  2957. extern void rtc_seconds_isr(void);
  2958. extern void pit0_isr(void);
  2959. extern void pit1_isr(void);
  2960. extern void pit2_isr(void);
  2961. extern void pit3_isr(void);
  2962. extern void pit_isr(void);
  2963. extern void pdb_isr(void);
  2964. extern void usb_isr(void);
  2965. extern void usb_charge_isr(void);
  2966. extern void dac0_isr(void);
  2967. extern void dac1_isr(void);
  2968. extern void tsi0_isr(void);
  2969. extern void mcg_isr(void);
  2970. extern void lptmr_isr(void);
  2971. extern void porta_isr(void);
  2972. extern void portb_isr(void);
  2973. extern void portc_isr(void);
  2974. extern void portd_isr(void);
  2975. extern void porte_isr(void);
  2976. extern void portcd_isr(void);
  2977. extern void software_isr(void);
  2978. extern void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);
  2979. extern void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void);
  2980. #ifdef __cplusplus
  2981. }
  2982. #endif
  2983. #undef BEGIN_ENUM
  2984. #undef END_ENUM
  2985. #endif