Teensy 4.1 core updated for C++20
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DMAChannel.cpp 4.1KB

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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2017 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "DMAChannel.h"
  31. // only 16 channels supported, because we don't handle sharing interrupts
  32. #define DMA_MAX_CHANNELS 16
  33. // The channel allocation bitmask is accessible from "C" namespace,
  34. // so C-only code can reserve DMA channels
  35. uint16_t dma_channel_allocated_mask = 0;
  36. #ifdef CR
  37. #warning "CR is defined as something?"
  38. #endif
  39. void DMAChannel::begin(bool force_initialization)
  40. {
  41. uint32_t ch = 0;
  42. __disable_irq();
  43. if (!force_initialization && TCD && channel < DMA_MAX_CHANNELS
  44. && (dma_channel_allocated_mask & (1 << channel))
  45. && (uint32_t)TCD == (uint32_t)(0x400E9000 + channel * 32)) {
  46. // DMA channel already allocated
  47. __enable_irq();
  48. return;
  49. }
  50. while (1) {
  51. if (!(dma_channel_allocated_mask & (1 << ch))) {
  52. dma_channel_allocated_mask |= (1 << ch);
  53. __enable_irq();
  54. break;
  55. }
  56. if (++ch >= DMA_MAX_CHANNELS) {
  57. __enable_irq();
  58. TCD = (TCD_t *)0;
  59. channel = DMA_MAX_CHANNELS;
  60. return; // no more channels available
  61. // attempts to use this object will hardfault
  62. }
  63. }
  64. channel = ch;
  65. CCM_CCGR5 |= CCM_CCGR5_DMA(CCM_CCGR_ON);
  66. DMA_CR = DMA_CR_GRP1PRI | DMA_CR_EMLM | DMA_CR_EDBG;
  67. DMA_CERQ = ch;
  68. DMA_CERR = ch;
  69. DMA_CEEI = ch;
  70. DMA_CINT = ch;
  71. TCD = (TCD_t *)(0x400E9000 + ch * 32);
  72. uint32_t *p = (uint32_t *)TCD;
  73. *p++ = 0;
  74. *p++ = 0;
  75. *p++ = 0;
  76. *p++ = 0;
  77. *p++ = 0;
  78. *p++ = 0;
  79. *p++ = 0;
  80. *p++ = 0;
  81. }
  82. void DMAChannel::release(void)
  83. {
  84. if (channel >= DMA_MAX_CHANNELS) return;
  85. DMA_CERQ = channel;
  86. __disable_irq();
  87. dma_channel_allocated_mask &= ~(1 << channel);
  88. __enable_irq();
  89. channel = DMA_MAX_CHANNELS;
  90. TCD = (TCD_t *)0;
  91. }
  92. static uint32_t priority(const DMAChannel &c)
  93. {
  94. uint32_t n;
  95. n = *(uint32_t *)((uint32_t)&DMA_DCHPRI3 + (c.channel & 0xFC));
  96. n = __builtin_bswap32(n);
  97. return (n >> ((c.channel & 0x03) << 3)) & 0x0F;
  98. }
  99. static void swap(DMAChannel &c1, DMAChannel &c2)
  100. {
  101. uint8_t c;
  102. DMABaseClass::TCD_t *t;
  103. c = c1.channel;
  104. c1.channel = c2.channel;
  105. c2.channel = c;
  106. t = c1.TCD;
  107. c1.TCD = c2.TCD;
  108. c2.TCD = t;
  109. }
  110. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2)
  111. {
  112. if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
  113. }
  114. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3)
  115. {
  116. if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
  117. if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
  118. if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
  119. }
  120. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3, DMAChannel &ch4)
  121. {
  122. if (priority(ch3) < priority(ch4)) swap(ch3, ch4);
  123. if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
  124. if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
  125. if (priority(ch3) < priority(ch4)) swap(ch2, ch3);
  126. if (priority(ch2) < priority(ch3)) swap(ch1, ch2);
  127. if (priority(ch3) < priority(ch4)) swap(ch2, ch3);
  128. }