| #define CORE_PIN33_PINREG GPIO4_PSR | #define CORE_PIN33_PINREG GPIO4_PSR | ||||
| // mux config registers control which peripheral uses the pin | // mux config registers control which peripheral uses the pin | ||||
| #define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 | |||||
| #define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 | |||||
| #define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 | |||||
| #define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 | |||||
| #define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 | #define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 | ||||
| #define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 | #define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 | ||||
| #define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 | #define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 |