|
|
|
|
|
|
|
|
#define SNVS_HPLR (IMXRT_SNVS.offset000) |
|
|
#define SNVS_HPLR (IMXRT_SNVS.offset000) |
|
|
#define SNVS_HPCOMR (IMXRT_SNVS.offset004) |
|
|
#define SNVS_HPCOMR (IMXRT_SNVS.offset004) |
|
|
#define SNVS_HPCR (IMXRT_SNVS.offset008) |
|
|
#define SNVS_HPCR (IMXRT_SNVS.offset008) |
|
|
#define SNVS_HPSICR (IMXRT_SNVS.offset00C) |
|
|
|
|
|
#define SNVS_HPSVCR (IMXRT_SNVS.offset010) |
|
|
|
|
|
|
|
|
#define SNVS_HPSICR (IMXRT_SNVS.offset00C) |
|
|
|
|
|
#define SNVS_HPSVCR (IMXRT_SNVS.offset010) |
|
|
#define SNVS_HPSR (IMXRT_SNVS.offset014) |
|
|
#define SNVS_HPSR (IMXRT_SNVS.offset014) |
|
|
#define SNVS_HPSVSR (IMXRT_SNVS.offset018) |
|
|
|
|
|
#define SNVS_HPHACIVR (IMXRT_SNVS.offset01C) |
|
|
|
|
|
#define SNVS_HPHACR (IMXRT_SNVS.offset020) |
|
|
|
|
|
#define SNVS_HPRTCMR (IMXRT_SNVS.offset024) |
|
|
|
|
|
#define SNVS_HPRTCLR (IMXRT_SNVS.offset028) |
|
|
|
|
|
|
|
|
#define SNVS_HPSVSR (IMXRT_SNVS.offset018) |
|
|
|
|
|
#define SNVS_HPHACIVR (IMXRT_SNVS.offset01C) |
|
|
|
|
|
#define SNVS_HPHACR (IMXRT_SNVS.offset020) |
|
|
|
|
|
#define SNVS_HPRTCMR (IMXRT_SNVS.offset024) |
|
|
|
|
|
#define SNVS_HPRTCLR (IMXRT_SNVS.offset028) |
|
|
#define SNVS_HPTAMR (IMXRT_SNVS.offset02C) |
|
|
#define SNVS_HPTAMR (IMXRT_SNVS.offset02C) |
|
|
#define SNVS_HPTALR (IMXRT_SNVS.offset030) |
|
|
#define SNVS_HPTALR (IMXRT_SNVS.offset030) |
|
|
#define SNVS_LPLR (IMXRT_SNVS.offset034) |
|
|
#define SNVS_LPLR (IMXRT_SNVS.offset034) |
|
|
#define SNVS_LPCR (IMXRT_SNVS.offset038) |
|
|
#define SNVS_LPCR (IMXRT_SNVS.offset038) |
|
|
#define SNVS_LPMKCR (IMXRT_SNVS.offset03C) |
|
|
|
|
|
#define SNVS_LPSVCR (IMXRT_SNVS.offset040) |
|
|
|
|
|
#define SNVS_LPTDCR (IMXRT_SNVS.offset048) |
|
|
|
|
|
|
|
|
#define SNVS_LPMKCR (IMXRT_SNVS.offset03C) |
|
|
|
|
|
#define SNVS_LPSVCR (IMXRT_SNVS.offset040) |
|
|
|
|
|
#define SNVS_LPTDCR (IMXRT_SNVS.offset048) |
|
|
#define SNVS_LPSR (IMXRT_SNVS.offset04C) |
|
|
#define SNVS_LPSR (IMXRT_SNVS.offset04C) |
|
|
#define SNVS_LPSRTCMR (IMXRT_SNVS.offset050) |
|
|
|
|
|
#define SNVS_LPSRTCLR (IMXRT_SNVS.offset054) |
|
|
|
|
|
|
|
|
#define SNVS_LPSRTCMR (IMXRT_SNVS.offset050) |
|
|
|
|
|
#define SNVS_LPSRTCLR (IMXRT_SNVS.offset054) |
|
|
#define SNVS_LPTAR (IMXRT_SNVS.offset058) |
|
|
#define SNVS_LPTAR (IMXRT_SNVS.offset058) |
|
|
#define SNVS_LPSMCMR (IMXRT_SNVS.offset05C) |
|
|
|
|
|
#define SNVS_LPSMCLR (IMXRT_SNVS.offset060) |
|
|
|
|
|
#define SNVS_LPPGDR (IMXRT_SNVS.offset064) |
|
|
|
|
|
|
|
|
#define SNVS_LPSMCMR (IMXRT_SNVS.offset05C) |
|
|
|
|
|
#define SNVS_LPSMCLR (IMXRT_SNVS.offset060) |
|
|
|
|
|
#define SNVS_LPPGDR (IMXRT_SNVS.offset064) |
|
|
#define SNVS_LPGPR (IMXRT_SNVS.offset068) |
|
|
#define SNVS_LPGPR (IMXRT_SNVS.offset068) |
|
|
#define IMXRT_SNVS_b (*(IMXRT_REGISTER32_t *)0x400D4800) |
|
|
|
|
|
|
|
|
#define IMXRT_SNVS_b (*(IMXRT_REGISTER32_t *)0x400D4800) |
|
|
#define SNVS_HPVIDR1 (IMXRT_SNVS_b.offset3F8) |
|
|
#define SNVS_HPVIDR1 (IMXRT_SNVS_b.offset3F8) |
|
|
#define SNVS_HPVIDR2 (IMXRT_SNVS_b.offset3FC) |
|
|
#define SNVS_HPVIDR2 (IMXRT_SNVS_b.offset3FC) |
|
|
|
|
|
#define SNVS_HPCR_BTN_MASK ((uint32_t)(1 << 27)) |
|
|
|
|
|
#define SNVS_HPCR_BTN_CONFIG(n) ((uint32_t)(((n) & 0x07) << 24)) |
|
|
|
|
|
#define SNVS_HPCR_HP_TS ((uint32_t)(1 << 16)) |
|
|
|
|
|
#define SNVS_HPCR_HPCALB_VAL(n) ((uint32_t)(((n) & 0x1F) << 10)) |
|
|
|
|
|
#define SNVS_HPCR_HPCALB_EN ((uint32_t)(1 << 8)) |
|
|
|
|
|
#define SNVS_HPCR_PI_FREQ(n) ((uint32_t)(((n) & 0x0F) << 4)) |
|
|
|
|
|
#define SNVS_HPCR_PI_EN ((uint32_t)(1 << 3)) |
|
|
|
|
|
#define SNVS_HPCR_DIS_PI ((uint32_t)(1 << 2)) |
|
|
|
|
|
#define SNVS_HPCR_HPTA_EN ((uint32_t)(1 << 1)) |
|
|
|
|
|
#define SNVS_HPCR_RTC_EN ((uint32_t)(1 << 0)) |
|
|
#define SNVS_DEFAULT_PGD_VALUE (0x41736166U) |
|
|
#define SNVS_DEFAULT_PGD_VALUE (0x41736166U) |
|
|
#define SNVS_LPSR_PGD_MASK (0x8) |
|
|
|
|
|
#define SNVS_LPCR_SRTC_ENV_MASK (0x1) |
|
|
|
|
|
#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0x1) |
|
|
|
|
|
#define SNVS_LPCR_LPTA_EN_MASK (0x2) |
|
|
|
|
|
#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << 1)) & 0x2) |
|
|
|
|
|
#define SNVS_LPCR_MC_ENV_MASK (0x4) |
|
|
|
|
|
#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << 2)) & 0x4) |
|
|
|
|
|
#define SNVS_LPCR_LPWUI_EN_MASK (0x8) |
|
|
|
|
|
#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << 3)) & 0x8) |
|
|
|
|
|
#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10) |
|
|
|
|
|
#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << 4)) & 0x10) |
|
|
|
|
|
#define SNVS_LPCR_DP_EN_MASK (0x20) |
|
|
|
|
|
#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << 5)) & 0x20) |
|
|
|
|
|
#define SNVS_LPCR_TOP_MASK (0x40) |
|
|
|
|
|
#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << 6)) & 0x40) |
|
|
|
|
|
#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80) |
|
|
|
|
|
#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << 7)) & 0x80) |
|
|
|
|
|
#define SNVS_LPCR_LPCALB_EN_MASK (0x100) |
|
|
|
|
|
#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0x100) |
|
|
|
|
|
#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00) |
|
|
|
|
|
#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << 10)) & 0x7C00) |
|
|
|
|
|
#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000) |
|
|
|
|
|
#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x30000) |
|
|
|
|
|
#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000) |
|
|
|
|
|
#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << 18)) & 0xC0000) |
|
|
|
|
|
#define SNVS_LPCR_ON_TIME_MASK (0x300000) |
|
|
|
|
|
#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << 20)) & 0x300000) |
|
|
|
|
|
#define SNVS_LPCR_PK_EN_MASK (0x400000) |
|
|
|
|
|
#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << 22)) & 0x400000) |
|
|
|
|
|
#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000) |
|
|
|
|
|
#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << 23)) & 0x800000) |
|
|
|
|
|
#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000) |
|
|
|
|
|
#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0x1000000) |
|
|
|
|
|
#define SNVS_LPSR_LPTA (0x1) |
|
|
|
|
|
|
|
|
#define SNVS_LPCR_SRTC_ENV ((uint32_t)(1 << 0)) |
|
|
|
|
|
#define SNVS_LPCR_MC_ENV ((uint32_t)(1 << 2)) |
|
|
|
|
|
#define SNVS_LPCR_LPWUI_EN ((uint32_t)(1 << 3)) |
|
|
|
|
|
#define SNVS_LPCR_DP_EN ((uint32_t)(1 << 5)) |
|
|
|
|
|
#define SNVS_LPCR_TOP ((uint32_t)(1 << 6)) |
|
|
|
|
|
#define SNVS_LPCR_PWR_GLITCH_EN ((uint32_t)(1 << 7)) |
|
|
|
|
|
#define SNVS_LPCR_BTN_PRESS_TIME(n) ((uint32_t)(((n) & 0x03) << 16)) |
|
|
|
|
|
#define SNVS_LPCR_DEBOUNCE(n) ((uint32_t)(((n) & 0x03) << 18)) |
|
|
|
|
|
#define SNVS_LPCR_ON_TIME(n) ((uint32_t)(((n) & 0x03) << 20)) |
|
|
|
|
|
#define SNVS_LPCR_PK_EN ((uint32_t)(1 << 22)) |
|
|
|
|
|
#define SNVS_LPCR_PK_OVERRIDE ((uint32_t)(1 << 23)) |
|
|
|
|
|
|
|
|
// 51.5: page 2938 |
|
|
// 51.5: page 2938 |
|
|
#define IMXRT_SPDIF (*(IMXRT_REGISTER32_t *)0x40380000) |
|
|
#define IMXRT_SPDIF (*(IMXRT_REGISTER32_t *)0x40380000) |