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fix for flash & bus clock divider

teensy4-core
duff2013 9 years ago
parent
commit
0e5922acfb
1 changed files with 2 additions and 2 deletions
  1. +2
    -2
      teensy3/mk20dx128.c

+ 2
- 2
teensy3/mk20dx128.c View File

#if defined(KINETISK) #if defined(KINETISK)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1); SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1);
#elif defined(KINETISL) #elif defined(KINETISL)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(0);
#endif #endif
#elif F_CPU == 4000000 #elif F_CPU == 4000000
// config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash
#if defined(KINETISK) #if defined(KINETISK)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3); SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3);
#elif defined(KINETISL) #elif defined(KINETISL)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(3);
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);
#endif #endif
#elif F_CPU == 2000000 #elif F_CPU == 2000000
// since we are running from the fast internal reference clock 4MHz // since we are running from the fast internal reference clock 4MHz

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