| @@ -186,13 +186,13 @@ void serial2_end(void) | |||
| UART1_C2 = 0; | |||
| switch (rx_pin_num) { | |||
| case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE1 | |||
| #endif | |||
| } | |||
| switch (tx_pin_num & 127) { | |||
| case 10: CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE0 | |||
| #endif | |||
| } | |||
| @@ -222,7 +222,7 @@ void serial2_set_tx(uint8_t pin, uint8_t opendrain) | |||
| if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | |||
| switch (tx_pin_num & 127) { | |||
| case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 | |||
| #endif | |||
| } | |||
| @@ -233,7 +233,7 @@ void serial2_set_tx(uint8_t pin, uint8_t opendrain) | |||
| } | |||
| switch (pin & 127) { | |||
| case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; | |||
| #endif | |||
| } | |||
| @@ -249,13 +249,13 @@ void serial2_set_rx(uint8_t pin) | |||
| if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | |||
| switch (rx_pin_num) { | |||
| case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 | |||
| #endif | |||
| } | |||
| switch (pin) { | |||
| case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||
| case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | |||
| #endif | |||
| } | |||