PaulStoffregen
5 years ago
1 changed files with 689 additions and 2 deletions
+ 689
- 2
teensy4/imxrt.h
View File
| @@ -1143,6 +1143,7 @@ typedef struct { | |||
| #define CCM_CCGR4 (IMXRT_CCM.offset078) | |||
| #define CCM_CCGR5 (IMXRT_CCM.offset07C) | |||
| #define CCM_CCGR6 (IMXRT_CCM.offset080) | |||
| #define CCM_CCGR7 (IMXRT_CCM.offset084) | |||
| #define CCM_CMEOR (IMXRT_CCM.offset088) | |||
| #define CCM_CCR_RBC_EN ((uint32_t)(1<<27)) | |||
| #define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(((n) & 0x3F) << 21)) | |||
| @@ -1355,7 +1356,8 @@ typedef struct { | |||
| #define CCM_CCGR6_QTIMER1(n) ((uint32_t)(((n) & 0x03) << 26)) | |||
| #define CCM_CCGR6_LPI2C4_SERIAL(n) ((uint32_t)(((n) & 0x03) << 24)) | |||
| #define CCM_CCGR6_ANADIG(n) ((uint32_t)(((n) & 0x03) << 22)) | |||
| #define CCM_CCGR6_SIM_PER(n) ((uint32_t)(((n) & 0x03) << 20)) | |||
| #define CCM_CCGR6_SIM_PER(n) ((uint32_t)(((n) & 0x03) << 20)) /* IMXRT1052 */ | |||
| #define CCM_CCGR6_AXBS_P(n) ((uint32_t)(((n) & 0x03) << 20)) /* IMXRT1062 */ | |||
| #define CCM_CCGR6_AIPS_TZ3(n) ((uint32_t)(((n) & 0x03) << 18)) | |||
| #define CCM_CCGR6_QTIMER4(n) ((uint32_t)(((n) & 0x03) << 16)) | |||
| #define CCM_CCGR6_LPUART8(n) ((uint32_t)(((n) & 0x03) << 14)) | |||
| @@ -1366,6 +1368,13 @@ typedef struct { | |||
| #define CCM_CCGR6_USDHC2(n) ((uint32_t)(((n) & 0x03) << 4)) | |||
| #define CCM_CCGR6_USDHC1(n) ((uint32_t)(((n) & 0x03) << 2)) | |||
| #define CCM_CCGR6_USBOH3(n) ((uint32_t)(((n) & 0x03) << 0)) | |||
| #define CCM_CCGR7_FLEXIO3(n) ((uint32_t)(((n) & 0x03) << 12)) | |||
| #define CCM_CCGR7_APIS_LITE(n) ((uint32_t)(((n) & 0x03) << 10)) | |||
| #define CCM_CCGR7_CAN3_SERIAL(n) ((uint32_t)(((n) & 0x03) << 8)) | |||
| #define CCM_CCGR7_CAN3(n) ((uint32_t)(((n) & 0x03) << 6)) | |||
| #define CCM_CCGR7_AXBS_L(n) ((uint32_t)(((n) & 0x03) << 4)) | |||
| #define CCM_CCGR7_FLEXSPI2(n) ((uint32_t)(((n) & 0x03) << 2)) | |||
| #define CCM_CCGR7_ENET2(n) ((uint32_t)(((n) & 0x03) << 0)) | |||
| #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI ((uint32_t)(1<<30)) | |||
| #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI ((uint32_t)(1<<28)) | |||
| #define CCM_CMEOR_MOD_EN_OV_TRNG ((uint32_t)(1<<9)) | |||
| @@ -2611,6 +2620,113 @@ typedef struct { | |||
| #define ENET_TCSR3 (IMXRT_ENET_TIMER.offset220) | |||
| #define ENET_TCCR3 (IMXRT_ENET_TIMER.offset224) | |||
| #define IMXRT_ENET2 (*(IMXRT_REGISTER32_t *)0x402D4000) | |||
| #define IMXRT_ENET2_TIMER (*(IMXRT_REGISTER32_t *)0x402D4400) | |||
| #define ENET2_EIR (IMXRT_ENET2.offset004) | |||
| #define ENET2_EIMR (IMXRT_ENET2.offset008) | |||
| #define ENET2_RDAR (IMXRT_ENET2.offset010) | |||
| #define ENET2_TDAR (IMXRT_ENET2.offset014) | |||
| #define ENET2_ECR (IMXRT_ENET2.offset024) | |||
| #define ENET2_MMFR (IMXRT_ENET2.offset040) | |||
| #define ENET2_MSCR (IMXRT_ENET2.offset044) | |||
| #define ENET2_MIBC (IMXRT_ENET2.offset064) | |||
| #define ENET2_RCR (IMXRT_ENET2.offset084) | |||
| #define ENET2_TCR (IMXRT_ENET2.offset0C4) | |||
| #define ENET2_PALR (IMXRT_ENET2.offset0E4) | |||
| #define ENET2_PAUR (IMXRT_ENET2.offset0E8) | |||
| #define ENET2_OPD (IMXRT_ENET2.offset0EC) | |||
| #define ENET2_TXIC (IMXRT_ENET2.offset0F0) | |||
| #define ENET2_RXIC (IMXRT_ENET2.offset100) | |||
| #define ENET2_IAUR (IMXRT_ENET2.offset118) | |||
| #define ENET2_IALR (IMXRT_ENET2.offset11C) | |||
| #define ENET2_GAUR (IMXRT_ENET2.offset120) | |||
| #define ENET2_GALR (IMXRT_ENET2.offset124) | |||
| #define ENET2_TFWR (IMXRT_ENET2.offset144) | |||
| #define ENET2_RDSR (IMXRT_ENET2.offset180) | |||
| #define ENET2_TDSR (IMXRT_ENET2.offset184) | |||
| #define ENET2_MRBR (IMXRT_ENET2.offset188) | |||
| #define ENET2_RSFL (IMXRT_ENET2.offset190) | |||
| #define ENET2_RSEM (IMXRT_ENET2.offset194) | |||
| #define ENET2_RAEM (IMXRT_ENET2.offset198) | |||
| #define ENET2_RAFL (IMXRT_ENET2.offset19C) | |||
| #define ENET2_TSEM (IMXRT_ENET2.offset1A0) | |||
| #define ENET2_TAEM (IMXRT_ENET2.offset1A4) | |||
| #define ENET2_TAFL (IMXRT_ENET2.offset1A8) | |||
| #define ENET2_TIPG (IMXRT_ENET2.offset1AC) | |||
| #define ENET2_FTRL (IMXRT_ENET2.offset1B0) | |||
| #define ENET2_TACC (IMXRT_ENET2.offset1C0) | |||
| #define ENET2_RACC (IMXRT_ENET2.offset1C4) | |||
| #define ENET2_RMON_T_DROP (IMXRT_ENET2.offset200) | |||
| #define ENET2_RMON_T_PACKETS (IMXRT_ENET2.offset204) | |||
| #define ENET2_RMON_T_BC_PKT (IMXRT_ENET2.offset208) | |||
| #define ENET2_RMON_T_MC_PKT (IMXRT_ENET2.offset20C) | |||
| #define ENET2_RMON_T_CRC_ALIGN (IMXRT_ENET2.offset210) | |||
| #define ENET2_RMON_T_UNDERSIZE (IMXRT_ENET2.offset214) | |||
| #define ENET2_RMON_T_OVERSIZE (IMXRT_ENET2.offset218) | |||
| #define ENET2_RMON_T_FRAG (IMXRT_ENET2.offset21C) | |||
| #define ENET2_RMON_T_JAB (IMXRT_ENET2.offset220) | |||
| #define ENET2_RMON_T_COL (IMXRT_ENET2.offset224) | |||
| #define ENET2_RMON_T_P64 (IMXRT_ENET2.offset228) | |||
| #define ENET2_RMON_T_P65TO127 (IMXRT_ENET2.offset22C) | |||
| #define ENET2_RMON_T_P128TO255 (IMXRT_ENET2.offset230) | |||
| #define ENET2_RMON_T_P256TO511 (IMXRT_ENET2.offset234) | |||
| #define ENET2_RMON_T_P512TO1023 (IMXRT_ENET2.offset238) | |||
| #define ENET2_RMON_T_P1024TO2047 (IMXRT_ENET2.offset23C) | |||
| #define ENET2_RMON_T_P_GTE2048 (IMXRT_ENET2.offset240) | |||
| #define ENET2_RMON_T_OCTETS (IMXRT_ENET2.offset244) | |||
| #define ENET2_IEEE_T_DROP (IMXRT_ENET2.offset248) | |||
| #define ENET2_IEEE_T_FRAME_OK (IMXRT_ENET2.offset24C) | |||
| #define ENET2_IEEE_T_1COL (IMXRT_ENET2.offset250) | |||
| #define ENET2_IEEE_T_MCOL (IMXRT_ENET2.offset254) | |||
| #define ENET2_IEEE_T_DEF (IMXRT_ENET2.offset258) | |||
| #define ENET2_IEEE_T_LCOL (IMXRT_ENET2.offset25C) | |||
| #define ENET2_IEEE_T_EXCOL (IMXRT_ENET2.offset260) | |||
| #define ENET2_IEEE_T_MACERR (IMXRT_ENET2.offset264) | |||
| #define ENET2_IEEE_T_CSERR (IMXRT_ENET2.offset268) | |||
| #define ENET2_IEEE_T_SQE (IMXRT_ENET2.offset26C) | |||
| #define ENET2_IEEE_T_FDXFC (IMXRT_ENET2.offset270) | |||
| #define ENET2_IEEE_T_OCTETS_OK (IMXRT_ENET2.offset274) | |||
| #define ENET2_RMON_R_PACKETS (IMXRT_ENET2.offset284) | |||
| #define ENET2_RMON_R_BC_PKT (IMXRT_ENET2.offset288) | |||
| #define ENET2_RMON_R_MC_PKT (IMXRT_ENET2.offset28C) | |||
| #define ENET2_RMON_R_CRC_ALIGN (IMXRT_ENET2.offset290) | |||
| #define ENET2_RMON_R_UNDERSIZE (IMXRT_ENET2.offset294) | |||
| #define ENET2_RMON_R_OVERSIZE (IMXRT_ENET2.offset298) | |||
| #define ENET2_RMON_R_FRAG (IMXRT_ENET2.offset29C) | |||
| #define ENET2_RMON_R_JAB (IMXRT_ENET2.offset2A0) | |||
| #define ENET2_RMON_R_RESVD_0 (IMXRT_ENET2.offset2A4) | |||
| #define ENET2_RMON_R_P64 (IMXRT_ENET2.offset2A8) | |||
| #define ENET2_RMON_R_P65TO127 (IMXRT_ENET2.offset2AC) | |||
| #define ENET2_RMON_R_P128TO255 (IMXRT_ENET2.offset2B0) | |||
| #define ENET2_RMON_R_P256TO511 (IMXRT_ENET2.offset2B4) | |||
| #define ENET2_RMON_R_P512TO1023 (IMXRT_ENET2.offset2B8) | |||
| #define ENET2_RMON_R_P1024TO2047 (IMXRT_ENET2.offset2BC) | |||
| #define ENET2_RMON_R_P_GTE2048 (IMXRT_ENET2.offset2C0) | |||
| #define ENET2_RMON_R_OCTETS (IMXRT_ENET2.offset2C4) | |||
| #define ENET2_IEEE_R_DROP (IMXRT_ENET2.offset2C8) | |||
| #define ENET2_IEEE_R_FRAME_OK (IMXRT_ENET2.offset2CC) | |||
| #define ENET2_IEEE_R_CRC (IMXRT_ENET2.offset2D0) | |||
| #define ENET2_IEEE_R_ALIGN (IMXRT_ENET2.offset2D4) | |||
| #define ENET2_IEEE_R_MACERR (IMXRT_ENET2.offset2D8) | |||
| #define ENET2_IEEE_R_FDXFC (IMXRT_ENET2.offset2DC) | |||
| #define ENET2_IEEE_R_OCTETS_OK (IMXRT_ENET2.offset2E0) | |||
| #define ENET2_ATCR (IMXRT_ENET2_TIMER.offset000) | |||
| #define ENET2_ATVR (IMXRT_ENET2_TIMER.offset004) | |||
| #define ENET2_ATOFF (IMXRT_ENET2_TIMER.offset008) | |||
| #define ENET2_ATPER (IMXRT_ENET2_TIMER.offset00C) | |||
| #define ENET2_ATCOR (IMXRT_ENET2_TIMER.offset010) | |||
| #define ENET2_ATINC (IMXRT_ENET2_TIMER.offset014) | |||
| #define ENET2_ATSTMP (IMXRT_ENET2_TIMER.offset018) | |||
| #define ENET2_TGSR (IMXRT_ENET2_TIMER.offset204) | |||
| #define ENET2_TCSR0 (IMXRT_ENET2_TIMER.offset208) | |||
| #define ENET2_TCCR0 (IMXRT_ENET2_TIMER.offset20C) | |||
| #define ENET2_TCSR1 (IMXRT_ENET2_TIMER.offset210) | |||
| #define ENET2_TCCR1 (IMXRT_ENET2_TIMER.offset214) | |||
| #define ENET2_TCSR2 (IMXRT_ENET2_TIMER.offset218) | |||
| #define ENET2_TCCR2 (IMXRT_ENET2_TIMER.offset21C) | |||
| #define ENET2_TCSR3 (IMXRT_ENET2_TIMER.offset220) | |||
| #define ENET2_TCCR3 (IMXRT_ENET2_TIMER.offset224) | |||
| // 25.3.1.1: page 1199 | |||
| #define IMXRT_EWM (*(IMXRT_REGISTER8_t *)0x402D8000) | |||
| #define EWM_CTRL (IMXRT_EWM.offset00) | |||
| @@ -2790,6 +2906,294 @@ typedef struct { | |||
| #define FLEXCAN2_RXIMR63 (IMXRT_FLEXCAN2_MASK.offset17C) | |||
| #define FLEXCAN2_GFWR (IMXRT_FLEXCAN2_MASK.offset1E0) | |||
| #define IMXRT_FLEXCAN3 (*(IMXRT_REGISTER32_t *)0x401D8000) | |||
| #define IMXRT_FLEXCAN3_MASK (*(IMXRT_REGISTER32_t *)0x401D8800) | |||
| #define IMXRT_FLEXCAN3_EXT (*(IMXRT_REGISTER32_t *)0x401D8B00) | |||
| #define IMXRT_FLEXCAN3_ERXFIFO (*(IMXRT_REGISTER32_t *)0x401DB000) | |||
| #define FLEXCAN3_MCR (IMXRT_FLEXCAN3.offset000) | |||
| #define FLEXCAN3_CTRL1 (IMXRT_FLEXCAN3.offset004) | |||
| #define FLEXCAN3_TIMER (IMXRT_FLEXCAN3.offset008) | |||
| #define FLEXCAN3_RXMGMASK (IMXRT_FLEXCAN3.offset010) | |||
| #define FLEXCAN3_RX14MASK (IMXRT_FLEXCAN3.offset014) | |||
| #define FLEXCAN3_RX15MASK (IMXRT_FLEXCAN3.offset018) | |||
| #define FLEXCAN3_ECR (IMXRT_FLEXCAN3.offset01C) | |||
| #define FLEXCAN3_ESR1 (IMXRT_FLEXCAN3.offset020) | |||
| #define FLEXCAN3_IMASK2 (IMXRT_FLEXCAN3.offset024) | |||
| #define FLEXCAN3_IMASK1 (IMXRT_FLEXCAN3.offset028) | |||
| #define FLEXCAN3_IFLAG2 (IMXRT_FLEXCAN3.offset02C) | |||
| #define FLEXCAN3_IFLAG1 (IMXRT_FLEXCAN3.offset030) | |||
| #define FLEXCAN3_CTRL2 (IMXRT_FLEXCAN3.offset034) | |||
| #define FLEXCAN3_ESR2 (IMXRT_FLEXCAN3.offset038) | |||
| #define FLEXCAN3_CRCR (IMXRT_FLEXCAN3.offset044) | |||
| #define FLEXCAN3_RXFGMASK (IMXRT_FLEXCAN3.offset048) | |||
| #define FLEXCAN3_RXFIR (IMXRT_FLEXCAN3.offset04C) | |||
| #define FLEXCAN3_RXIMR0 (IMXRT_FLEXCAN3_MASK.offset080) | |||
| #define FLEXCAN3_RXIMR1 (IMXRT_FLEXCAN3_MASK.offset084) | |||
| #define FLEXCAN3_RXIMR2 (IMXRT_FLEXCAN3_MASK.offset088) | |||
| #define FLEXCAN3_RXIMR3 (IMXRT_FLEXCAN3_MASK.offset08C) | |||
| #define FLEXCAN3_RXIMR4 (IMXRT_FLEXCAN3_MASK.offset090) | |||
| #define FLEXCAN3_RXIMR5 (IMXRT_FLEXCAN3_MASK.offset094) | |||
| #define FLEXCAN3_RXIMR6 (IMXRT_FLEXCAN3_MASK.offset098) | |||
| #define FLEXCAN3_RXIMR7 (IMXRT_FLEXCAN3_MASK.offset09C) | |||
| #define FLEXCAN3_RXIMR8 (IMXRT_FLEXCAN3_MASK.offset0A0) | |||
| #define FLEXCAN3_RXIMR9 (IMXRT_FLEXCAN3_MASK.offset0A4) | |||
| #define FLEXCAN3_RXIMR10 (IMXRT_FLEXCAN3_MASK.offset0A8) | |||
| #define FLEXCAN3_RXIMR11 (IMXRT_FLEXCAN3_MASK.offset0AC) | |||
| #define FLEXCAN3_RXIMR12 (IMXRT_FLEXCAN3_MASK.offset0B0) | |||
| #define FLEXCAN3_RXIMR13 (IMXRT_FLEXCAN3_MASK.offset0B4) | |||
| #define FLEXCAN3_RXIMR14 (IMXRT_FLEXCAN3_MASK.offset0B8) | |||
| #define FLEXCAN3_RXIMR15 (IMXRT_FLEXCAN3_MASK.offset0BC) | |||
| #define FLEXCAN3_RXIMR16 (IMXRT_FLEXCAN3_MASK.offset0C0) | |||
| #define FLEXCAN3_RXIMR17 (IMXRT_FLEXCAN3_MASK.offset0C4) | |||
| #define FLEXCAN3_RXIMR18 (IMXRT_FLEXCAN3_MASK.offset0C8) | |||
| #define FLEXCAN3_RXIMR19 (IMXRT_FLEXCAN3_MASK.offset0CC) | |||
| #define FLEXCAN3_RXIMR20 (IMXRT_FLEXCAN3_MASK.offset0D0) | |||
| #define FLEXCAN3_RXIMR21 (IMXRT_FLEXCAN3_MASK.offset0D4) | |||
| #define FLEXCAN3_RXIMR22 (IMXRT_FLEXCAN3_MASK.offset0D8) | |||
| #define FLEXCAN3_RXIMR23 (IMXRT_FLEXCAN3_MASK.offset0DC) | |||
| #define FLEXCAN3_RXIMR24 (IMXRT_FLEXCAN3_MASK.offset0E0) | |||
| #define FLEXCAN3_RXIMR25 (IMXRT_FLEXCAN3_MASK.offset0E4) | |||
| #define FLEXCAN3_RXIMR26 (IMXRT_FLEXCAN3_MASK.offset0E8) | |||
| #define FLEXCAN3_RXIMR27 (IMXRT_FLEXCAN3_MASK.offset0EC) | |||
| #define FLEXCAN3_RXIMR28 (IMXRT_FLEXCAN3_MASK.offset0F0) | |||
| #define FLEXCAN3_RXIMR29 (IMXRT_FLEXCAN3_MASK.offset0F4) | |||
| #define FLEXCAN3_RXIMR30 (IMXRT_FLEXCAN3_MASK.offset0F8) | |||
| #define FLEXCAN3_RXIMR31 (IMXRT_FLEXCAN3_MASK.offset0FC) | |||
| #define FLEXCAN3_RXIMR32 (IMXRT_FLEXCAN3_MASK.offset100) | |||
| #define FLEXCAN3_RXIMR33 (IMXRT_FLEXCAN3_MASK.offset104) | |||
| #define FLEXCAN3_RXIMR34 (IMXRT_FLEXCAN3_MASK.offset108) | |||
| #define FLEXCAN3_RXIMR35 (IMXRT_FLEXCAN3_MASK.offset10C) | |||
| #define FLEXCAN3_RXIMR36 (IMXRT_FLEXCAN3_MASK.offset110) | |||
| #define FLEXCAN3_RXIMR37 (IMXRT_FLEXCAN3_MASK.offset114) | |||
| #define FLEXCAN3_RXIMR38 (IMXRT_FLEXCAN3_MASK.offset118) | |||
| #define FLEXCAN3_RXIMR39 (IMXRT_FLEXCAN3_MASK.offset11C) | |||
| #define FLEXCAN3_RXIMR40 (IMXRT_FLEXCAN3_MASK.offset120) | |||
| #define FLEXCAN3_RXIMR41 (IMXRT_FLEXCAN3_MASK.offset124) | |||
| #define FLEXCAN3_RXIMR42 (IMXRT_FLEXCAN3_MASK.offset128) | |||
| #define FLEXCAN3_RXIMR43 (IMXRT_FLEXCAN3_MASK.offset12C) | |||
| #define FLEXCAN3_RXIMR44 (IMXRT_FLEXCAN3_MASK.offset130) | |||
| #define FLEXCAN3_RXIMR45 (IMXRT_FLEXCAN3_MASK.offset134) | |||
| #define FLEXCAN3_RXIMR46 (IMXRT_FLEXCAN3_MASK.offset138) | |||
| #define FLEXCAN3_RXIMR47 (IMXRT_FLEXCAN3_MASK.offset13C) | |||
| #define FLEXCAN3_RXIMR48 (IMXRT_FLEXCAN3_MASK.offset140) | |||
| #define FLEXCAN3_RXIMR49 (IMXRT_FLEXCAN3_MASK.offset144) | |||
| #define FLEXCAN3_RXIMR50 (IMXRT_FLEXCAN3_MASK.offset148) | |||
| #define FLEXCAN3_RXIMR51 (IMXRT_FLEXCAN3_MASK.offset14C) | |||
| #define FLEXCAN3_RXIMR52 (IMXRT_FLEXCAN3_MASK.offset150) | |||
| #define FLEXCAN3_RXIMR53 (IMXRT_FLEXCAN3_MASK.offset154) | |||
| #define FLEXCAN3_RXIMR54 (IMXRT_FLEXCAN3_MASK.offset158) | |||
| #define FLEXCAN3_RXIMR55 (IMXRT_FLEXCAN3_MASK.offset15C) | |||
| #define FLEXCAN3_RXIMR56 (IMXRT_FLEXCAN3_MASK.offset160) | |||
| #define FLEXCAN3_RXIMR57 (IMXRT_FLEXCAN3_MASK.offset164) | |||
| #define FLEXCAN3_RXIMR58 (IMXRT_FLEXCAN3_MASK.offset168) | |||
| #define FLEXCAN3_RXIMR59 (IMXRT_FLEXCAN3_MASK.offset16C) | |||
| #define FLEXCAN3_RXIMR60 (IMXRT_FLEXCAN3_MASK.offset170) | |||
| #define FLEXCAN3_RXIMR61 (IMXRT_FLEXCAN3_MASK.offset174) | |||
| #define FLEXCAN3_RXIMR62 (IMXRT_FLEXCAN3_MASK.offset178) | |||
| #define FLEXCAN3_RXIMR63 (IMXRT_FLEXCAN3_MASK.offset17C) | |||
| #define FLEXCAN3_EPRS (IMXRT_FLEXCAN3_EXT.offset0F0) | |||
| #define FLEXCAN3_ENCBT (IMXRT_FLEXCAN3_EXT.offset0F4) | |||
| #define FLEXCAN3_EDCBT (IMXRT_FLEXCAN3_EXT.offset0F8) | |||
| #define FLEXCAN3_ETDC (IMXRT_FLEXCAN3_EXT.offset0FC) | |||
| #define FLEXCAN3_FDCTRL (IMXRT_FLEXCAN3_EXT.offset100) | |||
| #define FLEXCAN3_FDCBT (IMXRT_FLEXCAN3_EXT.offset104) | |||
| #define FLEXCAN3_FDCRC (IMXRT_FLEXCAN3_EXT.offset108) | |||
| #define FLEXCAN3_ERFCR (IMXRT_FLEXCAN3_EXT.offset10C) | |||
| #define FLEXCAN3_ERFIER (IMXRT_FLEXCAN3_EXT.offset110) | |||
| #define FLEXCAN3_ERFSR (IMXRT_FLEXCAN3_EXT.offset114) | |||
| #define FLEXCAN3_HR_TIME_STAMP0 (IMXRT_FLEXCAN3_EXT.offset130) | |||
| #define FLEXCAN3_HR_TIME_STAMP1 (IMXRT_FLEXCAN3_EXT.offset134) | |||
| #define FLEXCAN3_HR_TIME_STAMP2 (IMXRT_FLEXCAN3_EXT.offset138) | |||
| #define FLEXCAN3_HR_TIME_STAMP3 (IMXRT_FLEXCAN3_EXT.offset13C) | |||
| #define FLEXCAN3_HR_TIME_STAMP4 (IMXRT_FLEXCAN3_EXT.offset140) | |||
| #define FLEXCAN3_HR_TIME_STAMP5 (IMXRT_FLEXCAN3_EXT.offset144) | |||
| #define FLEXCAN3_HR_TIME_STAMP6 (IMXRT_FLEXCAN3_EXT.offset148) | |||
| #define FLEXCAN3_HR_TIME_STAMP7 (IMXRT_FLEXCAN3_EXT.offset14C) | |||
| #define FLEXCAN3_HR_TIME_STAMP8 (IMXRT_FLEXCAN3_EXT.offset150) | |||
| #define FLEXCAN3_HR_TIME_STAMP9 (IMXRT_FLEXCAN3_EXT.offset154) | |||
| #define FLEXCAN3_HR_TIME_STAMP10 (IMXRT_FLEXCAN3_EXT.offset158) | |||
| #define FLEXCAN3_HR_TIME_STAMP11 (IMXRT_FLEXCAN3_EXT.offset15C) | |||
| #define FLEXCAN3_HR_TIME_STAMP12 (IMXRT_FLEXCAN3_EXT.offset160) | |||
| #define FLEXCAN3_HR_TIME_STAMP13 (IMXRT_FLEXCAN3_EXT.offset164) | |||
| #define FLEXCAN3_HR_TIME_STAMP14 (IMXRT_FLEXCAN3_EXT.offset168) | |||
| #define FLEXCAN3_HR_TIME_STAMP15 (IMXRT_FLEXCAN3_EXT.offset16C) | |||
| #define FLEXCAN3_HR_TIME_STAMP16 (IMXRT_FLEXCAN3_EXT.offset170) | |||
| #define FLEXCAN3_HR_TIME_STAMP17 (IMXRT_FLEXCAN3_EXT.offset174) | |||
| #define FLEXCAN3_HR_TIME_STAMP18 (IMXRT_FLEXCAN3_EXT.offset178) | |||
| #define FLEXCAN3_HR_TIME_STAMP19 (IMXRT_FLEXCAN3_EXT.offset17C) | |||
| #define FLEXCAN3_HR_TIME_STAMP20 (IMXRT_FLEXCAN3_EXT.offset180) | |||
| #define FLEXCAN3_HR_TIME_STAMP21 (IMXRT_FLEXCAN3_EXT.offset184) | |||
| #define FLEXCAN3_HR_TIME_STAMP22 (IMXRT_FLEXCAN3_EXT.offset188) | |||
| #define FLEXCAN3_HR_TIME_STAMP23 (IMXRT_FLEXCAN3_EXT.offset18C) | |||
| #define FLEXCAN3_HR_TIME_STAMP24 (IMXRT_FLEXCAN3_EXT.offset190) | |||
| #define FLEXCAN3_HR_TIME_STAMP25 (IMXRT_FLEXCAN3_EXT.offset194) | |||
| #define FLEXCAN3_HR_TIME_STAMP26 (IMXRT_FLEXCAN3_EXT.offset198) | |||
| #define FLEXCAN3_HR_TIME_STAMP27 (IMXRT_FLEXCAN3_EXT.offset19C) | |||
| #define FLEXCAN3_HR_TIME_STAMP28 (IMXRT_FLEXCAN3_EXT.offset1A0) | |||
| #define FLEXCAN3_HR_TIME_STAMP29 (IMXRT_FLEXCAN3_EXT.offset1A4) | |||
| #define FLEXCAN3_HR_TIME_STAMP30 (IMXRT_FLEXCAN3_EXT.offset1A8) | |||
| #define FLEXCAN3_HR_TIME_STAMP31 (IMXRT_FLEXCAN3_EXT.offset1AC) | |||
| #define FLEXCAN3_HR_TIME_STAMP32 (IMXRT_FLEXCAN3_EXT.offset1B0) | |||
| #define FLEXCAN3_HR_TIME_STAMP33 (IMXRT_FLEXCAN3_EXT.offset1B4) | |||
| #define FLEXCAN3_HR_TIME_STAMP34 (IMXRT_FLEXCAN3_EXT.offset1B8) | |||
| #define FLEXCAN3_HR_TIME_STAMP35 (IMXRT_FLEXCAN3_EXT.offset1BC) | |||
| #define FLEXCAN3_HR_TIME_STAMP36 (IMXRT_FLEXCAN3_EXT.offset1C0) | |||
| #define FLEXCAN3_HR_TIME_STAMP37 (IMXRT_FLEXCAN3_EXT.offset1C4) | |||
| #define FLEXCAN3_HR_TIME_STAMP38 (IMXRT_FLEXCAN3_EXT.offset1C8) | |||
| #define FLEXCAN3_HR_TIME_STAMP39 (IMXRT_FLEXCAN3_EXT.offset1CC) | |||
| #define FLEXCAN3_HR_TIME_STAMP40 (IMXRT_FLEXCAN3_EXT.offset1D0) | |||
| #define FLEXCAN3_HR_TIME_STAMP41 (IMXRT_FLEXCAN3_EXT.offset1D4) | |||
| #define FLEXCAN3_HR_TIME_STAMP42 (IMXRT_FLEXCAN3_EXT.offset1D8) | |||
| #define FLEXCAN3_HR_TIME_STAMP43 (IMXRT_FLEXCAN3_EXT.offset1DC) | |||
| #define FLEXCAN3_HR_TIME_STAMP44 (IMXRT_FLEXCAN3_EXT.offset1E0) | |||
| #define FLEXCAN3_HR_TIME_STAMP45 (IMXRT_FLEXCAN3_EXT.offset1E4) | |||
| #define FLEXCAN3_HR_TIME_STAMP46 (IMXRT_FLEXCAN3_EXT.offset1E8) | |||
| #define FLEXCAN3_HR_TIME_STAMP47 (IMXRT_FLEXCAN3_EXT.offset1EC) | |||
| #define FLEXCAN3_HR_TIME_STAMP48 (IMXRT_FLEXCAN3_EXT.offset1F0) | |||
| #define FLEXCAN3_HR_TIME_STAMP49 (IMXRT_FLEXCAN3_EXT.offset1F4) | |||
| #define FLEXCAN3_HR_TIME_STAMP50 (IMXRT_FLEXCAN3_EXT.offset1F8) | |||
| #define FLEXCAN3_HR_TIME_STAMP51 (IMXRT_FLEXCAN3_EXT.offset1FC) | |||
| #define FLEXCAN3_HR_TIME_STAMP52 (IMXRT_FLEXCAN3_EXT.offset200) | |||
| #define FLEXCAN3_HR_TIME_STAMP53 (IMXRT_FLEXCAN3_EXT.offset204) | |||
| #define FLEXCAN3_HR_TIME_STAMP54 (IMXRT_FLEXCAN3_EXT.offset208) | |||
| #define FLEXCAN3_HR_TIME_STAMP55 (IMXRT_FLEXCAN3_EXT.offset20C) | |||
| #define FLEXCAN3_HR_TIME_STAMP56 (IMXRT_FLEXCAN3_EXT.offset210) | |||
| #define FLEXCAN3_HR_TIME_STAMP57 (IMXRT_FLEXCAN3_EXT.offset234) | |||
| #define FLEXCAN3_HR_TIME_STAMP58 (IMXRT_FLEXCAN3_EXT.offset218) | |||
| #define FLEXCAN3_HR_TIME_STAMP59 (IMXRT_FLEXCAN3_EXT.offset21C) | |||
| #define FLEXCAN3_HR_TIME_STAMP60 (IMXRT_FLEXCAN3_EXT.offset220) | |||
| #define FLEXCAN3_HR_TIME_STAMP61 (IMXRT_FLEXCAN3_EXT.offset224) | |||
| #define FLEXCAN3_HR_TIME_STAMP62 (IMXRT_FLEXCAN3_EXT.offset228) | |||
| #define FLEXCAN3_HR_TIME_STAMP63 (IMXRT_FLEXCAN3_EXT.offset22C) | |||
| #define FLEXCAN3_ERFFEL0 (IMXRT_FLEXCAN3_ERXFIFO.offset000) | |||
| #define FLEXCAN3_ERFFEL1 (IMXRT_FLEXCAN3_ERXFIFO.offset004) | |||
| #define FLEXCAN3_ERFFEL2 (IMXRT_FLEXCAN3_ERXFIFO.offset008) | |||
| #define FLEXCAN3_ERFFEL3 (IMXRT_FLEXCAN3_ERXFIFO.offset00C) | |||
| #define FLEXCAN3_ERFFEL4 (IMXRT_FLEXCAN3_ERXFIFO.offset010) | |||
| #define FLEXCAN3_ERFFEL5 (IMXRT_FLEXCAN3_ERXFIFO.offset014) | |||
| #define FLEXCAN3_ERFFEL6 (IMXRT_FLEXCAN3_ERXFIFO.offset018) | |||
| #define FLEXCAN3_ERFFEL7 (IMXRT_FLEXCAN3_ERXFIFO.offset01C) | |||
| #define FLEXCAN3_ERFFEL8 (IMXRT_FLEXCAN3_ERXFIFO.offset020) | |||
| #define FLEXCAN3_ERFFEL9 (IMXRT_FLEXCAN3_ERXFIFO.offset024) | |||
| #define FLEXCAN3_ERFFEL10 (IMXRT_FLEXCAN3_ERXFIFO.offset028) | |||
| #define FLEXCAN3_ERFFEL11 (IMXRT_FLEXCAN3_ERXFIFO.offset02C) | |||
| #define FLEXCAN3_ERFFEL12 (IMXRT_FLEXCAN3_ERXFIFO.offset030) | |||
| #define FLEXCAN3_ERFFEL13 (IMXRT_FLEXCAN3_ERXFIFO.offset034) | |||
| #define FLEXCAN3_ERFFEL14 (IMXRT_FLEXCAN3_ERXFIFO.offset038) | |||
| #define FLEXCAN3_ERFFEL15 (IMXRT_FLEXCAN3_ERXFIFO.offset03C) | |||
| #define FLEXCAN3_ERFFEL16 (IMXRT_FLEXCAN3_ERXFIFO.offset040) | |||
| #define FLEXCAN3_ERFFEL17 (IMXRT_FLEXCAN3_ERXFIFO.offset044) | |||
| #define FLEXCAN3_ERFFEL18 (IMXRT_FLEXCAN3_ERXFIFO.offset048) | |||
| #define FLEXCAN3_ERFFEL19 (IMXRT_FLEXCAN3_ERXFIFO.offset04C) | |||
| #define FLEXCAN3_ERFFEL20 (IMXRT_FLEXCAN3_ERXFIFO.offset050) | |||
| #define FLEXCAN3_ERFFEL21 (IMXRT_FLEXCAN3_ERXFIFO.offset054) | |||
| #define FLEXCAN3_ERFFEL22 (IMXRT_FLEXCAN3_ERXFIFO.offset058) | |||
| #define FLEXCAN3_ERFFEL23 (IMXRT_FLEXCAN3_ERXFIFO.offset05C) | |||
| #define FLEXCAN3_ERFFEL24 (IMXRT_FLEXCAN3_ERXFIFO.offset060) | |||
| #define FLEXCAN3_ERFFEL25 (IMXRT_FLEXCAN3_ERXFIFO.offset064) | |||
| #define FLEXCAN3_ERFFEL26 (IMXRT_FLEXCAN3_ERXFIFO.offset068) | |||
| #define FLEXCAN3_ERFFEL27 (IMXRT_FLEXCAN3_ERXFIFO.offset06C) | |||
| #define FLEXCAN3_ERFFEL28 (IMXRT_FLEXCAN3_ERXFIFO.offset070) | |||
| #define FLEXCAN3_ERFFEL29 (IMXRT_FLEXCAN3_ERXFIFO.offset074) | |||
| #define FLEXCAN3_ERFFEL30 (IMXRT_FLEXCAN3_ERXFIFO.offset078) | |||
| #define FLEXCAN3_ERFFEL31 (IMXRT_FLEXCAN3_ERXFIFO.offset07C) | |||
| #define FLEXCAN3_ERFFEL32 (IMXRT_FLEXCAN3_ERXFIFO.offset080) | |||
| #define FLEXCAN3_ERFFEL33 (IMXRT_FLEXCAN3_ERXFIFO.offset084) | |||
| #define FLEXCAN3_ERFFEL34 (IMXRT_FLEXCAN3_ERXFIFO.offset088) | |||
| #define FLEXCAN3_ERFFEL35 (IMXRT_FLEXCAN3_ERXFIFO.offset08C) | |||
| #define FLEXCAN3_ERFFEL36 (IMXRT_FLEXCAN3_ERXFIFO.offset090) | |||
| #define FLEXCAN3_ERFFEL37 (IMXRT_FLEXCAN3_ERXFIFO.offset094) | |||
| #define FLEXCAN3_ERFFEL38 (IMXRT_FLEXCAN3_ERXFIFO.offset098) | |||
| #define FLEXCAN3_ERFFEL39 (IMXRT_FLEXCAN3_ERXFIFO.offset09C) | |||
| #define FLEXCAN3_ERFFEL40 (IMXRT_FLEXCAN3_ERXFIFO.offset0A0) | |||
| #define FLEXCAN3_ERFFEL41 (IMXRT_FLEXCAN3_ERXFIFO.offset0A4) | |||
| #define FLEXCAN3_ERFFEL42 (IMXRT_FLEXCAN3_ERXFIFO.offset0A8) | |||
| #define FLEXCAN3_ERFFEL43 (IMXRT_FLEXCAN3_ERXFIFO.offset0AC) | |||
| #define FLEXCAN3_ERFFEL44 (IMXRT_FLEXCAN3_ERXFIFO.offset0B0) | |||
| #define FLEXCAN3_ERFFEL45 (IMXRT_FLEXCAN3_ERXFIFO.offset0B4) | |||
| #define FLEXCAN3_ERFFEL46 (IMXRT_FLEXCAN3_ERXFIFO.offset0B8) | |||
| #define FLEXCAN3_ERFFEL47 (IMXRT_FLEXCAN3_ERXFIFO.offset0BC) | |||
| #define FLEXCAN3_ERFFEL48 (IMXRT_FLEXCAN3_ERXFIFO.offset0C0) | |||
| #define FLEXCAN3_ERFFEL49 (IMXRT_FLEXCAN3_ERXFIFO.offset0C4) | |||
| #define FLEXCAN3_ERFFEL50 (IMXRT_FLEXCAN3_ERXFIFO.offset0C8) | |||
| #define FLEXCAN3_ERFFEL51 (IMXRT_FLEXCAN3_ERXFIFO.offset0CC) | |||
| #define FLEXCAN3_ERFFEL52 (IMXRT_FLEXCAN3_ERXFIFO.offset0D0) | |||
| #define FLEXCAN3_ERFFEL53 (IMXRT_FLEXCAN3_ERXFIFO.offset0D4) | |||
| #define FLEXCAN3_ERFFEL54 (IMXRT_FLEXCAN3_ERXFIFO.offset0D8) | |||
| #define FLEXCAN3_ERFFEL55 (IMXRT_FLEXCAN3_ERXFIFO.offset0DC) | |||
| #define FLEXCAN3_ERFFEL56 (IMXRT_FLEXCAN3_ERXFIFO.offset0E0) | |||
| #define FLEXCAN3_ERFFEL57 (IMXRT_FLEXCAN3_ERXFIFO.offset0E4) | |||
| #define FLEXCAN3_ERFFEL58 (IMXRT_FLEXCAN3_ERXFIFO.offset0E8) | |||
| #define FLEXCAN3_ERFFEL59 (IMXRT_FLEXCAN3_ERXFIFO.offset0EC) | |||
| #define FLEXCAN3_ERFFEL60 (IMXRT_FLEXCAN3_ERXFIFO.offset0F0) | |||
| #define FLEXCAN3_ERFFEL61 (IMXRT_FLEXCAN3_ERXFIFO.offset0F4) | |||
| #define FLEXCAN3_ERFFEL62 (IMXRT_FLEXCAN3_ERXFIFO.offset0F8) | |||
| #define FLEXCAN3_ERFFEL63 (IMXRT_FLEXCAN3_ERXFIFO.offset0FC) | |||
| #define FLEXCAN3_ERFFEL64 (IMXRT_FLEXCAN3_ERXFIFO.offset100) | |||
| #define FLEXCAN3_ERFFEL65 (IMXRT_FLEXCAN3_ERXFIFO.offset104) | |||
| #define FLEXCAN3_ERFFEL66 (IMXRT_FLEXCAN3_ERXFIFO.offset108) | |||
| #define FLEXCAN3_ERFFEL67 (IMXRT_FLEXCAN3_ERXFIFO.offset10C) | |||
| #define FLEXCAN3_ERFFEL68 (IMXRT_FLEXCAN3_ERXFIFO.offset110) | |||
| #define FLEXCAN3_ERFFEL69 (IMXRT_FLEXCAN3_ERXFIFO.offset114) | |||
| #define FLEXCAN3_ERFFEL70 (IMXRT_FLEXCAN3_ERXFIFO.offset118) | |||
| #define FLEXCAN3_ERFFEL71 (IMXRT_FLEXCAN3_ERXFIFO.offset11C) | |||
| #define FLEXCAN3_ERFFEL72 (IMXRT_FLEXCAN3_ERXFIFO.offset120) | |||
| #define FLEXCAN3_ERFFEL73 (IMXRT_FLEXCAN3_ERXFIFO.offset124) | |||
| #define FLEXCAN3_ERFFEL74 (IMXRT_FLEXCAN3_ERXFIFO.offset128) | |||
| #define FLEXCAN3_ERFFEL75 (IMXRT_FLEXCAN3_ERXFIFO.offset12C) | |||
| #define FLEXCAN3_ERFFEL76 (IMXRT_FLEXCAN3_ERXFIFO.offset130) | |||
| #define FLEXCAN3_ERFFEL77 (IMXRT_FLEXCAN3_ERXFIFO.offset134) | |||
| #define FLEXCAN3_ERFFEL78 (IMXRT_FLEXCAN3_ERXFIFO.offset138) | |||
| #define FLEXCAN3_ERFFEL79 (IMXRT_FLEXCAN3_ERXFIFO.offset13C) | |||
| #define FLEXCAN3_ERFFEL80 (IMXRT_FLEXCAN3_ERXFIFO.offset140) | |||
| #define FLEXCAN3_ERFFEL81 (IMXRT_FLEXCAN3_ERXFIFO.offset144) | |||
| #define FLEXCAN3_ERFFEL82 (IMXRT_FLEXCAN3_ERXFIFO.offset148) | |||
| #define FLEXCAN3_ERFFEL83 (IMXRT_FLEXCAN3_ERXFIFO.offset14C) | |||
| #define FLEXCAN3_ERFFEL84 (IMXRT_FLEXCAN3_ERXFIFO.offset150) | |||
| #define FLEXCAN3_ERFFEL85 (IMXRT_FLEXCAN3_ERXFIFO.offset154) | |||
| #define FLEXCAN3_ERFFEL86 (IMXRT_FLEXCAN3_ERXFIFO.offset158) | |||
| #define FLEXCAN3_ERFFEL87 (IMXRT_FLEXCAN3_ERXFIFO.offset15C) | |||
| #define FLEXCAN3_ERFFEL88 (IMXRT_FLEXCAN3_ERXFIFO.offset160) | |||
| #define FLEXCAN3_ERFFEL89 (IMXRT_FLEXCAN3_ERXFIFO.offset164) | |||
| #define FLEXCAN3_ERFFEL90 (IMXRT_FLEXCAN3_ERXFIFO.offset168) | |||
| #define FLEXCAN3_ERFFEL91 (IMXRT_FLEXCAN3_ERXFIFO.offset16C) | |||
| #define FLEXCAN3_ERFFEL92 (IMXRT_FLEXCAN3_ERXFIFO.offset170) | |||
| #define FLEXCAN3_ERFFEL93 (IMXRT_FLEXCAN3_ERXFIFO.offset174) | |||
| #define FLEXCAN3_ERFFEL94 (IMXRT_FLEXCAN3_ERXFIFO.offset178) | |||
| #define FLEXCAN3_ERFFEL95 (IMXRT_FLEXCAN3_ERXFIFO.offset17C) | |||
| #define FLEXCAN3_ERFFEL96 (IMXRT_FLEXCAN3_ERXFIFO.offset180) | |||
| #define FLEXCAN3_ERFFEL97 (IMXRT_FLEXCAN3_ERXFIFO.offset184) | |||
| #define FLEXCAN3_ERFFEL98 (IMXRT_FLEXCAN3_ERXFIFO.offset188) | |||
| #define FLEXCAN3_ERFFEL99 (IMXRT_FLEXCAN3_ERXFIFO.offset18C) | |||
| #define FLEXCAN3_ERFFEL100 (IMXRT_FLEXCAN3_ERXFIFO.offset190) | |||
| #define FLEXCAN3_ERFFEL101 (IMXRT_FLEXCAN3_ERXFIFO.offset194) | |||
| #define FLEXCAN3_ERFFEL102 (IMXRT_FLEXCAN3_ERXFIFO.offset198) | |||
| #define FLEXCAN3_ERFFEL103 (IMXRT_FLEXCAN3_ERXFIFO.offset19C) | |||
| #define FLEXCAN3_ERFFEL104 (IMXRT_FLEXCAN3_ERXFIFO.offset1A0) | |||
| #define FLEXCAN3_ERFFEL105 (IMXRT_FLEXCAN3_ERXFIFO.offset1A4) | |||
| #define FLEXCAN3_ERFFEL106 (IMXRT_FLEXCAN3_ERXFIFO.offset1A8) | |||
| #define FLEXCAN3_ERFFEL107 (IMXRT_FLEXCAN3_ERXFIFO.offset1AC) | |||
| #define FLEXCAN3_ERFFEL108 (IMXRT_FLEXCAN3_ERXFIFO.offset1B0) | |||
| #define FLEXCAN3_ERFFEL109 (IMXRT_FLEXCAN3_ERXFIFO.offset1B4) | |||
| #define FLEXCAN3_ERFFEL110 (IMXRT_FLEXCAN3_ERXFIFO.offset1B8) | |||
| #define FLEXCAN3_ERFFEL111 (IMXRT_FLEXCAN3_ERXFIFO.offset1BC) | |||
| #define FLEXCAN3_ERFFEL112 (IMXRT_FLEXCAN3_ERXFIFO.offset1C0) | |||
| #define FLEXCAN3_ERFFEL113 (IMXRT_FLEXCAN3_ERXFIFO.offset1C4) | |||
| #define FLEXCAN3_ERFFEL114 (IMXRT_FLEXCAN3_ERXFIFO.offset1C8) | |||
| #define FLEXCAN3_ERFFEL115 (IMXRT_FLEXCAN3_ERXFIFO.offset1CC) | |||
| #define FLEXCAN3_ERFFEL116 (IMXRT_FLEXCAN3_ERXFIFO.offset1D0) | |||
| #define FLEXCAN3_ERFFEL117 (IMXRT_FLEXCAN3_ERXFIFO.offset1D4) | |||
| #define FLEXCAN3_ERFFEL118 (IMXRT_FLEXCAN3_ERXFIFO.offset1D8) | |||
| #define FLEXCAN3_ERFFEL119 (IMXRT_FLEXCAN3_ERXFIFO.offset1DC) | |||
| #define FLEXCAN3_ERFFEL120 (IMXRT_FLEXCAN3_ERXFIFO.offset1E0) | |||
| #define FLEXCAN3_ERFFEL121 (IMXRT_FLEXCAN3_ERXFIFO.offset1E4) | |||
| #define FLEXCAN3_ERFFEL122 (IMXRT_FLEXCAN3_ERXFIFO.offset1E8) | |||
| #define FLEXCAN3_ERFFEL123 (IMXRT_FLEXCAN3_ERXFIFO.offset1EC) | |||
| #define FLEXCAN3_ERFFEL124 (IMXRT_FLEXCAN3_ERXFIFO.offset1F0) | |||
| #define FLEXCAN3_ERFFEL125 (IMXRT_FLEXCAN3_ERXFIFO.offset1F4) | |||
| #define FLEXCAN3_ERFFEL126 (IMXRT_FLEXCAN3_ERXFIFO.offset1F8) | |||
| #define FLEXCAN3_ERFFEL127 (IMXRT_FLEXCAN3_ERXFIFO.offset1FC) | |||
| // 27.3.1.1: page 1292 | |||
| typedef struct { | |||
| const uint32_t VERID; // 0x00 (IMXRT_FLEXIO1.offset000) | |||
| @@ -2835,6 +3239,7 @@ typedef struct { | |||
| #define IMXRT_FLEXIO1_S (*(IMXRT_FLEXIO_t *)0x401AC000) | |||
| #define IMXRT_FLEXIO2_S (*(IMXRT_FLEXIO_t *)0x401B0000) | |||
| #define IMXRT_FLEXIO3_S (*(IMXRT_FLEXIO_t *)0x42020000) | |||
| #define IMXRT_FLEXIO1 (*(IMXRT_REGISTER32_t *)0x401AC000) | |||
| #define IMXRT_FLEXIO1_b (*(IMXRT_REGISTER32_t *)0x401AC400) | |||
| @@ -4351,6 +4756,174 @@ typedef struct { | |||
| #define FLEXSPI_LUT_NUM_PADS_4 0x02 | |||
| #define FLEXSPI_LUT_NUM_PADS_8 0x03 | |||
| #define IMXRT_FLEXSPI2 (*(IMXRT_REGISTER32_t *)0x402A4000) | |||
| #define FLEXSPI2_MCR0 (IMXRT_FLEXSPI2.offset000) | |||
| #define FLEXSPI2_MCR1 (IMXRT_FLEXSPI2.offset004) | |||
| #define FLEXSPI2_MCR2 (IMXRT_FLEXSPI2.offset008) | |||
| #define FLEXSPI2_AHBCR (IMXRT_FLEXSPI2.offset00C) | |||
| #define FLEXSPI2_INTEN (IMXRT_FLEXSPI2.offset010) | |||
| #define FLEXSPI2_INTR (IMXRT_FLEXSPI2.offset014) | |||
| #define FLEXSPI2_LUTKEY (IMXRT_FLEXSPI2.offset018) | |||
| #define FLEXSPI2_LUTCR (IMXRT_FLEXSPI2.offset01C) | |||
| #define FLEXSPI2_AHBRXBUF0CR0 (IMXRT_FLEXSPI2.offset020) | |||
| #define FLEXSPI2_AHBRXBUF1CR0 (IMXRT_FLEXSPI2.offset024) | |||
| #define FLEXSPI2_AHBRXBUF2CR0 (IMXRT_FLEXSPI2.offset028) | |||
| #define FLEXSPI2_AHBRXBUF3CR0 (IMXRT_FLEXSPI2.offset02C) | |||
| #define FLEXSPI2_FLSHA1CR0 (IMXRT_FLEXSPI2.offset060) | |||
| #define FLEXSPI2_FLSHA2CR0 (IMXRT_FLEXSPI2.offset064) | |||
| #define FLEXSPI2_FLSHB1CR0 (IMXRT_FLEXSPI2.offset068) | |||
| #define FLEXSPI2_FLSHB2CR0 (IMXRT_FLEXSPI2.offset06C) | |||
| #define FLEXSPI2_FLSHA1CR1 (IMXRT_FLEXSPI2.offset070) | |||
| #define FLEXSPI2_FLSHA2CR1 (IMXRT_FLEXSPI2.offset074) | |||
| #define FLEXSPI2_FLSHB1CR1 (IMXRT_FLEXSPI2.offset078) | |||
| #define FLEXSPI2_FLSHB2CR1 (IMXRT_FLEXSPI2.offset07C) | |||
| #define FLEXSPI2_FLSHA1CR2 (IMXRT_FLEXSPI2.offset080) | |||
| #define FLEXSPI2_FLSHA2CR2 (IMXRT_FLEXSPI2.offset084) | |||
| #define FLEXSPI2_FLSHB1CR2 (IMXRT_FLEXSPI2.offset088) | |||
| #define FLEXSPI2_FLSHB2CR2 (IMXRT_FLEXSPI2.offset08C) | |||
| #define FLEXSPI2_FLSHCR4 (IMXRT_FLEXSPI2.offset094) | |||
| #define FLEXSPI2_IPCR0 (IMXRT_FLEXSPI2.offset0A0) | |||
| #define FLEXSPI2_IPCR1 (IMXRT_FLEXSPI2.offset0A4) | |||
| #define FLEXSPI2_IPCMD (IMXRT_FLEXSPI2.offset0B0) | |||
| #define FLEXSPI2_IPRXFCR (IMXRT_FLEXSPI2.offset0B8) | |||
| #define FLEXSPI2_IPTXFCR (IMXRT_FLEXSPI2.offset0BC) | |||
| #define FLEXSPI2_DLLACR (IMXRT_FLEXSPI2.offset0C0) | |||
| #define FLEXSPI2_DLLBCR (IMXRT_FLEXSPI2.offset0C4) | |||
| #define FLEXSPI2_STS0 (IMXRT_FLEXSPI2.offset0E0) | |||
| #define FLEXSPI2_STS1 (IMXRT_FLEXSPI2.offset0E4) | |||
| #define FLEXSPI2_STS2 (IMXRT_FLEXSPI2.offset0E8) | |||
| #define FLEXSPI2_AHBSPNDSTS (IMXRT_FLEXSPI2.offset0EC) | |||
| #define FLEXSPI2_IPRXFSTS (IMXRT_FLEXSPI2.offset0F0) | |||
| #define FLEXSPI2_IPTXFSTS (IMXRT_FLEXSPI2.offset0F4) | |||
| #define FLEXSPI2_RFDR0 (IMXRT_FLEXSPI2.offset100) | |||
| #define FLEXSPI2_RFDR1 (IMXRT_FLEXSPI2.offset104) | |||
| #define FLEXSPI2_RFDR2 (IMXRT_FLEXSPI2.offset108) | |||
| #define FLEXSPI2_RFDR3 (IMXRT_FLEXSPI2.offset10C) | |||
| #define FLEXSPI2_RFDR4 (IMXRT_FLEXSPI2.offset110) | |||
| #define FLEXSPI2_RFDR5 (IMXRT_FLEXSPI2.offset114) | |||
| #define FLEXSPI2_RFDR6 (IMXRT_FLEXSPI2.offset118) | |||
| #define FLEXSPI2_RFDR7 (IMXRT_FLEXSPI2.offset11C) | |||
| #define FLEXSPI2_RFDR8 (IMXRT_FLEXSPI2.offset120) | |||
| #define FLEXSPI2_RFDR9 (IMXRT_FLEXSPI2.offset124) | |||
| #define FLEXSPI2_RFDR10 (IMXRT_FLEXSPI2.offset128) | |||
| #define FLEXSPI2_RFDR11 (IMXRT_FLEXSPI2.offset12C) | |||
| #define FLEXSPI2_RFDR12 (IMXRT_FLEXSPI2.offset130) | |||
| #define FLEXSPI2_RFDR13 (IMXRT_FLEXSPI2.offset134) | |||
| #define FLEXSPI2_RFDR14 (IMXRT_FLEXSPI2.offset138) | |||
| #define FLEXSPI2_RFDR15 (IMXRT_FLEXSPI2.offset13C) | |||
| #define FLEXSPI2_RFDR16 (IMXRT_FLEXSPI2.offset140) | |||
| #define FLEXSPI2_RFDR17 (IMXRT_FLEXSPI2.offset144) | |||
| #define FLEXSPI2_RFDR18 (IMXRT_FLEXSPI2.offset148) | |||
| #define FLEXSPI2_RFDR19 (IMXRT_FLEXSPI2.offset14C) | |||
| #define FLEXSPI2_RFDR20 (IMXRT_FLEXSPI2.offset150) | |||
| #define FLEXSPI2_RFDR21 (IMXRT_FLEXSPI2.offset154) | |||
| #define FLEXSPI2_RFDR22 (IMXRT_FLEXSPI2.offset158) | |||
| #define FLEXSPI2_RFDR23 (IMXRT_FLEXSPI2.offset15C) | |||
| #define FLEXSPI2_RFDR24 (IMXRT_FLEXSPI2.offset160) | |||
| #define FLEXSPI2_RFDR25 (IMXRT_FLEXSPI2.offset164) | |||
| #define FLEXSPI2_RFDR26 (IMXRT_FLEXSPI2.offset168) | |||
| #define FLEXSPI2_RFDR27 (IMXRT_FLEXSPI2.offset16C) | |||
| #define FLEXSPI2_RFDR28 (IMXRT_FLEXSPI2.offset170) | |||
| #define FLEXSPI2_RFDR29 (IMXRT_FLEXSPI2.offset174) | |||
| #define FLEXSPI2_RFDR30 (IMXRT_FLEXSPI2.offset178) | |||
| #define FLEXSPI2_RFDR31 (IMXRT_FLEXSPI2.offset17C) | |||
| #define FLEXSPI2_TFDR0 (IMXRT_FLEXSPI2.offset180) | |||
| #define FLEXSPI2_TFDR1 (IMXRT_FLEXSPI2.offset184) | |||
| #define FLEXSPI2_TFDR2 (IMXRT_FLEXSPI2.offset188) | |||
| #define FLEXSPI2_TFDR3 (IMXRT_FLEXSPI2.offset18C) | |||
| #define FLEXSPI2_TFDR4 (IMXRT_FLEXSPI2.offset190) | |||
| #define FLEXSPI2_TFDR5 (IMXRT_FLEXSPI2.offset194) | |||
| #define FLEXSPI2_TFDR6 (IMXRT_FLEXSPI2.offset198) | |||
| #define FLEXSPI2_TFDR7 (IMXRT_FLEXSPI2.offset19C) | |||
| #define FLEXSPI2_TFDR8 (IMXRT_FLEXSPI2.offset1A0) | |||
| #define FLEXSPI2_TFDR9 (IMXRT_FLEXSPI2.offset1A4) | |||
| #define FLEXSPI2_TFDR10 (IMXRT_FLEXSPI2.offset1A8) | |||
| #define FLEXSPI2_TFDR11 (IMXRT_FLEXSPI2.offset1AC) | |||
| #define FLEXSPI2_TFDR12 (IMXRT_FLEXSPI2.offset1B0) | |||
| #define FLEXSPI2_TFDR13 (IMXRT_FLEXSPI2.offset1B4) | |||
| #define FLEXSPI2_TFDR14 (IMXRT_FLEXSPI2.offset1B8) | |||
| #define FLEXSPI2_TFDR15 (IMXRT_FLEXSPI2.offset1BC) | |||
| #define FLEXSPI2_TFDR16 (IMXRT_FLEXSPI2.offset1C0) | |||
| #define FLEXSPI2_TFDR17 (IMXRT_FLEXSPI2.offset1C4) | |||
| #define FLEXSPI2_TFDR18 (IMXRT_FLEXSPI2.offset1C8) | |||
| #define FLEXSPI2_TFDR19 (IMXRT_FLEXSPI2.offset1CC) | |||
| #define FLEXSPI2_TFDR20 (IMXRT_FLEXSPI2.offset1D0) | |||
| #define FLEXSPI2_TFDR21 (IMXRT_FLEXSPI2.offset1D4) | |||
| #define FLEXSPI2_TFDR22 (IMXRT_FLEXSPI2.offset1D8) | |||
| #define FLEXSPI2_TFDR23 (IMXRT_FLEXSPI2.offset1DC) | |||
| #define FLEXSPI2_TFDR24 (IMXRT_FLEXSPI2.offset1E0) | |||
| #define FLEXSPI2_TFDR25 (IMXRT_FLEXSPI2.offset1E4) | |||
| #define FLEXSPI2_TFDR26 (IMXRT_FLEXSPI2.offset1E8) | |||
| #define FLEXSPI2_TFDR27 (IMXRT_FLEXSPI2.offset1EC) | |||
| #define FLEXSPI2_TFDR28 (IMXRT_FLEXSPI2.offset1F0) | |||
| #define FLEXSPI2_TFDR29 (IMXRT_FLEXSPI2.offset1F4) | |||
| #define FLEXSPI2_TFDR30 (IMXRT_FLEXSPI2.offset1F8) | |||
| #define FLEXSPI2_TFDR31 (IMXRT_FLEXSPI2.offset1FC) | |||
| #define FLEXSPI2_LUT0 (IMXRT_FLEXSPI2.offset200) | |||
| #define FLEXSPI2_LUT1 (IMXRT_FLEXSPI2.offset204) | |||
| #define FLEXSPI2_LUT2 (IMXRT_FLEXSPI2.offset208) | |||
| #define FLEXSPI2_LUT3 (IMXRT_FLEXSPI2.offset20C) | |||
| #define FLEXSPI2_LUT4 (IMXRT_FLEXSPI2.offset210) | |||
| #define FLEXSPI2_LUT5 (IMXRT_FLEXSPI2.offset214) | |||
| #define FLEXSPI2_LUT6 (IMXRT_FLEXSPI2.offset218) | |||
| #define FLEXSPI2_LUT7 (IMXRT_FLEXSPI2.offset21C) | |||
| #define FLEXSPI2_LUT8 (IMXRT_FLEXSPI2.offset220) | |||
| #define FLEXSPI2_LUT9 (IMXRT_FLEXSPI2.offset224) | |||
| #define FLEXSPI2_LUT10 (IMXRT_FLEXSPI2.offset228) | |||
| #define FLEXSPI2_LUT11 (IMXRT_FLEXSPI2.offset22C) | |||
| #define FLEXSPI2_LUT12 (IMXRT_FLEXSPI2.offset230) | |||
| #define FLEXSPI2_LUT13 (IMXRT_FLEXSPI2.offset234) | |||
| #define FLEXSPI2_LUT14 (IMXRT_FLEXSPI2.offset238) | |||
| #define FLEXSPI2_LUT15 (IMXRT_FLEXSPI2.offset23C) | |||
| #define FLEXSPI2_LUT16 (IMXRT_FLEXSPI2.offset240) | |||
| #define FLEXSPI2_LUT17 (IMXRT_FLEXSPI2.offset244) | |||
| #define FLEXSPI2_LUT18 (IMXRT_FLEXSPI2.offset248) | |||
| #define FLEXSPI2_LUT19 (IMXRT_FLEXSPI2.offset24C) | |||
| #define FLEXSPI2_LUT20 (IMXRT_FLEXSPI2.offset250) | |||
| #define FLEXSPI2_LUT21 (IMXRT_FLEXSPI2.offset254) | |||
| #define FLEXSPI2_LUT22 (IMXRT_FLEXSPI2.offset258) | |||
| #define FLEXSPI2_LUT23 (IMXRT_FLEXSPI2.offset25C) | |||
| #define FLEXSPI2_LUT24 (IMXRT_FLEXSPI2.offset260) | |||
| #define FLEXSPI2_LUT25 (IMXRT_FLEXSPI2.offset264) | |||
| #define FLEXSPI2_LUT26 (IMXRT_FLEXSPI2.offset268) | |||
| #define FLEXSPI2_LUT27 (IMXRT_FLEXSPI2.offset26C) | |||
| #define FLEXSPI2_LUT28 (IMXRT_FLEXSPI2.offset270) | |||
| #define FLEXSPI2_LUT29 (IMXRT_FLEXSPI2.offset274) | |||
| #define FLEXSPI2_LUT30 (IMXRT_FLEXSPI2.offset278) | |||
| #define FLEXSPI2_LUT31 (IMXRT_FLEXSPI2.offset27C) | |||
| #define FLEXSPI2_LUT32 (IMXRT_FLEXSPI2.offset280) | |||
| #define FLEXSPI2_LUT33 (IMXRT_FLEXSPI2.offset284) | |||
| #define FLEXSPI2_LUT34 (IMXRT_FLEXSPI2.offset288) | |||
| #define FLEXSPI2_LUT35 (IMXRT_FLEXSPI2.offset28C) | |||
| #define FLEXSPI2_LUT36 (IMXRT_FLEXSPI2.offset290) | |||
| #define FLEXSPI2_LUT37 (IMXRT_FLEXSPI2.offset294) | |||
| #define FLEXSPI2_LUT38 (IMXRT_FLEXSPI2.offset298) | |||
| #define FLEXSPI2_LUT39 (IMXRT_FLEXSPI2.offset29C) | |||
| #define FLEXSPI2_LUT40 (IMXRT_FLEXSPI2.offset2A0) | |||
| #define FLEXSPI2_LUT41 (IMXRT_FLEXSPI2.offset2A4) | |||
| #define FLEXSPI2_LUT42 (IMXRT_FLEXSPI2.offset2A8) | |||
| #define FLEXSPI2_LUT43 (IMXRT_FLEXSPI2.offset2AC) | |||
| #define FLEXSPI2_LUT44 (IMXRT_FLEXSPI2.offset2B0) | |||
| #define FLEXSPI2_LUT45 (IMXRT_FLEXSPI2.offset2B4) | |||
| #define FLEXSPI2_LUT46 (IMXRT_FLEXSPI2.offset2B8) | |||
| #define FLEXSPI2_LUT47 (IMXRT_FLEXSPI2.offset2BC) | |||
| #define FLEXSPI2_LUT48 (IMXRT_FLEXSPI2.offset2C0) | |||
| #define FLEXSPI2_LUT49 (IMXRT_FLEXSPI2.offset2C4) | |||
| #define FLEXSPI2_LUT50 (IMXRT_FLEXSPI2.offset2C8) | |||
| #define FLEXSPI2_LUT51 (IMXRT_FLEXSPI2.offset2CC) | |||
| #define FLEXSPI2_LUT52 (IMXRT_FLEXSPI2.offset2D0) | |||
| #define FLEXSPI2_LUT53 (IMXRT_FLEXSPI2.offset2D4) | |||
| #define FLEXSPI2_LUT54 (IMXRT_FLEXSPI2.offset2D8) | |||
| #define FLEXSPI2_LUT55 (IMXRT_FLEXSPI2.offset2DC) | |||
| #define FLEXSPI2_LUT56 (IMXRT_FLEXSPI2.offset2E0) | |||
| #define FLEXSPI2_LUT57 (IMXRT_FLEXSPI2.offset2E4) | |||
| #define FLEXSPI2_LUT58 (IMXRT_FLEXSPI2.offset2E8) | |||
| #define FLEXSPI2_LUT59 (IMXRT_FLEXSPI2.offset2EC) | |||
| #define FLEXSPI2_LUT60 (IMXRT_FLEXSPI2.offset2F0) | |||
| #define FLEXSPI2_LUT61 (IMXRT_FLEXSPI2.offset2F4) | |||
| #define FLEXSPI2_LUT62 (IMXRT_FLEXSPI2.offset2F8) | |||
| #define FLEXSPI2_LUT63 (IMXRT_FLEXSPI2.offset2FC) | |||
| // 31.5: page 1595 | |||
| #define IMXRT_GPC (*(IMXRT_REGISTER32_t *)0x400F4000) | |||
| #define GPC_CNTR (IMXRT_GPC.offset000) | |||
| @@ -4450,6 +5023,54 @@ typedef struct { | |||
| #define GPIO5_DR_SET (IMXRT_GPIO5.offset084) | |||
| #define GPIO5_DR_CLEAR (IMXRT_GPIO5.offset088) | |||
| #define GPIO5_DR_TOGGLE (IMXRT_GPIO5.offset08C) | |||
| #define IMXRT_GPIO6 (*(IMXRT_REGISTER32_t *)0x42000000) | |||
| #define GPIO6_DR (IMXRT_GPIO6.offset000) | |||
| #define GPIO6_GDIR (IMXRT_GPIO6.offset004) | |||
| #define GPIO6_PSR (IMXRT_GPIO6.offset008) | |||
| #define GPIO6_ICR1 (IMXRT_GPIO6.offset00C) | |||
| #define GPIO6_ICR2 (IMXRT_GPIO6.offset010) | |||
| #define GPIO6_IMR (IMXRT_GPIO6.offset014) | |||
| #define GPIO6_ISR (IMXRT_GPIO6.offset018) | |||
| #define GPIO6_EDGE_SEL (IMXRT_GPIO6.offset01C) | |||
| #define GPIO6_DR_SET (IMXRT_GPIO6.offset084) | |||
| #define GPIO6_DR_CLEAR (IMXRT_GPIO6.offset088) | |||
| #define GPIO6_DR_TOGGLE (IMXRT_GPIO6.offset08C) | |||
| #define IMXRT_GPIO7 (*(IMXRT_REGISTER32_t *)0x42004000) | |||
| #define GPIO7_DR (IMXRT_GPIO7.offset000) | |||
| #define GPIO7_GDIR (IMXRT_GPIO7.offset004) | |||
| #define GPIO7_PSR (IMXRT_GPIO7.offset008) | |||
| #define GPIO7_ICR1 (IMXRT_GPIO7.offset00C) | |||
| #define GPIO7_ICR2 (IMXRT_GPIO7.offset010) | |||
| #define GPIO7_IMR (IMXRT_GPIO7.offset014) | |||
| #define GPIO7_ISR (IMXRT_GPIO7.offset018) | |||
| #define GPIO7_EDGE_SEL (IMXRT_GPIO7.offset01C) | |||
| #define GPIO7_DR_SET (IMXRT_GPIO7.offset084) | |||
| #define GPIO7_DR_CLEAR (IMXRT_GPIO7.offset088) | |||
| #define GPIO7_DR_TOGGLE (IMXRT_GPIO7.offset08C) | |||
| #define IMXRT_GPIO8 (*(IMXRT_REGISTER32_t *)0x42008000) | |||
| #define GPIO8_DR (IMXRT_GPIO8.offset000) | |||
| #define GPIO8_GDIR (IMXRT_GPIO8.offset004) | |||
| #define GPIO8_PSR (IMXRT_GPIO8.offset008) | |||
| #define GPIO8_ICR1 (IMXRT_GPIO8.offset00C) | |||
| #define GPIO8_ICR2 (IMXRT_GPIO8.offset010) | |||
| #define GPIO8_IMR (IMXRT_GPIO8.offset014) | |||
| #define GPIO8_ISR (IMXRT_GPIO8.offset018) | |||
| #define GPIO8_EDGE_SEL (IMXRT_GPIO8.offset01C) | |||
| #define GPIO8_DR_SET (IMXRT_GPIO8.offset084) | |||
| #define GPIO8_DR_CLEAR (IMXRT_GPIO8.offset088) | |||
| #define GPIO8_DR_TOGGLE (IMXRT_GPIO8.offset08C) | |||
| #define IMXRT_GPIO9 (*(IMXRT_REGISTER32_t *)0x4200C000) | |||
| #define GPIO9_DR (IMXRT_GPIO9.offset000) | |||
| #define GPIO9_GDIR (IMXRT_GPIO9.offset004) | |||
| #define GPIO9_PSR (IMXRT_GPIO9.offset008) | |||
| #define GPIO9_ICR1 (IMXRT_GPIO9.offset00C) | |||
| #define GPIO9_ICR2 (IMXRT_GPIO9.offset010) | |||
| #define GPIO9_IMR (IMXRT_GPIO9.offset014) | |||
| #define GPIO9_ISR (IMXRT_GPIO9.offset018) | |||
| #define GPIO9_EDGE_SEL (IMXRT_GPIO9.offset01C) | |||
| #define GPIO9_DR_SET (IMXRT_GPIO9.offset084) | |||
| #define GPIO9_DR_CLEAR (IMXRT_GPIO9.offset088) | |||
| #define GPIO9_DR_TOGGLE (IMXRT_GPIO9.offset08C) | |||
| // 33.6: page 1651 | |||
| #define IMXRT_GPT1 (*(IMXRT_REGISTER32_t *)0x401EC000) | |||
| @@ -4535,14 +5156,25 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR23 (IMXRT_IOMUXC_GPR.offset05C) | |||
| #define IOMUXC_GPR_GPR24 (IMXRT_IOMUXC_GPR.offset060) | |||
| #define IOMUXC_GPR_GPR25 (IMXRT_IOMUXC_GPR.offset064) | |||
| #define IOMUXC_GPR_GPR26 (IMXRT_IOMUXC_GPR.offset068) | |||
| #define IOMUXC_GPR_GPR27 (IMXRT_IOMUXC_GPR.offset06C) | |||
| #define IOMUXC_GPR_GPR28 (IMXRT_IOMUXC_GPR.offset070) | |||
| #define IOMUXC_GPR_GPR29 (IMXRT_IOMUXC_GPR.offset074) | |||
| #define IOMUXC_GPR_GPR30 (IMXRT_IOMUXC_GPR.offset078) | |||
| #define IOMUXC_GPR_GPR31 (IMXRT_IOMUXC_GPR.offset07C) | |||
| #define IOMUXC_GPR_GPR32 (IMXRT_IOMUXC_GPR.offset080) | |||
| #define IOMUXC_GPR_GPR33 (IMXRT_IOMUXC_GPR.offset084) | |||
| #define IOMUXC_GPR_GPR34 (IMXRT_IOMUXC_GPR.offset088) | |||
| #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN ((uint32_t)(1<<31)) | |||
| #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN ((uint32_t)(1<<23)) | |||
| #define IOMUXC_GPR_GPR1_EXC_MON ((uint32_t)(1<<22)) | |||
| #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR ((uint32_t)(1<<21)) | |||
| #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR ((uint32_t)(1<<20)) | |||
| #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR ((uint32_t)(1<<19)) | |||
| #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR ((uint32_t)(1<<18)) | |||
| #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR ((uint32_t)(1<<17)) | |||
| #define IOMUXC_GPR_GPR1_USB_EXP_MODE ((uint32_t)(1<<15)) | |||
| #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL ((uint32_t)(1<<14)) | |||
| #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL ((uint32_t)(1<<13)) | |||
| #define IOMUXC_GPR_GPR1_GINT ((uint32_t)(1<<12)) | |||
| #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(n) ((uint32_t)(((n) & 0x03) << 10)) | |||
| @@ -4564,11 +5196,25 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR2_MQS_SW_RST ((uint32_t)(1<<24)) | |||
| #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(n) ((uint32_t)(((n) & 0xFF) << 16)) | |||
| #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP ((uint32_t)(1<<14)) | |||
| #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN ((uint32_t)(1<<13)) | |||
| #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING ((uint32_t)(1<<12)) | |||
| #define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS ((uint32_t)(1<<6)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN ((uint32_t)(1<<5)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY ((uint32_t)(1<<4)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY ((uint32_t)(1<<3)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN ((uint32_t)(1<<2)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY ((uint32_t)(1<<1)) | |||
| #define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK IOMUXC_GPR_GPR2_MQS_CLK_DIV(255) | |||
| #define IOMUXC_GPR_GPR3_AXBS_L_HALTED ((uint32_t)(1<<31)) | |||
| #define IOMUXC_GPR_GPR3_OCRAM2_STATUS(n) ((uint32_t)(((n) & 0x0F) << 24)) | |||
| #define IOMUXC_GPR_GPR3_OCRAM_STATUS(n) ((uint32_t)(((n) & 0x0F) << 16)) | |||
| #define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ ((uint32_t)(1<<15)) | |||
| #define IOMUXC_GPR_GPR3_OCRAM2_CTL(n) ((uint32_t)(((n) & 0x0F) << 8)) | |||
| #define IOMUXC_GPR_GPR3_DCP_KEY_SEL ((uint32_t)(1<<4)) | |||
| #define IOMUXC_GPR_GPR3_OCRAM_CTL(n) ((uint32_t)(((n) & 0x0F) << 0)) | |||
| #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK ((uint32_t)(1<<31)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK ((uint32_t)(1<<30)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK ((uint32_t)(1<<29)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK ((uint32_t)(1<<28)) | |||
| #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK ((uint32_t)(1<<27)) | |||
| @@ -4582,6 +5228,8 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK ((uint32_t)(1<<18)) | |||
| #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK ((uint32_t)(1<<17)) | |||
| #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK ((uint32_t)(1<<16)) | |||
| #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ ((uint32_t)(1<<15)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ ((uint32_t)(1<<14)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ ((uint32_t)(1<<13)) | |||
| #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ ((uint32_t)(1<<12)) | |||
| #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ ((uint32_t)(1<<11)) | |||
| @@ -4597,6 +5245,7 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 ((uint32_t)(1<<29)) | |||
| #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 ((uint32_t)(1<<28)) | |||
| #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL ((uint32_t)(1<<26)) | |||
| #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL ((uint32_t)(1<<25)) | |||
| #define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL ((uint32_t)(1<<24)) | |||
| #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL ((uint32_t)(1<<23)) | |||
| @@ -4720,13 +5369,17 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(n) ((uint32_t)(((n) & 0x03) << 4)) | |||
| #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(n) ((uint32_t)(((n) & 0x03) << 2)) | |||
| #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(n) ((uint32_t)(((n) & 0x03) << 0)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE ((uint32_t)(1<<6)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE ((uint32_t)(1<<5)) | |||
| #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE ((uint32_t)(1<<4)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE ((uint32_t)(1<<3)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE ((uint32_t)(1<<2)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE ((uint32_t)(1<<1)) | |||
| #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR13_CANFD_STOP_ACK ((uint32_t)(1<<20)) | |||
| #define IOMUXC_GPR_GPR13_CACHE_USB ((uint32_t)(1<<13)) | |||
| #define IOMUXC_GPR_GPR13_CACHE_ENET ((uint32_t)(1<<7)) | |||
| #define IOMUXC_GPR_GPR13_CANFD_STOP_REQ ((uint32_t)(1<<4)) | |||
| #define IOMUXC_GPR_GPR13_AWCACHE_USDHC ((uint32_t)(1<<1)) | |||
| #define IOMUXC_GPR_GPR13_ARCACHE_USDHC ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(n) ((uint32_t)(((n) & 0x0F) << 20)) | |||
| @@ -4763,6 +5416,12 @@ typedef struct { | |||
| #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3)) | |||
| #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 17)) | |||
| #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN ((uint32_t)(1<<16)) | |||
| #define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 1)) | |||
| #define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN ((uint32_t)(1<<0)) | |||
| #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN ((uint32_t)(1<<8)) | |||
| #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n) ((uint32_t)(((n) & 0xFF) << 0)) | |||
| // 34.5: page 1717 | |||
| #define IMXRT_IOMUXC_SNVS (*(IMXRT_REGISTER32_t *)0x400A8000) | |||
| @@ -6027,6 +6686,14 @@ typedef struct { | |||
| #define HW_OCOTP_ANA0 (IMXRT_OCOTP_VALUE.offset0D0) | |||
| #define HW_OCOTP_ANA1 (IMXRT_OCOTP_VALUE.offset0E0) | |||
| #define HW_OCOTP_ANA2 (IMXRT_OCOTP_VALUE.offset0F0) | |||
| #define HW_OCOTP_OTPMK0 (IMXRT_OCOTP_VALUE.offset100) | |||
| #define HW_OCOTP_OTPMK1 (IMXRT_OCOTP_VALUE.offset110) | |||
| #define HW_OCOTP_OTPMK2 (IMXRT_OCOTP_VALUE.offset120) | |||
| #define HW_OCOTP_OTPMK3 (IMXRT_OCOTP_VALUE.offset130) | |||
| #define HW_OCOTP_OTPMK4 (IMXRT_OCOTP_VALUE.offset140) | |||
| #define HW_OCOTP_OTPMK5 (IMXRT_OCOTP_VALUE.offset150) | |||
| #define HW_OCOTP_OTPMK6 (IMXRT_OCOTP_VALUE.offset160) | |||
| #define HW_OCOTP_OTPMK7 (IMXRT_OCOTP_VALUE.offset170) | |||
| #define HW_OCOTP_SRK0 (IMXRT_OCOTP_VALUE.offset180) | |||
| #define HW_OCOTP_SRK1 (IMXRT_OCOTP_VALUE.offset190) | |||
| #define HW_OCOTP_SRK2 (IMXRT_OCOTP_VALUE.offset1A0) | |||
| @@ -6040,7 +6707,8 @@ typedef struct { | |||
| #define HW_OCOTP_MAC0 (IMXRT_OCOTP_VALUE.offset220) | |||
| #define HW_OCOTP_MAC1 (IMXRT_OCOTP_VALUE.offset230) | |||
| #define HW_OCOTP_MAC2 (IMXRT_OCOTP_VALUE.offset240) | |||
| #define HW_OCOTP_GP3 (IMXRT_OCOTP_VALUE.offset250) | |||
| #define HW_OCOTP_GP3 (IMXRT_OCOTP_VALUE.offset250) /* IMXRT1052 */ | |||
| #define HW_OCOTP_OTPMK_CRC32 (IMXRT_OCOTP_VALUE.offset250) /* IMXRT1062 */ | |||
| #define HW_OCOTP_GP1 (IMXRT_OCOTP_VALUE.offset260) | |||
| #define HW_OCOTP_GP2 (IMXRT_OCOTP_VALUE.offset270) | |||
| #define HW_OCOTP_SW_GP1 (IMXRT_OCOTP_VALUE.offset280) | |||
| @@ -6051,6 +6719,25 @@ typedef struct { | |||
| #define HW_OCOTP_MISC_CONF0 (IMXRT_OCOTP_VALUE.offset2D0) | |||
| #define HW_OCOTP_MISC_CONF1 (IMXRT_OCOTP_VALUE.offset2E0) | |||
| #define HW_OCOTP_SRK_REVOKE (IMXRT_OCOTP_VALUE.offset2F0) | |||
| #if defined(__IMXRT1062__) | |||
| #define IMXRT_OCOTP_VALUE2 (*(IMXRT_REGISTER32_t *)0x401F4800) | |||
| #define HW_OCOTP_ROM_PATCH0 (IMXRT_OCOTP_VALUE2.offset000) | |||
| #define HW_OCOTP_ROM_PATCH1 (IMXRT_OCOTP_VALUE2.offset010) | |||
| #define HW_OCOTP_ROM_PATCH2 (IMXRT_OCOTP_VALUE2.offset020) | |||
| #define HW_OCOTP_ROM_PATCH3 (IMXRT_OCOTP_VALUE2.offset030) | |||
| #define HW_OCOTP_ROM_PATCH4 (IMXRT_OCOTP_VALUE2.offset040) | |||
| #define HW_OCOTP_ROM_PATCH5 (IMXRT_OCOTP_VALUE2.offset050) | |||
| #define HW_OCOTP_ROM_PATCH6 (IMXRT_OCOTP_VALUE2.offset060) | |||
| #define HW_OCOTP_ROM_PATCH7 (IMXRT_OCOTP_VALUE2.offset070) | |||
| #define HW_OCOTP_GP30 (IMXRT_OCOTP_VALUE2.offset080) | |||
| #define HW_OCOTP_GP31 (IMXRT_OCOTP_VALUE2.offset090) | |||
| #define HW_OCOTP_GP32 (IMXRT_OCOTP_VALUE2.offset0A0) | |||
| #define HW_OCOTP_GP33 (IMXRT_OCOTP_VALUE2.offset0B0) | |||
| #define HW_OCOTP_GP40 (IMXRT_OCOTP_VALUE2.offset0C0) | |||
| #define HW_OCOTP_GP41 (IMXRT_OCOTP_VALUE2.offset0D0) | |||
| #define HW_OCOTP_GP42 (IMXRT_OCOTP_VALUE2.offset0E0) | |||
| #define HW_OCOTP_GP43 (IMXRT_OCOTP_VALUE2.offset0F0) | |||
| #endif | |||
| // 44.8.1: page 2583 | |||
| #define IMXRT_PIT (*(IMXRT_REGISTER32_t *)0x40084000) | |||
Loading…