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(MKL26Z64) update for F_PLL <= 16MHz

teensy4-core
duff2013 10 years ago
parent
commit
1fa14faf08
1 changed files with 1 additions and 1 deletions
  1. +1
    -1
      teensy3/mk20dx128.c

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teensy3/mk20dx128.c View File

// C2[LP] bit is written to 1 // C2[LP] bit is written to 1
#else #else
// enable capacitors for crystal // enable capacitors for crystal
OSC0_CR = OSC_SC8P | OSC_SC2P | 0x80;
OSC0_CR = OSC_SC8P | OSC_SC2P | OSC_ERCLKEN;
// enable osc, 8-32 MHz range, low power mode // enable osc, 8-32 MHz range, low power mode
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS; MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
// switch to crystal as clock source, FLL input = 16 MHz / 512 // switch to crystal as clock source, FLL input = 16 MHz / 512

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