Update defs for extra pins

teensy4/analog.c

 	1,	// 24/A10 AD_B0_12
 	2,	// 25/A11 AD_B0_13
 	128+3,	// 26/A12 AD_B1_14 - only on ADC2, 3
-	128+4	// 27/A13 AD_B1_15 - only on ADC2, 4
+	128+4,	// 27/A13 AD_B1_15 - only on ADC2, 4
+#ifdef ARDUINO_TEENSY41
+	255,	// 28
+	255,	// 29
+	255,	// 30
+	255,	// 31
+	255,	// 32
+	255,	// 33
+	255,	// 34
+	255,	// 35
+	255,	// 36
+	255,	// 37
+	128+1,	// 38/A14 AD_B1_12 - only on ADC2, 1
+	128+2,	// 39/A15 AD_B1_13 - only on ADC2, 2
+	9,	// 40/A16 AD_B1_04
+	10,	// 41/A17 AD_B1_05
+#endif
 };
 
 
 	if (pin > sizeof(pin_to_channel)) return 0;
 	if (calibrating) wait_for_cal();
 	uint8_t ch = pin_to_channel[pin];
+	if (ch == 255) return 0;
 //	printf("%d\n", ch);
 //	if (ch > 15) return 0;
 	if(!(ch & 0x80)) {

teensy4/core_pins.h

 
 #elif defined(__IMXRT1062__) && defined(ARDUINO_TEENSY41)
 
-#define CORE_NUM_TOTAL_PINS	48
-#define CORE_NUM_DIGITAL	48
-#define CORE_NUM_INTERRUPT	48
+#define CORE_NUM_TOTAL_PINS	55
+#define CORE_NUM_DIGITAL	55
+#define CORE_NUM_INTERRUPT	55
 #define CORE_NUM_ANALOG		18
-#define CORE_NUM_PWM		29
+#define CORE_NUM_PWM		31
 
 #define CORE_PIN0_BIT		3
 #define CORE_PIN1_BIT		2
 #define CORE_PIN45_BIT		12
 #define CORE_PIN46_BIT		17
 #define CORE_PIN47_BIT		16
+#define CORE_PIN48_BIT		24
+#define CORE_PIN49_BIT		27
+#define CORE_PIN50_BIT		28
+#define CORE_PIN51_BIT		22
+#define CORE_PIN52_BIT		26
+#define CORE_PIN53_BIT		25
+#define CORE_PIN54_BIT		29
 
 #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
 #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
 #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
 #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
 #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
+#define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
+#define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
+#define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
+#define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
+#define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
+#define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
+#define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
 
 // Fast GPIO
 #define CORE_PIN0_PORTREG	GPIO6_DR
 #define CORE_PIN45_PORTREG	GPIO8_DR
 #define CORE_PIN46_PORTREG	GPIO8_DR
 #define CORE_PIN47_PORTREG	GPIO8_DR
+#define CORE_PIN48_PORTREG	GPIO9_DR
+#define CORE_PIN49_PORTREG	GPIO9_DR
+#define CORE_PIN50_PORTREG	GPIO9_DR
+#define CORE_PIN51_PORTREG	GPIO9_DR
+#define CORE_PIN52_PORTREG	GPIO9_DR
+#define CORE_PIN53_PORTREG	GPIO9_DR
+#define CORE_PIN54_PORTREG	GPIO9_DR
 
 #define CORE_PIN0_PORTSET	GPIO6_DR_SET
 #define CORE_PIN1_PORTSET	GPIO6_DR_SET
 #define CORE_PIN45_PORTSET	GPIO8_DR_SET
 #define CORE_PIN46_PORTSET	GPIO8_DR_SET
 #define CORE_PIN47_PORTSET	GPIO8_DR_SET
+#define CORE_PIN48_PORTSET	GPIO9_DR_SET
+#define CORE_PIN49_PORTSET	GPIO9_DR_SET
+#define CORE_PIN50_PORTSET	GPIO9_DR_SET
+#define CORE_PIN51_PORTSET	GPIO9_DR_SET
+#define CORE_PIN52_PORTSET	GPIO9_DR_SET
+#define CORE_PIN53_PORTSET	GPIO9_DR_SET
+#define CORE_PIN54_PORTSET	GPIO9_DR_SET
 
 #define CORE_PIN0_PORTCLEAR	GPIO6_DR_CLEAR
 #define CORE_PIN1_PORTCLEAR	GPIO6_DR_CLEAR
 #define CORE_PIN45_PORTCLEAR	GPIO8_DR_CLEAR
 #define CORE_PIN46_PORTCLEAR	GPIO8_DR_CLEAR
 #define CORE_PIN47_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN48_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN49_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN50_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN51_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN52_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN53_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN54_PORTCLEAR	GPIO9_DR_CLEAR
 
 #define CORE_PIN0_DDRREG	GPIO6_GDIR
 #define CORE_PIN1_DDRREG	GPIO6_GDIR
 #define CORE_PIN45_DDRREG	GPIO8_GDIR
 #define CORE_PIN46_DDRREG	GPIO8_GDIR
 #define CORE_PIN47_DDRREG	GPIO8_GDIR
+#define CORE_PIN48_DDRREG	GPIO9_GDIR
+#define CORE_PIN49_DDRREG	GPIO9_GDIR
+#define CORE_PIN50_DDRREG	GPIO9_GDIR
+#define CORE_PIN51_DDRREG	GPIO9_GDIR
+#define CORE_PIN52_DDRREG	GPIO9_GDIR
+#define CORE_PIN53_DDRREG	GPIO9_GDIR
+#define CORE_PIN54_DDRREG	GPIO9_GDIR
 
 #define CORE_PIN0_PINREG	GPIO6_PSR
 #define CORE_PIN1_PINREG	GPIO6_PSR
 #define CORE_PIN45_PINREG	GPIO8_PSR
 #define CORE_PIN46_PINREG	GPIO8_PSR
 #define CORE_PIN47_PINREG	GPIO8_PSR
-
-
+#define CORE_PIN48_PINREG	GPIO9_PSR
+#define CORE_PIN49_PINREG	GPIO9_PSR
+#define CORE_PIN50_PINREG	GPIO9_PSR
+#define CORE_PIN51_PINREG	GPIO9_PSR
+#define CORE_PIN52_PINREG	GPIO9_PSR
+#define CORE_PIN53_PINREG	GPIO9_PSR
+#define CORE_PIN54_PINREG	GPIO9_PSR
 
 // mux config registers control which peripheral uses the pin
 #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
 #define CORE_PIN45_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
 #define CORE_PIN46_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
 #define CORE_PIN47_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
+#define CORE_PIN48_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
+#define CORE_PIN49_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
+#define CORE_PIN50_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
+#define CORE_PIN51_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
+#define CORE_PIN52_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
+#define CORE_PIN53_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
+#define CORE_PIN54_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
 
 // pad config registers control pullup/pulldown/keeper, drive strength, etc
 #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
 #define CORE_PIN45_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
 #define CORE_PIN46_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
 #define CORE_PIN47_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
+#define CORE_PIN48_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
+#define CORE_PIN49_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
+#define CORE_PIN50_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
+#define CORE_PIN51_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
+#define CORE_PIN52_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
+#define CORE_PIN53_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
+#define CORE_PIN54_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
 
 #define CORE_LED0_PIN		13
 
 #define CORE_INT45_PIN		45
 #define CORE_INT46_PIN		46
 #define CORE_INT47_PIN		47
+#define CORE_INT48_PIN		48
+#define CORE_INT49_PIN		49
+#define CORE_INT50_PIN		50
+#define CORE_INT51_PIN		51
+#define CORE_INT52_PIN		52
+#define CORE_INT53_PIN		53
+#define CORE_INT54_PIN		54
 #define CORE_INT_EVERY_PIN	1
 
 
 				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
 			} else if (pin == 33) {
 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
-#if defined(__IMXRT1062__)
 			} else if (pin == 34) {
 				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
 			} else if (pin == 35) {
 				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
 			} else if (pin == 39) {
 				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
+#if CORE_NUM_DIGITAL >= 55
+			} else if (pin == 40) {
+				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
+			} else if (pin == 41) {
+				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
+			} else if (pin == 42) {
+				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
+			} else if (pin == 43) {
+				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
+			} else if (pin == 44) {
+				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
+			} else if (pin == 45) {
+				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
+			} else if (pin == 46) {
+				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
+			} else if (pin == 47) {
+				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
+			} else if (pin == 48) {
+				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
+			} else if (pin == 49) {
+				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
+			} else if (pin == 50) {
+				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
+			} else if (pin == 51) {
+				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
+			} else if (pin == 52) {
+				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
+			} else if (pin == 53) {
+				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
+			} else if (pin == 54) {
+				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
 #endif
 			}
 		} else {
 				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
 			} else if (pin == 33) {
 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
-#if defined(__IMXRT1062__)
 			} else if (pin == 34) {
 				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
 			} else if (pin == 35) {
 				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
 			} else if (pin == 39) {
 				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
+#if CORE_NUM_DIGITAL >= 55
+			} else if (pin == 40) {
+				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
+			} else if (pin == 41) {
+				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
+			} else if (pin == 42) {
+				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
+			} else if (pin == 43) {
+				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
+			} else if (pin == 44) {
+				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
+			} else if (pin == 45) {
+				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
+			} else if (pin == 46) {
+				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
+			} else if (pin == 47) {
+				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
+			} else if (pin == 48) {
+				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
+			} else if (pin == 49) {
+				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
+			} else if (pin == 50) {
+				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
+			} else if (pin == 51) {
+				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
+			} else if (pin == 52) {
+				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
+			} else if (pin == 53) {
+				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
+			} else if (pin == 54) {
+				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
 #endif
 			}
 		}
 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
 		} else if (pin == 33) {
 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
+		} else if (pin == 34) {
+			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
+		} else if (pin == 35) {
+			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
+		} else if (pin == 36) {
+			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
+		} else if (pin == 37) {
+			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
+		} else if (pin == 38) {
+			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
+		} else if (pin == 39) {
+			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
+#if CORE_NUM_DIGITAL >= 55
+		} else if (pin == 40) {
+			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
+		} else if (pin == 41) {
+			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
+		} else if (pin == 42) {
+			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
+		} else if (pin == 43) {
+			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
+		} else if (pin == 44) {
+			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
+		} else if (pin == 45) {
+			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
+		} else if (pin == 46) {
+			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
+		} else if (pin == 47) {
+			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
+		} else if (pin == 48) {
+			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
+		} else if (pin == 49) {
+			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
+		} else if (pin == 50) {
+			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
+		} else if (pin == 51) {
+			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
+		} else if (pin == 52) {
+			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
+		} else if (pin == 53) {
+			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
+		} else if (pin == 54) {
+			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
+#endif
 		} else {
 			return 0;
 		}

teensy4/digital.c

 	{&CORE_PIN45_PORTREG, &CORE_PIN45_CONFIG, &CORE_PIN45_PADCONFIG, CORE_PIN45_BITMASK},
 	{&CORE_PIN46_PORTREG, &CORE_PIN46_CONFIG, &CORE_PIN46_PADCONFIG, CORE_PIN46_BITMASK},
 	{&CORE_PIN47_PORTREG, &CORE_PIN47_CONFIG, &CORE_PIN47_PADCONFIG, CORE_PIN47_BITMASK},
+	{&CORE_PIN48_PORTREG, &CORE_PIN48_CONFIG, &CORE_PIN48_PADCONFIG, CORE_PIN48_BITMASK},
+	{&CORE_PIN49_PORTREG, &CORE_PIN49_CONFIG, &CORE_PIN49_PADCONFIG, CORE_PIN49_BITMASK},
+	{&CORE_PIN50_PORTREG, &CORE_PIN50_CONFIG, &CORE_PIN50_PADCONFIG, CORE_PIN50_BITMASK},
+	{&CORE_PIN51_PORTREG, &CORE_PIN51_CONFIG, &CORE_PIN51_PADCONFIG, CORE_PIN51_BITMASK},
+	{&CORE_PIN52_PORTREG, &CORE_PIN52_CONFIG, &CORE_PIN52_PADCONFIG, CORE_PIN52_BITMASK},
+	{&CORE_PIN53_PORTREG, &CORE_PIN53_CONFIG, &CORE_PIN53_PADCONFIG, CORE_PIN53_BITMASK},
+	{&CORE_PIN54_PORTREG, &CORE_PIN54_CONFIG, &CORE_PIN54_PADCONFIG, CORE_PIN54_BITMASK},
 #endif
 };
 

teensy4/pins_arduino.h

 const static uint8_t A11 = PIN_A11;
 const static uint8_t A12 = PIN_A12;
 const static uint8_t A13 = PIN_A13;
+#ifdef ARDUINO_TEENSY41
+#define PIN_A14 (38)
+#define PIN_A15 (39)
+#define PIN_A16 (40)
+#define PIN_A17 (41)
+const static uint8_t A14 = PIN_A14;
+const static uint8_t A15 = PIN_A15;
+const static uint8_t A16 = PIN_A16;
+const static uint8_t A17 = PIN_A17;
+#endif
 
 #define LED_BUILTIN   (13)
 

teensy4/pwm.c

 	{0, M(1, 0), 0, 0},
 	{0, M(1, 0), 0, 0},
 	{1, M(2, 0), 2, 1},  // FlexPWM2_0_B  33  // EMC_07
-	{1, M(1, 1), 2, 1},	 // FlexPWM1_1_B  34  // SD_B0_03
-	{1, M(1, 1), 1, 1},	 // FlexPWM1_1_A  35  // SD_B0_02
-	{1, M(1, 0), 2, 1},	 // FlexPWM1_0_B  36  // SD_B0_01
-	{1, M(1, 0), 1, 1},	 // FlexPWM1_0_A  37  // SD_B0_00
-	{1, M(1, 2), 2, 1},	 // FlexPWM1_2_B  38  // SD_B0_05
-	{1, M(1, 2), 1, 1},	 // FlexPWM1_2_A  39  // SD_B0_04
+#ifdef ARDUINO_TEENSY40
+	{1, M(1, 1), 2, 1},  // FlexPWM1_1_B  34  // SD_B0_03
+	{1, M(1, 1), 1, 1},  // FlexPWM1_1_A  35  // SD_B0_02
+	{1, M(1, 0), 2, 1},  // FlexPWM1_0_B  36  // SD_B0_01
+	{1, M(1, 0), 1, 1},  // FlexPWM1_0_A  37  // SD_B0_00
+	{1, M(1, 2), 2, 1},  // FlexPWM1_2_B  38  // SD_B0_05
+	{1, M(1, 2), 1, 1},  // FlexPWM1_2_A  39  // SD_B0_04
+#endif
+#ifdef ARDUINO_TEENSY41
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{1, M(2, 3), 1, 6},  // FlexPWM2_3_A  36  // B1_00
+	{1, M(2, 3), 2, 6},  // FlexPWM2_3_B  37  // B1_01
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{1, M(1, 1), 2, 1},  // FlexPWM1_1_B  42  // SD_B0_03
+	{1, M(1, 1), 1, 1},  // FlexPWM1_1_A  43  // SD_B0_02
+	{1, M(1, 0), 2, 1},  // FlexPWM1_0_B  44  // SD_B0_01
+	{1, M(1, 0), 1, 1},  // FlexPWM1_0_A  45  // SD_B0_00
+	{1, M(1, 2), 2, 1},  // FlexPWM1_2_B  46  // SD_B0_05
+	{1, M(1, 2), 1, 1},  // FlexPWM1_2_A  47  // SD_B0_04
+	{0, M(1, 0), 0, 0},  // duplicate FlexPWM1_0_B
+	{0, M(1, 0), 0, 0},  // duplicate FlexPWM1_2_A
+	{0, M(1, 0), 0, 0},  // duplicate FlexPWM1_2_B
+	{1, M(3, 3), 2, 1},  // FlexPWM3_3_B  51  // EMC_22
+	{0, M(1, 0), 0, 0},  // duplicate FlexPWM1_1_B
+	{0, M(1, 0), 0, 0},  // duplicate FlexPWM1_1_A
+	{1, M(3, 0), 1, 1},  // FlexPWM3_0_A  53  // EMC_29
+#endif
 };
 
 #endif // __IMXRT1062__