Add DMAChannel for IMXRT

teensy4/DMAChannel.cpp

@@ -0,0 +1,145 @@
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2017 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "DMAChannel.h"
+
+// only 16 channels supported, because we don't handle sharing interrupts
+#define DMA_MAX_CHANNELS 16
+
+// The channel allocation bitmask is accessible from "C" namespace,
+// so C-only code can reserve DMA channels
+uint16_t dma_channel_allocated_mask = 0;
+
+#ifdef CR
+#warning "CR is defined as something?"
+#endif
+
+
+void DMAChannel::begin(bool force_initialization)
+{
+	uint32_t ch = 0;
+
+	__disable_irq();
+	if (!force_initialization && TCD && channel < DMA_MAX_CHANNELS
+	  && (dma_channel_allocated_mask & (1 << channel))
+	  && (uint32_t)TCD == (uint32_t)(0x400E9000 + channel * 32)) {
+		// DMA channel already allocated
+		__enable_irq();
+		return;
+	}
+	while (1) {
+		if (!(dma_channel_allocated_mask & (1 << ch))) {
+			dma_channel_allocated_mask |= (1 << ch);
+			__enable_irq();
+			break;
+		}
+		if (++ch >= DMA_MAX_CHANNELS) {
+			__enable_irq();
+			TCD = (TCD_t *)0;
+			channel = DMA_MAX_CHANNELS;
+			return; // no more channels available
+			// attempts to use this object will hardfault
+		}
+	}
+	channel = ch;
+
+	CCM_CCGR5 |= CCM_CCGR5_DMA(CCM_CCGR_ON);
+	DMA_CR = DMA_CR_GRP1PRI | DMA_CR_EMLM | DMA_CR_EDBG;
+	DMA_CERQ = ch;
+	DMA_CERR = ch;
+	DMA_CEEI = ch;
+	DMA_CINT = ch;
+	TCD = (TCD_t *)(0x400E9000 + ch * 32);
+	uint32_t *p = (uint32_t *)TCD;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+	*p++ = 0;
+}
+
+void DMAChannel::release(void)
+{
+	if (channel >= DMA_MAX_CHANNELS) return;
+	DMA_CERQ = channel;
+	__disable_irq();
+	dma_channel_allocated_mask &= ~(1 << channel);
+	__enable_irq();
+	channel = DMA_MAX_CHANNELS;
+	TCD = (TCD_t *)0;
+}
+
+static uint32_t priority(const DMAChannel &c)
+{
+	uint32_t n;
+	n = *(uint32_t *)((uint32_t)&DMA_DCHPRI3 + (c.channel & 0xFC));
+	n = __builtin_bswap32(n);
+	return (n >> ((c.channel & 0x03) << 3)) & 0x0F;
+}
+
+static void swap(DMAChannel &c1, DMAChannel &c2)
+{
+	uint8_t c;
+	DMABaseClass::TCD_t *t;
+
+	c = c1.channel;
+	c1.channel = c2.channel;
+	c2.channel = c;
+	t = c1.TCD;
+	c1.TCD = c2.TCD;
+	c2.TCD = t;
+}
+
+
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2)
+{
+	if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
+}
+
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3)
+{
+	if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
+	if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
+	if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
+}
+
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3, DMAChannel &ch4)
+{
+	if (priority(ch3) < priority(ch4)) swap(ch3, ch4);
+	if (priority(ch2) < priority(ch3)) swap(ch2, ch3);
+	if (priority(ch1) < priority(ch2)) swap(ch1, ch2);
+	if (priority(ch3) < priority(ch4)) swap(ch2, ch3);
+	if (priority(ch2) < priority(ch3)) swap(ch1, ch2);
+	if (priority(ch3) < priority(ch4)) swap(ch2, ch3);
+}
+

teensy4/DMAChannel.h

@@ -0,0 +1,605 @@
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2017 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef DMAChannel_h_
+#define DMAChannel_h_
+
+#include "imxrt.h"
+
+// Discussion about DMAChannel is here:
+// http://forum.pjrc.com/threads/25778-Could-there-be-something-like-an-ISR-template-function/page3
+
+#define DMACHANNEL_HAS_BEGIN
+#define DMACHANNEL_HAS_BOOLEAN_CTOR
+
+
+// The channel allocation bitmask is accessible from "C" namespace,
+// so C-only code can reserve DMA channels
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern uint16_t dma_channel_allocated_mask;
+#ifdef __cplusplus
+}
+#endif
+
+
+#ifdef __cplusplus
+
+// known libraries with DMA usage (in need of porting to this new scheme):
+//
+// https://github.com/PaulStoffregen/Audio
+// https://github.com/PaulStoffregen/OctoWS2811
+// https://github.com/pedvide/ADC
+// https://github.com/duff2013/SerialEvent
+// https://github.com/pixelmatix/SmartMatrix
+// https://github.com/crteensy/DmaSpi <-- DmaSpi has adopted this scheme
+
+
+class DMABaseClass {
+public:
+	typedef struct __attribute__((packed, aligned(4))) {
+		volatile const void * volatile SADDR;
+		int16_t SOFF;
+		union { uint16_t ATTR;
+			struct { uint8_t ATTR_DST; uint8_t ATTR_SRC; }; };
+		union { uint32_t NBYTES; uint32_t NBYTES_MLNO;
+			uint32_t NBYTES_MLOFFNO; uint32_t NBYTES_MLOFFYES; };
+		int32_t SLAST;
+		volatile void * volatile DADDR;
+		int16_t DOFF;
+		union { volatile uint16_t CITER;
+			volatile uint16_t CITER_ELINKYES; volatile uint16_t CITER_ELINKNO; };
+		int32_t DLASTSGA;
+		volatile uint16_t CSR;
+		union { volatile uint16_t BITER;
+			volatile uint16_t BITER_ELINKYES; volatile uint16_t BITER_ELINKNO; };
+	} TCD_t;
+	TCD_t *TCD;
+
+	/***************************************/
+	/**    Data Transfer                  **/
+	/***************************************/
+
+	// Use a single variable as the data source.  Typically a register
+	// for receiving data from one of the hardware peripherals is used.
+	void source(volatile const signed char &p) { source(*(volatile const uint8_t *)&p); }
+	void source(volatile const unsigned char &p) {
+		TCD->SADDR = &p;
+		TCD->SOFF = 0;
+		TCD->ATTR_SRC = 0;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;
+		TCD->SLAST = 0;
+	}
+	void source(volatile const signed short &p) { source(*(volatile const uint16_t *)&p); }
+	void source(volatile const unsigned short &p) {
+		TCD->SADDR = &p;
+		TCD->SOFF = 0;
+		TCD->ATTR_SRC = 1;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;
+		TCD->SLAST = 0;
+	}
+	void source(volatile const signed int &p) { source(*(volatile const uint32_t *)&p); }
+	void source(volatile const unsigned int &p) { source(*(volatile const uint32_t *)&p); }
+	void source(volatile const signed long &p) { source(*(volatile const uint32_t *)&p); }
+	void source(volatile const unsigned long &p) {
+		TCD->SADDR = &p;
+		TCD->SOFF = 0;
+		TCD->ATTR_SRC = 2;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;
+		TCD->SLAST = 0;
+	}
+
+	// Use a buffer (array of data) as the data source.  Typically a
+	// buffer for transmitting data is used.
+	void sourceBuffer(volatile const signed char p[], unsigned int len) {
+		sourceBuffer((volatile const uint8_t *)p, len); }
+	void sourceBuffer(volatile const unsigned char p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 1;
+		TCD->ATTR_SRC = 0;
+		TCD->NBYTES = 1;
+		TCD->SLAST = -len;
+		TCD->BITER = len;
+		TCD->CITER = len;
+	}
+	void sourceBuffer(volatile const signed short p[], unsigned int len) {
+		sourceBuffer((volatile const uint16_t *)p, len); }
+	void sourceBuffer(volatile const unsigned short p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 2;
+		TCD->ATTR_SRC = 1;
+		TCD->NBYTES = 2;
+		TCD->SLAST = -len;
+		TCD->BITER = len / 2;
+		TCD->CITER = len / 2;
+	}
+	void sourceBuffer(volatile const signed int p[], unsigned int len) {
+		sourceBuffer((volatile const uint32_t *)p, len); }
+	void sourceBuffer(volatile const unsigned int p[], unsigned int len) {
+		sourceBuffer((volatile const uint32_t *)p, len); }
+	void sourceBuffer(volatile const signed long p[], unsigned int len) {
+		sourceBuffer((volatile const uint32_t *)p, len); }
+	void sourceBuffer(volatile const unsigned long p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 4;
+		TCD->ATTR_SRC = 2;
+		TCD->NBYTES = 4;
+		TCD->SLAST = -len;
+		TCD->BITER = len / 4;
+		TCD->CITER = len / 4;
+	}
+
+	// Use a circular buffer as the data source
+	void sourceCircular(volatile const signed char p[], unsigned int len) {
+		sourceCircular((volatile const uint8_t *)p, len); }
+	void sourceCircular(volatile const unsigned char p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 1;
+		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3);
+		TCD->NBYTES = 1;
+		TCD->SLAST = 0;
+		TCD->BITER = len;
+		TCD->CITER = len;
+	}
+	void sourceCircular(volatile const signed short p[], unsigned int len) {
+		sourceCircular((volatile const uint16_t *)p, len); }
+	void sourceCircular(volatile const unsigned short p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 2;
+		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 1;
+		TCD->NBYTES = 2;
+		TCD->SLAST = 0;
+		TCD->BITER = len / 2;
+		TCD->CITER = len / 2;
+	}
+	void sourceCircular(volatile const signed int p[], unsigned int len) {
+		sourceCircular((volatile const uint32_t *)p, len); }
+	void sourceCircular(volatile const unsigned int p[], unsigned int len) {
+		sourceCircular((volatile const uint32_t *)p, len); }
+	void sourceCircular(volatile const signed long p[], unsigned int len) {
+		sourceCircular((volatile const uint32_t *)p, len); }
+	void sourceCircular(volatile const unsigned long p[], unsigned int len) {
+		TCD->SADDR = p;
+		TCD->SOFF = 4;
+		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 2;
+		TCD->NBYTES = 4;
+		TCD->SLAST = 0;
+		TCD->BITER = len / 4;
+		TCD->CITER = len / 4;
+	}
+
+	// Use a single variable as the data destination.  Typically a register
+	// for transmitting data to one of the hardware peripherals is used.
+	void destination(volatile signed char &p) { destination(*(volatile uint8_t *)&p); }
+	void destination(volatile unsigned char &p) {
+		TCD->DADDR = &p;
+		TCD->DOFF = 0;
+		TCD->ATTR_DST = 0;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;
+		TCD->DLASTSGA = 0;
+	}
+	void destination(volatile signed short &p) { destination(*(volatile uint16_t *)&p); }
+	void destination(volatile unsigned short &p) {
+		TCD->DADDR = &p;
+		TCD->DOFF = 0;
+		TCD->ATTR_DST = 1;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;
+		TCD->DLASTSGA = 0;
+	}
+	void destination(volatile signed int &p) { destination(*(volatile uint32_t *)&p); }
+	void destination(volatile unsigned int &p) { destination(*(volatile uint32_t *)&p); }
+	void destination(volatile signed long &p) { destination(*(volatile uint32_t *)&p); }
+	void destination(volatile unsigned long &p) {
+		TCD->DADDR = &p;
+		TCD->DOFF = 0;
+		TCD->ATTR_DST = 2;
+		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;
+		TCD->DLASTSGA = 0;
+	}
+
+	// Use a buffer (array of data) as the data destination.  Typically a
+	// buffer for receiving data is used.
+	void destinationBuffer(volatile signed char p[], unsigned int len) {
+		destinationBuffer((volatile uint8_t *)p, len); }
+	void destinationBuffer(volatile unsigned char p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 1;
+		TCD->ATTR_DST = 0;
+		TCD->NBYTES = 1;
+		TCD->DLASTSGA = -len;
+		TCD->BITER = len;
+		TCD->CITER = len;
+	}
+	void destinationBuffer(volatile signed short p[], unsigned int len) {
+		destinationBuffer((volatile uint16_t *)p, len); }
+	void destinationBuffer(volatile unsigned short p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 2;
+		TCD->ATTR_DST = 1;
+		TCD->NBYTES = 2;
+		TCD->DLASTSGA = -len;
+		TCD->BITER = len / 2;
+		TCD->CITER = len / 2;
+	}
+	void destinationBuffer(volatile signed int p[], unsigned int len) {
+		destinationBuffer((volatile uint32_t *)p, len); }
+	void destinationBuffer(volatile unsigned int p[], unsigned int len) {
+		destinationBuffer((volatile uint32_t *)p, len); }
+	void destinationBuffer(volatile signed long p[], unsigned int len) {
+		destinationBuffer((volatile uint32_t *)p, len); }
+	void destinationBuffer(volatile unsigned long p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 4;
+		TCD->ATTR_DST = 2;
+		TCD->NBYTES = 4;
+		TCD->DLASTSGA = -len;
+		TCD->BITER = len / 4;
+		TCD->CITER = len / 4;
+	}
+
+	// Use a circular buffer as the data destination
+	void destinationCircular(volatile signed char p[], unsigned int len) {
+		destinationCircular((volatile uint8_t *)p, len); }
+	void destinationCircular(volatile unsigned char p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 1;
+		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3);
+		TCD->NBYTES = 1;
+		TCD->DLASTSGA = 0;
+		TCD->BITER = len;
+		TCD->CITER = len;
+	}
+	void destinationCircular(volatile signed short p[], unsigned int len) {
+		destinationCircular((volatile uint16_t *)p, len); }
+	void destinationCircular(volatile unsigned short p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 2;
+		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 1;
+		TCD->NBYTES = 2;
+		TCD->DLASTSGA = 0;
+		TCD->BITER = len / 2;
+		TCD->CITER = len / 2;
+	}
+	void destinationCircular(volatile signed int p[], unsigned int len) {
+		destinationCircular((volatile uint32_t *)p, len); }
+	void destinationCircular(volatile unsigned int p[], unsigned int len) {
+		destinationCircular((volatile uint32_t *)p, len); }
+	void destinationCircular(volatile signed long p[], unsigned int len) {
+		destinationCircular((volatile uint32_t *)p, len); }
+	void destinationCircular(volatile unsigned long p[], unsigned int len) {
+		TCD->DADDR = p;
+		TCD->DOFF = 4;
+		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 2;
+		TCD->NBYTES = 4;
+		TCD->DLASTSGA = 0;
+		TCD->BITER = len / 4;
+		TCD->CITER = len / 4;
+	}
+
+	/*************************************************/
+	/**    Quantity of Data to Transfer             **/
+	/*************************************************/
+
+	// Set the data size used for each triggered transfer
+	void transferSize(unsigned int len) {
+		if (len == 16) {
+			TCD->NBYTES = 16;
+			if (TCD->SOFF != 0) TCD->SOFF = 16;
+			if (TCD->DOFF != 0) TCD->DOFF = 16;
+			TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0404;
+		} else if (len == 4) {
+			TCD->NBYTES = 4;
+			if (TCD->SOFF != 0) TCD->SOFF = 4;
+			if (TCD->DOFF != 0) TCD->DOFF = 4;
+			TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0202;
+		} else if (len == 2) {
+			TCD->NBYTES = 2;
+			if (TCD->SOFF != 0) TCD->SOFF = 2;
+			if (TCD->DOFF != 0) TCD->DOFF = 2;
+			TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0101;
+		} else {
+			TCD->NBYTES = 1;
+			if (TCD->SOFF != 0) TCD->SOFF = 1;
+			if (TCD->DOFF != 0) TCD->DOFF = 1;
+			TCD->ATTR = TCD->ATTR & 0xF8F8;
+		}
+	}
+
+	// Set the number of transfers (number of triggers until complete)
+	void transferCount(unsigned int len) {
+		if (!(TCD->BITER & DMA_TCD_BITER_ELINK)) {
+			if (len > 32767) return;
+			TCD->BITER = len;
+			TCD->CITER = len;
+		} else {
+			if (len > 511) return;
+			TCD->BITER = (TCD->BITER & 0xFE00) | len;
+			TCD->CITER = (TCD->CITER & 0xFE00) | len;
+		}
+	}
+
+	/*************************************************/
+	/**    Special Options / Features               **/
+	/*************************************************/
+
+	void interruptAtCompletion(void) {
+		TCD->CSR |= DMA_TCD_CSR_INTMAJOR;
+	}
+
+	void interruptAtHalf(void) {
+		TCD->CSR |= DMA_TCD_CSR_INTHALF;
+	}
+
+	void disableOnCompletion(void) {
+		TCD->CSR |= DMA_TCD_CSR_DREQ;
+	}
+
+	void replaceSettingsOnCompletion(const DMABaseClass &settings) {
+		TCD->DLASTSGA = (int32_t)(settings.TCD);
+		TCD->CSR &= ~DMA_TCD_CSR_DONE;
+		TCD->CSR |= DMA_TCD_CSR_ESG;
+	}
+
+protected:
+	// users should not be able to create instances of DMABaseClass, which
+	// require the inheriting class to initialize the TCD pointer.
+	DMABaseClass() {}
+
+	static inline void copy_tcd(TCD_t *dst, const TCD_t *src) {
+		const uint32_t *p = (const uint32_t *)src;
+		uint32_t *q = (uint32_t *)dst;
+		uint32_t t1, t2, t3, t4;
+		t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;
+		*q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;
+		t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;
+		*q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;
+	}
+};
+
+
+// DMASetting represents settings stored only in memory, which can be
+// applied to any DMA channel.
+
+class DMASetting : public DMABaseClass {
+public:
+	DMASetting() {
+		TCD = &tcddata;
+	}
+	DMASetting(const DMASetting &c) {
+		TCD = &tcddata;
+		*this = c;
+	}
+	DMASetting(const DMABaseClass &c) {
+		TCD = &tcddata;
+		*this = c;
+	}
+	DMASetting & operator = (const DMABaseClass &rhs) {
+		copy_tcd(TCD, rhs.TCD);
+		return *this;
+	}
+private:
+	TCD_t tcddata __attribute__((aligned(32)));
+};
+
+
+// DMAChannel reprents an actual DMA channel and its current settings
+
+class DMAChannel : public DMABaseClass {
+public:
+	/*************************************************/
+	/**    Channel Allocation                       **/
+	/*************************************************/
+
+	DMAChannel() {
+		begin();
+	}
+	DMAChannel(const DMAChannel &c) {
+		TCD = c.TCD;
+		channel = c.channel;
+	}
+	DMAChannel(const DMASetting &c) {
+		begin();
+		copy_tcd(TCD, c.TCD);
+	}
+	DMAChannel(bool allocate) {
+		if (allocate) begin();
+	}
+	DMAChannel & operator = (const DMAChannel &rhs) {
+		if (channel != rhs.channel) {
+			release();
+			TCD = rhs.TCD;
+			channel = rhs.channel;
+		}
+		return *this;
+	}
+	DMAChannel & operator = (const DMASetting &rhs) {
+		copy_tcd(TCD, rhs.TCD);
+		return *this;
+	}
+	~DMAChannel() {
+		release();
+	}
+	void begin(bool force_initialization = false);
+private:
+	void release(void);
+
+public:
+	/***************************************/
+	/**    Triggering                     **/
+	/***************************************/
+
+	// Triggers cause the DMA channel to actually move data.  Each
+	// trigger moves a single data unit, which is typically 8, 16 or
+	// 32 bits.  If a channel is configured for 200 transfers
+
+	// Use a hardware trigger to make the DMA channel run
+	void triggerAtHardwareEvent(uint8_t source) {
+		volatile uint32_t *mux = &DMAMUX_CHCFG0 + channel;
+		//mux = (volatile uint32_t *)&(DMAMUX_CHCFG0) + channel;
+		*mux = 0;
+		*mux = (source & 0x7F) | DMAMUX_CHCFG_ENBL;
+	}
+
+	// Use another DMA channel as the trigger, causing this
+	// channel to trigger after each transfer is makes, except
+	// the its last transfer.  This effectively makes the 2
+	// channels run in parallel until the last transfer
+	void triggerAtTransfersOf(DMABaseClass &ch) {
+		ch.TCD->BITER = (ch.TCD->BITER & ~DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
+		  | DMA_TCD_BITER_ELINKYES_LINKCH(channel) | DMA_TCD_BITER_ELINKYES_ELINK;
+		ch.TCD->CITER = ch.TCD->BITER ;
+	}
+
+	// Use another DMA channel as the trigger, causing this
+	// channel to trigger when the other channel completes.
+	void triggerAtCompletionOf(DMABaseClass &ch) {
+		ch.TCD->CSR = (ch.TCD->CSR & ~(DMA_TCD_CSR_MAJORLINKCH_MASK|DMA_TCD_CSR_DONE))
+		  | DMA_TCD_CSR_MAJORLINKCH(channel) | DMA_TCD_CSR_MAJORELINK;
+	}
+
+	// Cause this DMA channel to be continuously triggered, so
+	// it will move data as rapidly as possible, without waiting.
+	// Normally this would be used with disableOnCompletion().
+	void triggerContinuously(void) {
+		// TODO: update this for IMXRT.  On Kinetis, a small handful
+		// of DMAMUX slots were dedicated to "always on".  On IMXRT,
+		// all of them can work as "always on" by setting their
+		// DMAMUX_CHCFG_A_ON bit.
+#if 0
+		volatile uint8_t *mux = (volatile uint8_t *)&DMAMUX0_CHCFG0;
+		mux[channel] = 0;
+#if DMAMUX_NUM_SOURCE_ALWAYS >= DMA_NUM_CHANNELS
+		mux[channel] = DMAMUX_SOURCE_ALWAYS0 + channel;	
+#else
+		// search for an unused "always on" source
+		unsigned int i = DMAMUX_SOURCE_ALWAYS0;
+		for (i = DMAMUX_SOURCE_ALWAYS0;
+		  i < DMAMUX_SOURCE_ALWAYS0 + DMAMUX_NUM_SOURCE_ALWAYS; i++) {
+			unsigned int ch;
+			for (ch=0; ch < DMA_NUM_CHANNELS; ch++) {
+				if (mux[ch] == i) break;
+			}
+			if (ch >= DMA_NUM_CHANNELS) {
+				mux[channel] = (i | DMAMUX_ENABLE);
+				return;
+			}
+		}
+#endif
+#endif
+	}
+
+	// Manually trigger the DMA channel.
+	void triggerManual(void) {
+		DMA_SSRT = channel;
+	}
+
+
+	/***************************************/
+	/**    Interrupts                     **/
+	/***************************************/
+
+	// An interrupt routine can be run when the DMA channel completes
+	// the entire transfer, and also optionally when half of the
+	// transfer is completed.
+	void attachInterrupt(void (*isr)(void)) {
+		_VectorsRam[channel + IRQ_DMA_CH0 + 16] = isr;
+		NVIC_ENABLE_IRQ(IRQ_DMA_CH0 + channel);
+	}
+
+	void detachInterrupt(void) {
+		NVIC_DISABLE_IRQ(IRQ_DMA_CH0 + channel);
+	}
+
+	void clearInterrupt(void) {
+		DMA_CINT = channel;
+	}
+
+
+	/***************************************/
+	/**    Enable / Disable               **/
+	/***************************************/
+
+	void enable(void) {
+		DMA_SERQ = channel;
+	}
+	void disable(void) {
+		DMA_CERQ = channel;
+	}
+
+	/***************************************/
+	/**    Status                         **/
+	/***************************************/
+
+	bool complete(void) {
+		if (TCD->CSR & DMA_TCD_CSR_DONE) return true;
+		return false;
+	}
+	void clearComplete(void) {
+		DMA_CDNE = channel;
+	}
+	bool error(void) {
+		if (DMA_ERR & (1<<channel)) return true;
+		return false;
+	}
+	void clearError(void) {
+		DMA_CERR = channel;
+	}
+	void * sourceAddress(void) {
+		return (void *)(TCD->SADDR);
+	}
+	void * destinationAddress(void) {
+		return (void *)(TCD->DADDR);
+	}
+
+	/***************************************/
+	/**    Direct Hardware Access         **/
+	/***************************************/
+
+	// For complex and unusual configurations not possible with the above
+	// functions, the Transfer Control Descriptor (TCD) and channel number
+	// can be used directly.  This leads to less portable and less readable
+	// code, but direct control of all parameters is possible.
+	uint8_t channel;
+	// TCD is accessible due to inheritance from DMABaseClass
+};
+
+// arrange the relative priority of 2 or more DMA channels
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2);
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3);
+void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3, DMAChannel &ch4);
+
+
+
+
+
+#endif // __cplusplus
+
+#endif // DMAChannel_h_

teensy4/EventResponder.cpp

@@ -334,6 +334,7 @@ void MillisTimer::runFromTimer()
 // code will run at lower interrupt priority for better compatibility
 // with libraries using mid-to-high priority interrupts.
 
+// TODO: this doesn't work for IMXRT - no longer using predefined names
 extern "C" volatile uint32_t systick_millis_count;
 void systick_isr(void)
 {

teensy4/imxrt.h

@@ -1548,6 +1548,9 @@ typedef struct {
 #define DMAMUX_CHCFG29			(IMXRT_DMAMUX.offset074)
 #define DMAMUX_CHCFG30			(IMXRT_DMAMUX.offset078)
 #define DMAMUX_CHCFG31			(IMXRT_DMAMUX.offset07C)
+#define DMAMUX_CHCFG_ENBL			((uint32_t)(1<<31))
+#define DMAMUX_CHCFG_TRIG			((uint32_t)(1<<30))
+#define DMAMUX_CHCFG_A_ON			((uint32_t)(1<<29))
 
 // 22.3.5.1: page 864
 typedef struct {
@@ -1609,6 +1612,7 @@ typedef struct {
 	volatile uint8_t DCHPRI29;
 	volatile uint8_t DCHPRI28;
 } IMXRT_DMA_t;
+
 typedef struct {
 	volatile const void * volatile SADDR;
 	int16_t SOFF;
@@ -1691,6 +1695,43 @@ typedef struct {
 #define DMA_DCHPRI29			(IMXRT_DMA.DCHPRI29)
 #define DMA_DCHPRI28			(IMXRT_DMA.DCHPRI28)
 
+#define DMA_CR_ACTIVE                   ((uint32_t)(1<<31))     // 1=DMA is executing
+#define DMA_CR_CX                       ((uint32_t)(1<<17))     // Cancel Transfer
+#define DMA_CR_ECX                      ((uint32_t)(1<<16))     // Error Cancel Transfer
+#define DMA_CR_GRP1PRI                  ((uint32_t)(1<<10))
+#define DMA_CR_GRP0PRI                  ((uint32_t)(1<<8))
+#define DMA_CR_EMLM                     ((uint32_t)(1<<7))      // Enable Minor Loop Mapping
+#define DMA_CR_CLM                      ((uint32_t)(1<<6))      // Continuous Link Mode
+#define DMA_CR_HALT                     ((uint32_t)(1<<5))      // Halt DMA Operations
+#define DMA_CR_HOE                      ((uint32_t)(1<<4))      // Halt On Error
+#define DMA_CR_ERGA                     ((uint32_t)(1<<3))      // Enable Round Robin Group Arb
+#define DMA_CR_ERCA                     ((uint32_t)(1<<2))      // Enable Round Robin Channel Arb
+#define DMA_CR_EDBG                     ((uint32_t)(1<<1))      // Enable Debug
+#define DMA_CEEI_CEEI(n)                ((uint8_t)(n & 0x1F))   // Clear Enable Error Interrupt
+#define DMA_CEEI_CAEE                   ((uint8_t)1<<6)         // Clear All Enable Error Interrupts
+#define DMA_CEEI_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_SEEI_SEEI(n)                ((uint8_t)(n & 0x1F))   // Set Enable Error Interrupt
+#define DMA_SEEI_SAEE                   ((uint8_t)1<<6)         // Set All Enable Error Interrupts
+#define DMA_SEEI_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_CERQ_CERQ(n)                ((uint8_t)(n & 0x1F))   // Clear Enable Request
+#define DMA_CERQ_CAER                   ((uint8_t)1<<6)         // Clear All Enable Requests
+#define DMA_CERQ_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_SERQ_SERQ(n)                ((uint8_t)(n & 0x1F))   // Set Enable Request
+#define DMA_SERQ_SAER                   ((uint8_t)1<<6)         // Set All Enable Requests
+#define DMA_SERQ_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_CDNE_CDNE(n)                ((uint8_t)(n & 0x1F))   // Clear Done Bit
+#define DMA_CDNE_CADN                   ((uint8_t)1<<6)         // Clear All Done Bits
+#define DMA_CDNE_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_SSRT_SSRT(n)                ((uint8_t)(n & 0x1F))   // Set Start Bit
+#define DMA_SSRT_SAST                   ((uint8_t)1<<6)         // Set All Start Bits
+#define DMA_SSRT_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_CERR_CERR(n)                ((uint8_t)(n & 0x1F))   // Clear Error Indicator
+#define DMA_CERR_CAEI                   ((uint8_t)1<<6)         // Clear All Error Indicators
+#define DMA_CERR_NOP                    ((uint8_t)1<<7)         // NOP
+#define DMA_CINT_CINT(n)                ((uint8_t)(n & 0x1F))   // Clear Interrupt Request
+#define DMA_CINT_CAIR                   ((uint8_t)1<<6)         // Clear All Interrupt Requests
+#define DMA_CINT_NOP                    ((uint8_t)1<<7)         // NOP
+
 #define IMXRT_DMA_TCD		((IMXRT_DMA_TCD_t *)0x400E9000)
 #define DMA_TCD0_SADDR			(IMXRT_DMA_TCD[0].SADDR)
 #define DMA_TCD0_SOFF			(IMXRT_DMA_TCD[0].SOFF)
@@ -2300,6 +2341,49 @@ typedef struct {
 #define DMA_TCD31_BITER_ELINKYES	(IMXRT_DMA_TCD[31].BITER_ELINKYES)
 #define DMA_TCD31_BITER_ELINKNO		(IMXRT_DMA_TCD[31].BITER_ELINKNO)
 
+// TODO: double check these defines from Teensy 3.x are still correct for IMXRT
+#define DMA_TCD_ATTR_SMOD(n)            (((n) & 0x1F) << 11)
+#define DMA_TCD_ATTR_SSIZE(n)           (((n) & 0x7) << 8)
+#define DMA_TCD_ATTR_DMOD(n)            (((n) & 0x1F) << 3)
+#define DMA_TCD_ATTR_DSIZE(n)           (((n) & 0x7) << 0)
+#define DMA_TCD_ATTR_SIZE_8BIT          0
+#define DMA_TCD_ATTR_SIZE_16BIT         1
+#define DMA_TCD_ATTR_SIZE_32BIT         2
+#define DMA_TCD_ATTR_SIZE_16BYTE        4
+#define DMA_TCD_ATTR_SIZE_32BYTE        5 // caution: this might not be supported in newer chips?
+#define DMA_TCD_CSR_BWC(n)              (((n) & 0x3) << 14)
+#define DMA_TCD_CSR_BWC_MASK            0xC000
+#define DMA_TCD_CSR_MAJORLINKCH(n)      (((n) & 0xF) << 8)
+#define DMA_TCD_CSR_MAJORLINKCH_MASK    0x0F00
+#define DMA_TCD_CSR_DONE                0x0080
+#define DMA_TCD_CSR_ACTIVE              0x0040
+#define DMA_TCD_CSR_MAJORELINK          0x0020
+#define DMA_TCD_CSR_ESG                 0x0010
+#define DMA_TCD_CSR_DREQ                0x0008
+#define DMA_TCD_CSR_INTHALF             0x0004
+#define DMA_TCD_CSR_INTMAJOR            0x0002
+#define DMA_TCD_CSR_START               0x0001
+#define DMA_TCD_CITER_MASK              ((uint16_t)0x7FFF)         // Loop count mask
+#define DMA_TCD_CITER_ELINK             ((uint16_t)1<<15)          // Enable channel linking on minor-loop complete
+#define DMA_TCD_BITER_MASK              ((uint16_t)0x7FFF)         // Loop count mask
+#define DMA_TCD_BITER_ELINK             ((uint16_t)1<<15)          // Enable channel linking on minor-loop complete
+#define DMA_TCD_BITER_ELINKYES_ELINK            0x8000
+#define DMA_TCD_BITER_ELINKYES_LINKCH(n)        (((n) & 0xF) << 9)
+#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK      0x1E00
+#define DMA_TCD_BITER_ELINKYES_BITER(n)         (((n) & 0x1FF) << 0)
+#define DMA_TCD_BITER_ELINKYES_BITER_MASK       0x01FF
+#define DMA_TCD_CITER_ELINKYES_ELINK            0x8000
+#define DMA_TCD_CITER_ELINKYES_LINKCH(n)        (((n) & 0xF) << 9)
+#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK      0x1E00
+#define DMA_TCD_CITER_ELINKYES_CITER(n)         (((n) & 0x1FF) << 0)
+#define DMA_TCD_CITER_ELINKYES_CITER_MASK       0x01FF
+#define DMA_TCD_NBYTES_SMLOE                ((uint32_t)1<<31)               // Source Minor Loop Offset Enable
+#define DMA_TCD_NBYTES_DMLOE                ((uint32_t)1<<30)               // Destination Minor Loop Offset Enable
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n)    ((uint32_t)((n) & 0x3FFFFFFF))  // NBytes transfer count when minor loop disabled
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n)   ((uint32_t)((n) & 0x3FF))       // NBytes transfer count when minor loop enabled
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n)    ((uint32_t)((n) & 0xFFFFF)<<10) // Minor loop offset
+
+
 // 23.7.1: page 1023
 #define IMXRT_ENC1		(*(IMXRT_REGISTER16_t *)0x403C8000)
 #define ENC1_CTRL			(IMXRT_ENC1.offset000)